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0588ed70 UH |
1 | ## |
2 | ## This file is part of the sigrok project. | |
3 | ## | |
7b86f0bc | 4 | ## Copyright (C) 2010-2011 Uwe Hermann <uwe@hermann-uwe.de> |
0588ed70 UH |
5 | ## |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, write to the Free Software | |
18 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | ## | |
20 | ||
21 | # | |
22 | # I2C protocol decoder | |
23 | # | |
24 | ||
9e587cc9 | 25 | # |
0588ed70 UH |
26 | # The Inter-Integrated Circuit (I2C) bus is a bidirectional, multi-master |
27 | # bus using two signals (SCL = serial clock line, SDA = serial data line). | |
28 | # | |
29 | # There can be many devices on the same bus. Each device can potentially be | |
30 | # master or slave (and that can change during runtime). Both slave and master | |
31 | # can potentially play the transmitter or receiver role (this can also | |
32 | # change at runtime). | |
33 | # | |
34 | # Possible maximum data rates: | |
35 | # - Standard mode: 100 kbit/s | |
36 | # - Fast mode: 400 kbit/s | |
37 | # - Fast-mode Plus: 1 Mbit/s | |
38 | # - High-speed mode: 3.4 Mbit/s | |
39 | # | |
40 | # START condition (S): SDA = falling, SCL = high | |
41 | # Repeated START condition (Sr): same as S | |
7b86f0bc | 42 | # Data bit sampling: SCL = rising |
0588ed70 UH |
43 | # STOP condition (P): SDA = rising, SCL = high |
44 | # | |
33e72c54 | 45 | # All data bytes on SDA are exactly 8 bits long (transmitted MSB-first). |
0588ed70 UH |
46 | # Each byte has to be followed by a 9th ACK/NACK bit. If that bit is low, |
47 | # that indicates an ACK, if it's high that indicates a NACK. | |
48 | # | |
49 | # After the first START condition, a master sends the device address of the | |
50 | # slave it wants to talk to. Slave addresses are 7 bits long (MSB-first). | |
33e72c54 | 51 | # After those 7 bits, a data direction bit is sent. If the bit is low that |
0588ed70 UH |
52 | # indicates a WRITE operation, if it's high that indicates a READ operation. |
53 | # | |
54 | # Later an optional 10bit slave addressing scheme was added. | |
55 | # | |
56 | # Documentation: | |
57 | # http://www.nxp.com/acrobat/literature/9398/39340011.pdf (v2.1 spec) | |
58 | # http://www.nxp.com/acrobat/usermanuals/UM10204_3.pdf (v3 spec) | |
59 | # http://en.wikipedia.org/wiki/I2C | |
60 | # | |
61 | ||
62 | # TODO: Look into arbitration, collision detection, clock synchronisation, etc. | |
63 | # TODO: Handle clock stretching. | |
64 | # TODO: Handle combined messages / repeated START. | |
65 | # TODO: Implement support for 7bit and 10bit slave addresses. | |
66 | # TODO: Implement support for inverting SDA/SCL levels (0->1 and 1->0). | |
67 | # TODO: Implement support for detecting various bus errors. | |
23fb2e12 UH |
68 | # TODO: I2C address of slaves. |
69 | # TODO: Handle multiple different I2C devices on same bus | |
70 | # -> we need to decode multiple protocols at the same time. | |
23fb2e12 | 71 | |
9e587cc9 UH |
72 | ''' |
73 | Protocol output format: | |
87998e97 | 74 | |
9e587cc9 UH |
75 | I2C packet: |
76 | [<i2c_command>, <data>, <ack_bit>] | |
87998e97 | 77 | |
9e587cc9 | 78 | <i2c_command> is one of: |
87998e97 | 79 | - 'START' (START condition) |
9e587cc9 UH |
80 | - 'START REPEAT' (Repeated START) |
81 | - 'ADDRESS READ' (Address, read) | |
82 | - 'ADDRESS WRITE' (Address, write) | |
83 | - 'DATA READ' (Data, read) | |
84 | - 'DATA WRITE' (Data, write) | |
87998e97 BV |
85 | - 'STOP' (STOP condition) |
86 | ||
9e587cc9 UH |
87 | <data> is the data or address byte associated with the 'ADDRESS*' and 'DATA*' |
88 | command. For 'START', 'START REPEAT' and 'STOP', this is None. | |
87998e97 | 89 | |
9e587cc9 UH |
90 | <ack_bit> is either 'ACK' or 'NACK', but may also be None. |
91 | ''' | |
23fb2e12 | 92 | |
677d597b | 93 | import sigrokdecode as srd |
b2c19614 | 94 | |
eb7082c9 | 95 | # Annotation feed formats |
7ce7775c BV |
96 | ANN_SHIFTED = 0 |
97 | ANN_SHIFTED_SHORT = 1 | |
98 | ANN_RAW = 2 | |
99 | ||
eb7082c9 | 100 | # Values are verbose and short annotation, respectively. |
15969949 | 101 | protocol = { |
eb7082c9 | 102 | 'START': ['START', 'S'], |
a2d2aff2 | 103 | 'START REPEAT': ['START REPEAT', 'Sr'], |
eb7082c9 UH |
104 | 'STOP': ['STOP', 'P'], |
105 | 'ACK': ['ACK', 'A'], | |
106 | 'NACK': ['NACK', 'N'], | |
a2d2aff2 UH |
107 | 'ADDRESS READ': ['ADDRESS READ', 'AR'], |
108 | 'ADDRESS WRITE': ['ADDRESS WRITE', 'AW'], | |
109 | 'DATA READ': ['DATA READ', 'DR'], | |
110 | 'DATA WRITE': ['DATA WRITE', 'DW'], | |
15969949 | 111 | } |
e5080882 | 112 | |
400f9ae7 UH |
113 | # States |
114 | FIND_START = 0 | |
115 | FIND_ADDRESS = 1 | |
116 | FIND_DATA = 2 | |
117 | ||
677d597b | 118 | class Decoder(srd.Decoder): |
a2c2afd9 | 119 | api_version = 1 |
67e847fd | 120 | id = 'i2c' |
f39d2404 | 121 | name = 'I2C' |
9a12a6e7 | 122 | longname = 'Inter-Integrated Circuit' |
f39d2404 UH |
123 | desc = 'I2C is a two-wire, multi-master, serial bus.' |
124 | longdesc = '...' | |
f39d2404 UH |
125 | license = 'gplv2+' |
126 | inputs = ['logic'] | |
127 | outputs = ['i2c'] | |
bc5f5a43 BV |
128 | probes = [ |
129 | {'id': 'scl', 'name': 'SCL', 'desc': 'Serial clock line'}, | |
130 | {'id': 'sda', 'name': 'SDA', 'desc': 'Serial data line'}, | |
131 | ] | |
b77614bc | 132 | optional_probes = [] |
f39d2404 | 133 | options = { |
ea90233e | 134 | 'addressing': ['Slave addressing (in bits)', 7], # 7 or 10 |
ad2dc0de | 135 | } |
e97b6ef5 | 136 | annotations = [ |
15969949 | 137 | # ANN_SHIFTED |
eb7082c9 UH |
138 | ['7-bit shifted hex', |
139 | 'Read/write bit shifted out from the 8-bit I2C slave address'], | |
15969949 | 140 | # ANN_SHIFTED_SHORT |
eb7082c9 UH |
141 | ['7-bit shifted hex (short)', |
142 | 'Read/write bit shifted out from the 8-bit I2C slave address'], | |
15969949 | 143 | # ANN_RAW |
eb7082c9 | 144 | ['Raw hex', 'Unaltered raw data'], |
15969949 | 145 | ] |
0588ed70 | 146 | |
3643fc3f | 147 | def __init__(self, **kwargs): |
c4975078 BV |
148 | self.startsample = -1 |
149 | self.samplenum = None | |
f39d2404 UH |
150 | self.bitcount = 0 |
151 | self.databyte = 0 | |
152 | self.wr = -1 | |
5dd9af5b | 153 | self.is_repeat_start = 0 |
400f9ae7 | 154 | self.state = FIND_START |
f39d2404 UH |
155 | self.oldscl = None |
156 | self.oldsda = None | |
157 | ||
3643fc3f | 158 | def start(self, metadata): |
56202222 UH |
159 | self.out_proto = self.add(srd.OUTPUT_PROTO, 'i2c') |
160 | self.out_ann = self.add(srd.OUTPUT_ANN, 'i2c') | |
3643fc3f | 161 | |
decde15e UH |
162 | def report(self): |
163 | pass | |
164 | ||
7b86f0bc | 165 | def is_start_condition(self, scl, sda): |
eb7082c9 | 166 | # START condition (S): SDA = falling, SCL = high |
7b86f0bc UH |
167 | if (self.oldsda == 1 and sda == 0) and scl == 1: |
168 | return True | |
169 | return False | |
170 | ||
171 | def is_data_bit(self, scl, sda): | |
eb7082c9 | 172 | # Data sampling of receiver: SCL = rising |
7b86f0bc UH |
173 | if self.oldscl == 0 and scl == 1: |
174 | return True | |
175 | return False | |
176 | ||
177 | def is_stop_condition(self, scl, sda): | |
eb7082c9 | 178 | # STOP condition (P): SDA = rising, SCL = high |
7b86f0bc UH |
179 | if (self.oldsda == 0 and sda == 1) and scl == 1: |
180 | return True | |
181 | return False | |
182 | ||
e5080882 | 183 | def found_start(self, scl, sda): |
c4975078 | 184 | self.startsample = self.samplenum |
eb7082c9 | 185 | |
c4975078 | 186 | cmd = 'START REPEAT' if (self.is_repeat_start == 1) else 'START' |
eb7082c9 UH |
187 | self.put(self.out_proto, [cmd, None, None]) |
188 | self.put(self.out_ann, [ANN_SHIFTED, [protocol[cmd][0]]]) | |
189 | self.put(self.out_ann, [ANN_SHIFTED_SHORT, [protocol[cmd][1]]]) | |
e5080882 | 190 | |
400f9ae7 | 191 | self.state = FIND_ADDRESS |
7b86f0bc | 192 | self.bitcount = self.databyte = 0 |
5dd9af5b | 193 | self.is_repeat_start = 1 |
7b86f0bc | 194 | self.wr = -1 |
7b86f0bc | 195 | |
c4975078 | 196 | # Gather 8 bits of data plus the ACK/NACK bit. |
e5080882 | 197 | def found_address_or_data(self, scl, sda): |
7b86f0bc UH |
198 | # Address and data are transmitted MSB-first. |
199 | self.databyte <<= 1 | |
200 | self.databyte |= sda | |
201 | ||
c4975078 BV |
202 | if self.bitcount == 0: |
203 | self.startsample = self.samplenum | |
204 | ||
7b86f0bc | 205 | # Return if we haven't collected all 8 + 1 bits, yet. |
c4975078 | 206 | self.bitcount += 1 |
7b86f0bc | 207 | if self.bitcount != 9: |
eb7082c9 | 208 | return |
7b86f0bc | 209 | |
eb7082c9 UH |
210 | # Send raw output annotation before we start shifting out |
211 | # read/write and ack/nack bits. | |
212 | self.put(self.out_ann, [ANN_RAW, ['0x%.2x' % self.databyte]]) | |
15969949 | 213 | |
7b86f0bc UH |
214 | # We received 8 address/data bits and the ACK/NACK bit. |
215 | self.databyte >>= 1 # Shift out unwanted ACK/NACK bit here. | |
216 | ||
400f9ae7 | 217 | if self.state == FIND_ADDRESS: |
7b86f0bc | 218 | # The READ/WRITE bit is only in address bytes, not data bytes. |
bf1c3f4d | 219 | self.wr = 0 if (self.databyte & 1) else 1 |
84b81f1d | 220 | d = self.databyte >> 1 |
400f9ae7 | 221 | elif self.state == FIND_DATA: |
7b86f0bc UH |
222 | d = self.databyte |
223 | else: | |
224 | # TODO: Error? | |
225 | pass | |
226 | ||
eb7082c9 | 227 | # Last bit that came in was the ACK/NACK bit (1 = NACK). |
bf1c3f4d | 228 | ack_bit = 'NACK' if (sda == 1) else 'ACK' |
15969949 | 229 | |
400f9ae7 | 230 | if self.state == FIND_ADDRESS and self.wr == 1: |
a2d2aff2 | 231 | cmd = 'ADDRESS WRITE' |
400f9ae7 | 232 | elif self.state == FIND_ADDRESS and self.wr == 0: |
a2d2aff2 | 233 | cmd = 'ADDRESS READ' |
400f9ae7 | 234 | elif self.state == FIND_DATA and self.wr == 1: |
a2d2aff2 | 235 | cmd = 'DATA WRITE' |
400f9ae7 | 236 | elif self.state == FIND_DATA and self.wr == 0: |
a2d2aff2 | 237 | cmd = 'DATA READ' |
eb7082c9 UH |
238 | |
239 | self.put(self.out_proto, [cmd, d, ack_bit]) | |
957da073 UH |
240 | self.put(self.out_ann, [ANN_SHIFTED, |
241 | [protocol[cmd][0], '0x%02x' % d, protocol[ack_bit][0]]]) | |
242 | self.put(self.out_ann, [ANN_SHIFTED_SHORT, | |
243 | [protocol[cmd][1], '0x%02x' % d, protocol[ack_bit][1]]]) | |
7b86f0bc | 244 | |
7b86f0bc UH |
245 | self.bitcount = self.databyte = 0 |
246 | self.startsample = -1 | |
247 | ||
400f9ae7 UH |
248 | if self.state == FIND_ADDRESS: |
249 | self.state = FIND_DATA | |
250 | elif self.state == FIND_DATA: | |
7b86f0bc UH |
251 | # There could be multiple data bytes in a row. |
252 | # So, either find a STOP condition or another data byte next. | |
253 | pass | |
254 | ||
e5080882 | 255 | def found_stop(self, scl, sda): |
c4975078 BV |
256 | self.startsample = self.samplenum |
257 | ||
eb7082c9 UH |
258 | self.put(self.out_proto, ['STOP', None, None]) |
259 | self.put(self.out_ann, [ANN_SHIFTED, [protocol['STOP'][0]]]) | |
260 | self.put(self.out_ann, [ANN_SHIFTED_SHORT, [protocol['STOP'][1]]]) | |
7b86f0bc | 261 | |
400f9ae7 | 262 | self.state = FIND_START |
5dd9af5b | 263 | self.is_repeat_start = 0 |
7b86f0bc UH |
264 | self.wr = -1 |
265 | ||
1aef2f93 | 266 | def put(self, output_id, data): |
eb7082c9 | 267 | # Inject sample range into the call up to sigrok. |
c4975078 | 268 | super(Decoder, self).put(self.startsample, self.samplenum, output_id, data) |
1aef2f93 | 269 | |
2b9837d9 | 270 | def decode(self, ss, es, data): |
bc5f5a43 | 271 | for samplenum, (scl, sda) in data: |
c4975078 | 272 | self.samplenum = samplenum |
f39d2404 UH |
273 | |
274 | # First sample: Save SCL/SDA value. | |
275 | if self.oldscl == None: | |
bc5f5a43 BV |
276 | self.oldscl = scl |
277 | self.oldsda = sda | |
ad2dc0de | 278 | continue |
0588ed70 | 279 | |
f39d2404 UH |
280 | # TODO: Wait until the bus is idle (SDA = SCL = 1) first? |
281 | ||
7b86f0bc | 282 | # State machine. |
400f9ae7 | 283 | if self.state == FIND_START: |
7b86f0bc | 284 | if self.is_start_condition(scl, sda): |
e5080882 | 285 | self.found_start(scl, sda) |
400f9ae7 | 286 | elif self.state == FIND_ADDRESS: |
7b86f0bc | 287 | if self.is_data_bit(scl, sda): |
e5080882 | 288 | self.found_address_or_data(scl, sda) |
400f9ae7 | 289 | elif self.state == FIND_DATA: |
7b86f0bc | 290 | if self.is_data_bit(scl, sda): |
e5080882 | 291 | self.found_address_or_data(scl, sda) |
7b86f0bc | 292 | elif self.is_start_condition(scl, sda): |
e5080882 | 293 | self.found_start(scl, sda) |
7b86f0bc | 294 | elif self.is_stop_condition(scl, sda): |
e5080882 | 295 | self.found_stop(scl, sda) |
7b86f0bc | 296 | else: |
decde15e | 297 | raise Exception('Invalid state %d' % self.STATE) |
f39d2404 UH |
298 | |
299 | # Save current SDA/SCL values for the next round. | |
300 | self.oldscl = scl | |
301 | self.oldsda = sda | |
302 |