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1 | ## |
2 | ## This file is part of the sigrok project. | |
3 | ## | |
4 | ## Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de> | |
5 | ## | |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, write to the Free Software | |
18 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | ## | |
20 | ||
21 | # | |
22 | # I2C protocol decoder | |
23 | # | |
24 | ||
25 | # | |
26 | # The Inter-Integrated Circuit (I2C) bus is a bidirectional, multi-master | |
27 | # bus using two signals (SCL = serial clock line, SDA = serial data line). | |
28 | # | |
29 | # There can be many devices on the same bus. Each device can potentially be | |
30 | # master or slave (and that can change during runtime). Both slave and master | |
31 | # can potentially play the transmitter or receiver role (this can also | |
32 | # change at runtime). | |
33 | # | |
34 | # Possible maximum data rates: | |
35 | # - Standard mode: 100 kbit/s | |
36 | # - Fast mode: 400 kbit/s | |
37 | # - Fast-mode Plus: 1 Mbit/s | |
38 | # - High-speed mode: 3.4 Mbit/s | |
39 | # | |
40 | # START condition (S): SDA = falling, SCL = high | |
41 | # Repeated START condition (Sr): same as S | |
42 | # STOP condition (P): SDA = rising, SCL = high | |
43 | # | |
33e72c54 | 44 | # All data bytes on SDA are exactly 8 bits long (transmitted MSB-first). |
0588ed70 UH |
45 | # Each byte has to be followed by a 9th ACK/NACK bit. If that bit is low, |
46 | # that indicates an ACK, if it's high that indicates a NACK. | |
47 | # | |
48 | # After the first START condition, a master sends the device address of the | |
49 | # slave it wants to talk to. Slave addresses are 7 bits long (MSB-first). | |
33e72c54 | 50 | # After those 7 bits, a data direction bit is sent. If the bit is low that |
0588ed70 UH |
51 | # indicates a WRITE operation, if it's high that indicates a READ operation. |
52 | # | |
53 | # Later an optional 10bit slave addressing scheme was added. | |
54 | # | |
55 | # Documentation: | |
56 | # http://www.nxp.com/acrobat/literature/9398/39340011.pdf (v2.1 spec) | |
57 | # http://www.nxp.com/acrobat/usermanuals/UM10204_3.pdf (v3 spec) | |
58 | # http://en.wikipedia.org/wiki/I2C | |
59 | # | |
60 | ||
61 | # TODO: Look into arbitration, collision detection, clock synchronisation, etc. | |
62 | # TODO: Handle clock stretching. | |
63 | # TODO: Handle combined messages / repeated START. | |
64 | # TODO: Implement support for 7bit and 10bit slave addresses. | |
65 | # TODO: Implement support for inverting SDA/SCL levels (0->1 and 1->0). | |
66 | # TODO: Implement support for detecting various bus errors. | |
67 | ||
23fb2e12 UH |
68 | # |
69 | # I2C output format: | |
70 | # | |
71 | # The output consists of a (Python) list of I2C "packets", each of which | |
72 | # has an (implicit) index number (its index in the list). | |
73 | # Each packet consists of a Python dict with certain key/value pairs. | |
74 | # | |
75 | # TODO: Make this a list later instead of a dict? | |
76 | # | |
77 | # 'type': (string) | |
78 | # - 'S' (START condition) | |
79 | # - 'Sr' (Repeated START) | |
80 | # - 'AR' (Address, read) | |
81 | # - 'AW' (Address, write) | |
82 | # - 'DR' (Data, read) | |
83 | # - 'DW' (Data, write) | |
84 | # - 'P' (STOP condition) | |
85 | # 'range': (tuple of 2 integers, the min/max samplenumber of this range) | |
86 | # - (min, max) | |
87 | # - min/max can also be identical. | |
88 | # 'data': (actual data as integer ???) TODO: This can be very variable... | |
89 | # 'ann': (string; additional annotations / comments) | |
90 | # | |
91 | # Example output: | |
92 | # [{'type': 'S', 'range': (150, 160), 'data': None, 'ann': 'Foobar'}, | |
93 | # {'type': 'AW', 'range': (200, 300), 'data': 0x50, 'ann': 'Slave 4'}, | |
94 | # {'type': 'DW', 'range': (310, 370), 'data': 0x00, 'ann': 'Init cmd'}, | |
95 | # {'type': 'AR', 'range': (500, 560), 'data': 0x50, 'ann': 'Get stat'}, | |
96 | # {'type': 'DR', 'range': (580, 640), 'data': 0xfe, 'ann': 'OK'}, | |
97 | # {'type': 'P', 'range': (650, 660), 'data': None, 'ann': None}] | |
98 | # | |
99 | # Possible other events: | |
100 | # - Error event in case protocol looks broken: | |
101 | # [{'type': 'ERROR', 'range': (min, max), | |
ad2dc0de | 102 | # 'data': TODO, 'ann': 'This is not a Microchip 24XX64 EEPROM'}, |
23fb2e12 | 103 | # [{'type': 'ERROR', 'range': (min, max), |
ad2dc0de | 104 | # 'data': TODO, 'ann': 'TODO'}, |
23fb2e12 UH |
105 | # - TODO: Make list of possible errors accessible as metadata? |
106 | # | |
107 | # TODO: I2C address of slaves. | |
108 | # TODO: Handle multiple different I2C devices on same bus | |
109 | # -> we need to decode multiple protocols at the same time. | |
110 | # TODO: range: Always contiguous? Splitted ranges? Multiple per event? | |
111 | # | |
112 | ||
113 | # | |
114 | # I2C input format: | |
115 | # | |
116 | # signals: | |
117 | # [[id, channel, description], ...] # TODO | |
118 | # | |
119 | # Example: | |
120 | # {'id': 'SCL', 'ch': 5, 'desc': 'Serial clock line'} | |
121 | # {'id': 'SDA', 'ch': 7, 'desc': 'Serial data line'} | |
122 | # ... | |
123 | # | |
124 | # {'inbuf': [...], | |
125 | # 'signals': [{'SCL': }]} | |
126 | # | |
127 | ||
f39d2404 UH |
128 | class Sample(): |
129 | def __init__(self, data): | |
130 | self.data = data | |
131 | def probe(self, probe): | |
132 | s = ord(self.data[probe / 8]) & (1 << (probe % 8)) | |
133 | return True if s else False | |
134 | ||
135 | def sampleiter(data, unitsize): | |
136 | for i in range(0, len(data), unitsize): | |
137 | yield(Sample(data[i:i+unitsize])) | |
138 | ||
139 | class Decoder(): | |
140 | name = 'I2C' | |
141 | longname = 'Inter-Integrated Circuit (I2C) bus' | |
142 | desc = 'I2C is a two-wire, multi-master, serial bus.' | |
143 | longdesc = '...' | |
144 | author = 'Uwe Hermann' | |
145 | email = 'uwe@hermann-uwe.de' | |
146 | license = 'gplv2+' | |
147 | inputs = ['logic'] | |
148 | outputs = ['i2c'] | |
149 | probes = { | |
150 | 'scl': {'ch': 0, 'name': 'SCL', 'desc': 'Serial clock line'}, | |
151 | 'sda': {'ch': 1, 'name': 'SDA', 'desc': 'Serial data line'}, | |
152 | } | |
153 | options = { | |
154 | 'address-space': ['Address space (in bits)', 7], | |
ad2dc0de | 155 | } |
0588ed70 | 156 | |
f39d2404 UH |
157 | def __init__(self, unitsize, **kwargs): |
158 | # Metadata comes in here, we don't care for now. | |
159 | # print kwargs | |
160 | self.unitsize = unitsize | |
161 | ||
162 | self.probes = Decoder.probes.copy() | |
163 | ||
164 | # TODO: Don't hardcode the number of channels. | |
165 | self.channels = 8 | |
166 | ||
167 | self.samplenum = 0 | |
168 | ||
169 | self.bitcount = 0 | |
170 | self.databyte = 0 | |
171 | self.wr = -1 | |
172 | self.startsample = -1 | |
173 | self.IDLE, self.START, self.ADDRESS, self.DATA = range(4) | |
174 | self.state = self.IDLE | |
175 | ||
176 | # Get the channel/probe number of the SCL/SDA signals. | |
177 | self.scl_bit = self.probes['scl']['ch'] | |
178 | self.sda_bit = self.probes['sda']['ch'] | |
179 | ||
180 | self.oldscl = None | |
181 | self.oldsda = None | |
182 | ||
183 | def report(self): | |
184 | pass | |
185 | ||
186 | def decode(self, data): | |
187 | """I2C protocol decoder""" | |
188 | ||
189 | out = [] | |
190 | o = ack = d = '' | |
191 | ||
192 | # We should accept a list of samples and iterate... | |
193 | for sample in sampleiter(data["data"], self.unitsize): | |
194 | ||
195 | # TODO: Eliminate the need for ord(). | |
196 | s = ord(sample.data) | |
197 | ||
198 | # TODO: Start counting at 0 or 1? | |
199 | self.samplenum += 1 | |
200 | ||
201 | # First sample: Save SCL/SDA value. | |
202 | if self.oldscl == None: | |
203 | # Get SCL/SDA bit values (0/1 for low/high) of the first sample. | |
204 | self.oldscl = (s & (1 << self.scl_bit)) >> self.scl_bit | |
205 | self.oldsda = (s & (1 << self.sda_bit)) >> self.sda_bit | |
ad2dc0de | 206 | continue |
0588ed70 | 207 | |
f39d2404 UH |
208 | # Get SCL/SDA bit values (0/1 for low/high). |
209 | scl = (s & (1 << self.scl_bit)) >> self.scl_bit | |
210 | sda = (s & (1 << self.sda_bit)) >> self.sda_bit | |
211 | ||
212 | # TODO: Wait until the bus is idle (SDA = SCL = 1) first? | |
213 | ||
214 | # START condition (S): SDA = falling, SCL = high | |
215 | if (self.oldsda == 1 and sda == 0) and scl == 1: | |
216 | o = {'type': 'S', 'range': (self.samplenum, self.samplenum), | |
217 | 'data': None, 'ann': None}, | |
218 | out.append(o) | |
219 | self.state = self.ADDRESS | |
220 | self.bitcount = self.databyte = 0 | |
221 | ||
222 | # Data latching by transmitter: SCL = low | |
223 | elif (scl == 0): | |
224 | pass # TODO | |
225 | ||
226 | # Data sampling of receiver: SCL = rising | |
227 | elif (self.oldscl == 0 and scl == 1): | |
228 | if self.startsample == -1: | |
229 | self.startsample = self.samplenum | |
230 | self.bitcount += 1 | |
231 | ||
232 | # out.append("%d\t\tRECEIVED BIT %d: %d\n" % \ | |
233 | # (self.samplenum, 8 - bitcount, sda)) | |
234 | ||
235 | # Address and data are transmitted MSB-first. | |
236 | self.databyte <<= 1 | |
237 | self.databyte |= sda | |
238 | ||
239 | if self.bitcount != 9: | |
240 | continue | |
241 | ||
242 | # We received 8 address/data bits and the ACK/NACK bit. | |
243 | self.databyte >>= 1 # Shift out unwanted ACK/NACK bit here. | |
244 | ack = (sda == 1) and 'N' or 'A' | |
245 | d = (self.state == self.ADDRESS) and (self.databyte & 0xfe) or self.databyte | |
246 | if self.state == self.ADDRESS: | |
247 | self.wr = (self.databyte & 1) and 1 or 0 | |
248 | self.state = self.DATA | |
249 | o = {'type': self.state, | |
250 | 'range': (self.startsample, self.samplenum - 1), | |
251 | 'data': d, 'ann': None} | |
252 | if self.state == self.ADDRESS and self.wr == 1: | |
253 | o['type'] = 'AW' | |
254 | elif self.state == self.ADDRESS and self.wr == 0: | |
255 | o['type'] = 'AR' | |
256 | elif self.state == self.DATA and self.wr == 1: | |
257 | o['type'] = 'DW' | |
258 | elif self.state == self.DATA and self.wr == 0: | |
259 | o['type'] = 'DR' | |
260 | out.append(o) | |
261 | o = {'type': ack, 'range': (self.samplenum, self.samplenum), | |
262 | 'data': None, 'ann': None} | |
263 | out.append(o) | |
264 | self.bitcount = self.databyte = self.startsample = 0 | |
265 | self.startsample = -1 | |
266 | ||
267 | # STOP condition (P): SDA = rising, SCL = high | |
268 | elif (self.oldsda == 0 and sda == 1) and scl == 1: | |
269 | o = {'type': 'P', 'range': (self.samplenum, self.samplenum), | |
270 | 'data': None, 'ann': None}, | |
271 | out.append(o) | |
272 | self.state = self.IDLE | |
273 | self.wr = -1 | |
274 | ||
275 | # Save current SDA/SCL values for the next round. | |
276 | self.oldscl = scl | |
277 | self.oldsda = sda | |
278 | ||
279 | # TODO: Which output format? | |
280 | # TODO: How to only output something after the last chunk of data? | |
281 | if out != []: | |
282 | sigrok.put(out) | |
0588ed70 | 283 | |
887d6cfa UH |
284 | # Use psyco (if available) as it results in huge performance improvements. |
285 | try: | |
ad2dc0de UH |
286 | import psyco |
287 | psyco.bind(decode) | |
887d6cfa | 288 | except ImportError: |
ad2dc0de | 289 | pass |
887d6cfa | 290 | |
f39d2404 UH |
291 | import sigrok |
292 |