+/*
+ * This is a unified protocol driver for the DS1000 and DS2000 series.
+ *
+ * DS1000 support tested with a Rigol DS1102D.
+ *
+ * DS2000 support tested with a Rigol DS2072 using firmware version 01.01.00.02.
+ *
+ * The Rigol DS2000 series scopes try to adhere to the IEEE 488.2 (I think)
+ * standard. If you want to read it - it costs real money...
+ *
+ * Every response from the scope has a linefeed appended because the
+ * standard says so. In principle this could be ignored because sending the
+ * next command clears the output queue of the scope. This driver tries to
+ * avoid doing that because it may cause an error being generated inside the
+ * scope and who knows what bugs the firmware has WRT this.
+ *
+ * Waveform data is transferred in a format called "arbitrary block program
+ * data" specified in IEEE 488.2. See Agilents programming manuals for their
+ * 2000/3000 series scopes for a nice description.
+ *
+ * Each data block from the scope has a header, e.g. "#900000001400".
+ * The '#' marks the start of a block.
+ * Next is one ASCII decimal digit between 1 and 9, this gives the number of
+ * ASCII decimal digits following.
+ * Last are the ASCII decimal digits giving the number of bytes (not
+ * samples!) in the block.
+ *
+ * After this header as many data bytes as indicated follow.
+ *
+ * Each data block has a trailing linefeed too.
+ */
+
+static int get_cfg(const struct sr_dev_inst *sdi, char *cmd, char *reply, size_t maxlen);
+static int get_cfg_int(const struct sr_dev_inst *sdi, char *cmd, int *i);
+
+static int parse_int(const char *str, int *ret)
+{
+ char *e;
+ long tmp;
+
+ errno = 0;
+ tmp = strtol(str, &e, 10);
+ if (e == str || *e != '\0') {
+ sr_dbg("Failed to parse integer: '%s'", str);
+ return SR_ERR;
+ }
+ if (errno) {
+ sr_dbg("Failed to parse integer: '%s', numerical overflow", str);
+ return SR_ERR;
+ }
+ if (tmp > INT_MAX || tmp < INT_MIN) {
+ sr_dbg("Failed to parse integer: '%s', value to large/small", str);
+ return SR_ERR;
+ }
+
+ *ret = (int)tmp;
+ return SR_OK;
+}
+
+/*
+ * Waiting for a trigger event will return a timeout after 2, 3 seconds in
+ * order to not block the application.
+ */
+
+static int rigol_ds2xx2_trigger_wait(const struct sr_dev_inst *sdi)
+{
+ char buf[20];
+ struct dev_context *devc;
+ time_t start;
+
+ if (!(devc = sdi->priv))
+ return SR_ERR;
+
+ start = time(NULL);
+
+ /*
+ * Trigger status may return:
+ * "TD" - triggered
+ * "AUTO" - autotriggered
+ * "RUN" - running
+ * "WAIT" - waiting for trigger
+ * "STOP" - stopped
+ */
+
+ if (devc->trigger_wait_status == 1) {
+ do {
+ if (time(NULL) - start >= 3) {
+ sr_dbg("Timeout waiting for trigger");
+ return SR_ERR_TIMEOUT;
+ }
+
+ if (get_cfg(sdi, ":TRIG:STAT?", buf, sizeof(buf)) != SR_OK)
+ return SR_ERR;
+ } while (buf[0] == 'T' || buf[0] == 'A');
+
+ devc->trigger_wait_status = 2;
+ }
+ if (devc->trigger_wait_status == 2) {
+ do {
+ if (time(NULL) - start >= 3) {
+ sr_dbg("Timeout waiting for trigger");
+ return SR_ERR_TIMEOUT;
+ }
+
+ if (get_cfg(sdi, ":TRIG:STAT?", buf, sizeof(buf)) != SR_OK)
+ return SR_ERR;
+ } while (buf[0] != 'T' && buf[0] != 'A');
+
+ devc->trigger_wait_status = 0;
+ }
+
+ return SR_OK;
+}
+
+/*
+ * This needs to wait for a new trigger event to ensure that sample data is
+ * not returned twice.
+ *
+ * Unfortunately this will never really work because for sufficiently fast
+ * timebases it just can't catch the status changes.
+ *
+ * What would be needed is a trigger event register with autoreset like the
+ * Agilents have. The Rigols don't seem to have anything like this.
+ *
+ * The workaround is to only wait for the trigger when the timebase is slow
+ * enough. Of course this means that for faster timebases sample data can be
+ * returned multiple times.
+ */
+
+SR_PRIV int rigol_ds2xx2_acquisition_start(const struct sr_dev_inst *sdi,
+ gboolean wait_for_trigger)
+{
+ struct dev_context *devc;
+
+ if (!(devc = sdi->priv))
+ return SR_ERR;
+
+ devc->channel_frame = devc->enabled_analog_probes->data;
+
+ sr_dbg("Starting acquisition on channel %d",
+ devc->channel_frame->index + 1);
+
+ if (rigol_ds_send(sdi, ":WAV:FORM BYTE") != SR_OK)
+ return SR_ERR;
+ if (rigol_ds_send(sdi, ":WAV:SOUR CHAN%d",
+ devc->channel_frame->index + 1) != SR_OK)
+ return SR_ERR;
+ if (rigol_ds_send(sdi, ":WAV:MODE NORM") != SR_OK)
+ return SR_ERR;
+
+ devc->num_frame_bytes = 0;
+ devc->num_block_bytes = 0;
+
+ /* only wait for trigger if timbase 50 msecs/DIV or slower */
+ if (wait_for_trigger && devc->timebase > 0.0499)
+ {
+ devc->trigger_wait_status = 1;
+ } else {
+ devc->trigger_wait_status = 0;
+ }
+
+ return SR_OK;
+}
+
+static int rigol_ds2xx2_read_header(struct sr_serial_dev_inst *serial)
+{
+ char start[3], length[10];
+ int len, tmp;
+
+ /* Read the hashsign and length digit. */
+ tmp = serial_read(serial, start, 2);
+ start[2] = '\0';
+ if (tmp != 2)
+ {
+ sr_err("Failed to read first two bytes of data block header.");
+ return -1;
+ }
+ if (start[0] != '#' || !isdigit(start[1]) || start[1] == '0')
+ {
+ sr_err("Received invalid data block header start '%s'.", start);
+ return -1;
+ }
+ len = atoi(start + 1);
+
+ /* Read the data length. */
+ tmp = serial_read(serial, length, len);
+ length[len] = '\0';
+ if (tmp != len)
+ {
+ sr_err("Failed to read %d bytes of data block length.", len);
+ return -1;
+ }
+ if (parse_int(length, &len) != SR_OK)
+ {
+ sr_err("Received invalid data block length '%s'.", length);
+ return -1;
+ }
+
+ sr_dbg("Received data block header: %s%s -> block length %d", start, length, len);
+
+ return len;
+}
+