+ acq = devc->acquisition;
+
+ /* By default, run virtually unlimited. */
+ acq->duration_max = (devc->limit_msec > 0)
+ ? devc->limit_msec : MAX_LIMIT_MSEC;
+ acq->samples_max = (devc->limit_samples > 0)
+ ? devc->limit_samples : MAX_LIMIT_SAMPLES;
+
+ switch (devc->cur_clock_source) {
+ case CLOCK_SOURCE_INT:
+ if (devc->samplerate == 0)
+ return SR_ERR_BUG;
+ /* At 125 MHz, the clock divider is bypassed. */
+ acq->bypass_clockdiv = (devc->samplerate > SR_MHZ(100));
+
+ /* If only one of the limits is set, derive the other one. */
+ if (devc->limit_msec == 0 && devc->limit_samples > 0)
+ acq->duration_max = devc->limit_samples
+ * 1000 / devc->samplerate + 1;
+ else if (devc->limit_samples == 0 && devc->limit_msec > 0)
+ acq->samples_max = devc->limit_msec
+ * devc->samplerate / 1000;
+ break;
+ case CLOCK_SOURCE_EXT_FALL:
+ case CLOCK_SOURCE_EXT_RISE:
+ acq->bypass_clockdiv = TRUE;
+ break;
+ default:
+ sr_err("No valid clock source has been configured.");
+ return SR_ERR;
+ }