+/* USB PID dependent MCU firmware. Model dependent FPGA bitstream. */
+#define MCU_FWFILE_FMT "kingst-la-%04x.fw"
+#define FPGA_FWFILE_FMT "kingst-%s-fpga.bitstream"
+
+/*
+ * List of known devices and their features. See @ref kingst_model
+ * for the fields' type and meaning. Table is sorted by EEPROM magic.
+ * More specific items need to go first (additional byte[2/6]). Not
+ * all devices are covered by this driver implementation, but telling
+ * users what was detected is considered useful.
+ *
+ * TODO Verify the identification of models that were not tested before.
+ */
+static const struct kingst_model models[] = {
+ { 0x02, 0x01, "LA2016", "la2016a1", SR_MHZ(200), 16, 1, 0, },
+ { 0x02, 0x00, "LA2016", "la2016", SR_MHZ(200), 16, 1, 0, },
+ { 0x03, 0x01, "LA1016", "la1016a1", SR_MHZ(100), 16, 1, 0, },
+ { 0x03, 0x00, "LA1016", "la1016", SR_MHZ(100), 16, 1, 0, },
+ { 0x04, 0x00, "LA1010", "la1010a0", SR_MHZ(100), 16, 0, SR_MHZ(800), },
+ { 0x05, 0x00, "LA5016", "la5016a1", SR_MHZ(500), 16, 2, SR_MHZ(800), },
+ { 0x06, 0x00, "LA5032", "la5032a0", SR_MHZ(500), 32, 4, SR_MHZ(800), },
+ { 0x07, 0x00, "LA1010", "la1010a1", SR_MHZ(100), 16, 0, SR_MHZ(800), },
+ { 0x08, 0x00, "LA2016", "la2016a1", SR_MHZ(200), 16, 1, 0, },
+ { 0x09, 0x00, "LA1016", "la1016a1", SR_MHZ(100), 16, 1, 0, },
+ { 0x0a, 0x00, "LA1010", "la1010a2", SR_MHZ(100), 16, 0, SR_MHZ(800), },
+ { 0x0b, 0x10, "LA2016", "la2016a2", SR_MHZ(200), 16, 1, 0, },
+ { 0x0c, 0x10, "LA5016", "la5016a2", SR_MHZ(500), 16, 2, SR_MHZ(800), },
+ { 0x0c, 0x00, "LA5016", "la5016a2", SR_MHZ(500), 16, 2, SR_MHZ(800), },
+ { 0x41, 0x00, "LA5016", "la5016a1", SR_MHZ(500), 16, 2, SR_MHZ(800), },
+};
+
+/* USB vendor class control requests, executed by the Cypress FX2 MCU. */
+#define CMD_FPGA_ENABLE 0x10
+#define CMD_FPGA_SPI 0x20 /* R/W access to FPGA registers via SPI. */
+#define CMD_BULK_START 0x30 /* Start sample data download via USB EP6 IN. */
+#define CMD_BULK_RESET 0x38 /* Flush FIFO of FX2 USB EP6 IN. */
+#define CMD_FPGA_INIT 0x50 /* Used before and after FPGA bitstream upload. */
+#define CMD_KAUTH 0x60 /* Communicate to auth IC (U10). Not used. */
+#define CMD_EEPROM 0xa2 /* R/W access to EEPROM content. */
+
+/*
+ * FPGA register addresses (base addresses when registers span multiple
+ * bytes, in that case data is kept in little endian format). Passed to
+ * CMD_FPGA_SPI requests. The FX2 MCU transparently handles the detail
+ * of SPI transfers encoding the read (1) or write (0) direction in the
+ * MSB of the address field. There are some 60 byte-wide FPGA registers.
+ *
+ * Unfortunately the FPGA registers change their meaning between the
+ * read and write directions of access, or exclusively provide one of
+ * these directions and not the other. This is an arbitrary vendor's
+ * choice, there is nothing which the sigrok driver could do about it.
+ * Values written to registers typically cannot get read back, neither
+ * verified after writing a configuration, nor queried upon startup for
+ * automatic detection of the current configuration. Neither appear to
+ * be there echo registers for presence and communication checks, nor
+ * version identifying registers, as far as we know.
+ */
+#define REG_RUN 0x00 /* Read capture status, write start capture. */
+#define REG_PWM_EN 0x02 /* User PWM channels on/off. */
+#define REG_CAPT_MODE 0x03 /* Write 0x00 capture to SDRAM, 0x01 streaming. */
+#define REG_PIN_STATE 0x04 /* Read current pin state (real time display). */
+#define REG_BULK 0x08 /* Write start addr, byte count to download samples. */
+#define REG_SAMPLING 0x10 /* Write capture config, read capture SDRAM location. */
+#define REG_TRIGGER 0x20 /* Write level and edge trigger config. */
+#define REG_UNKNOWN_30 0x30
+#define REG_THRESHOLD 0x68 /* Write PWM config to setup input threshold DAC. */
+#define REG_PWM1 0x70 /* Write config for user PWM1. */
+#define REG_PWM2 0x78 /* Write config for user PWM2. */
+
+/* Bit patterns to write to REG_CAPT_MODE. */
+#define CAPTMODE_TO_RAM 0x00
+#define CAPTMODE_STREAM 0x01
+
+/* Bit patterns to write to REG_RUN, setup run mode. */
+#define RUNMODE_HALT 0x00
+#define RUNMODE_RUN 0x03
+
+/* Bit patterns when reading from REG_RUN, get run state. */
+#define RUNSTATE_IDLE_BIT (1UL << 0)
+#define RUNSTATE_DRAM_BIT (1UL << 1)
+#define RUNSTATE_TRGD_BIT (1UL << 2)
+#define RUNSTATE_POST_BIT (1UL << 3)