SR_CONF_CLOCK_EDGE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
};
-static const char *const signal_edge_names[] = {
+static const int32_t trigger_matches[] = {
+ SR_TRIGGER_ZERO,
+ SR_TRIGGER_ONE,
+ SR_TRIGGER_RISING,
+ SR_TRIGGER_FALLING,
+ SR_TRIGGER_EDGE,
+};
+
+static const char *signal_edges[] = {
[DS_EDGE_RISING] = "rising",
[DS_EDGE_FALLING] = "falling",
};
-static const double voltage_thresholds[][2] = {
+static const double thresholds[][2] = {
{ 0.7, 1.4 },
{ 1.4, 3.6 },
};
continue;
}
- usb_get_port_path(devlist[i], connection_id, sizeof(connection_id));
-
libusb_close(hdl);
+ if (usb_get_port_path(devlist[i], connection_id, sizeof(connection_id)) < 0)
+ continue;
+
prof = NULL;
for (j = 0; supported_device[j].vid; j++) {
if (des.idVendor == supported_device[j].vid &&
sdi->connection_id = g_strdup(connection_id);
/* Logic channels, all in one channel group. */
- cg = g_malloc0(sizeof(struct sr_channel_group));
- cg->name = g_strdup("Logic");
- for (j = 0; j < 16; j++) {
+ cg = sr_channel_group_new(sdi, "Logic", NULL);
+ for (j = 0; j < NUM_CHANNELS; j++) {
sprintf(channel_name, "%d", j);
ch = sr_channel_new(sdi, j, SR_CHANNEL_LOGIC,
TRUE, channel_name);
cg->channels = g_slist_append(cg->channels, ch);
}
- sdi->channel_groups = g_slist_append(NULL, cg);
devc = dslogic_dev_new();
devc->profile = prof;
libusb_get_device_address(devlist[i]), NULL);
} else {
if (ezusb_upload_firmware(drvc->sr_ctx, devlist[i],
- USB_CONFIGURATION, prof->firmware) == SR_OK)
+ USB_CONFIGURATION, prof->firmware) == SR_OK) {
/* Store when this device's FW was updated. */
devc->fw_updated = g_get_monotonic_time();
- else
+ } else {
sr_err("Firmware upload failed for "
- "device %d.%d (logical).",
+ "device %d.%d (logical), name %s.",
libusb_get_bus_number(devlist[i]),
- libusb_get_device_address(devlist[i]));
+ libusb_get_device_address(devlist[i]),
+ prof->firmware);
+ }
sdi->inst_type = SR_INST_USB;
sdi->conn = sr_usb_dev_inst_new(libusb_get_bus_number(devlist[i]),
0xff, NULL);
devc->cur_samplerate = devc->samplerates[0];
}
- if (devc->cur_threshold == 0.0)
- devc->cur_threshold = 1.5;
+ if (devc->cur_threshold == 0.0) {
+ devc->cur_threshold = thresholds[1][0];
+ return dslogic_set_voltage_threshold(sdi, devc->cur_threshold);
+ }
return SR_OK;
}
{
struct dev_context *devc;
struct sr_usb_dev_inst *usb;
- unsigned int i, voltage_range;
+ int idx;
(void)cg;
break;
case SR_CONF_VOLTAGE_THRESHOLD:
if (!strcmp(devc->profile->model, "DSLogic")) {
- voltage_range = 0;
-
- for (i = 0; i < ARRAY_SIZE(voltage_thresholds); i++)
- if (voltage_thresholds[i][0] == devc->cur_threshold) {
- voltage_range = i;
- break;
- }
- *data = std_gvar_tuple_double(voltage_thresholds[voltage_range][0],
- voltage_thresholds[voltage_range][1]);
+ if ((idx = std_double_tuple_idx_d0(devc->cur_threshold,
+ ARRAY_AND_SIZE(thresholds))) < 0)
+ return SR_ERR_BUG;
+ *data = std_gvar_tuple_double(thresholds[idx][0],
+ thresholds[idx][1]);
} else {
*data = std_gvar_tuple_double(devc->cur_threshold, devc->cur_threshold);
}
*data = g_variant_new_boolean(devc->continuous_mode);
break;
case SR_CONF_CLOCK_EDGE:
- i = devc->clock_edge;
- if (i >= ARRAY_SIZE(signal_edge_names))
+ idx = devc->clock_edge;
+ if (idx >= (int)ARRAY_SIZE(signal_edges))
return SR_ERR_BUG;
- *data = g_variant_new_string(signal_edge_names[0]);
+ *data = g_variant_new_string(signal_edges[0]);
break;
default:
return SR_ERR_NA;
return SR_OK;
}
-/*
- * Helper for mapping a string-typed configuration value to an index
- * within a table of possible values.
- */
-static int lookup_index(GVariant *value, const char *const *table, int len)
-{
- const char *entry;
- int i;
-
- entry = g_variant_get_string(value, NULL);
- if (!entry)
- return -1;
-
- /* Linear search is fine for very small tables. */
- for (i = 0; i < len; i++) {
- if (strcmp(entry, table[i]) == 0)
- return i;
- }
-
- return -1;
-}
-
static int config_set(uint32_t key, GVariant *data,
const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
{
struct dev_context *devc;
- uint64_t arg;
- int i, ret;
+ int idx;
gdouble low, high;
(void)cg;
devc = sdi->priv;
- ret = SR_OK;
-
switch (key) {
case SR_CONF_SAMPLERATE:
- arg = g_variant_get_uint64(data);
- for (i = 0; i < devc->num_samplerates; i++) {
- if (devc->samplerates[i] == arg) {
- devc->cur_samplerate = arg;
- break;
- }
- }
- if (i == devc->num_samplerates)
- ret = SR_ERR_ARG;
+ if ((idx = std_u64_idx(data, devc->samplerates, devc->num_samplerates)) < 0)
+ return SR_ERR_ARG;
+ devc->cur_samplerate = devc->samplerates[idx];
break;
case SR_CONF_LIMIT_SAMPLES:
devc->limit_samples = g_variant_get_uint64(data);
break;
case SR_CONF_CAPTURE_RATIO:
devc->capture_ratio = g_variant_get_uint64(data);
- ret = (devc->capture_ratio > 100) ? SR_ERR : SR_OK;
break;
case SR_CONF_VOLTAGE_THRESHOLD:
- g_variant_get(data, "(dd)", &low, &high);
if (!strcmp(devc->profile->model, "DSLogic")) {
- for (i = 0; (unsigned int)i < ARRAY_SIZE(voltage_thresholds); i++) {
- if (fabs(voltage_thresholds[i][0] - low) < 0.1 &&
- fabs(voltage_thresholds[i][1] - high) < 0.1) {
- devc->cur_threshold =
- voltage_thresholds[i][0];
- break;
- }
- }
- ret = dslogic_fpga_firmware_upload(sdi);
+ if ((idx = std_double_tuple_idx(data, ARRAY_AND_SIZE(thresholds))) < 0)
+ return SR_ERR_ARG;
+ devc->cur_threshold = thresholds[idx][0];
+ return dslogic_fpga_firmware_upload(sdi);
} else {
- ret = dslogic_set_voltage_threshold(sdi, (low + high) / 2.0);
+ g_variant_get(data, "(dd)", &low, &high);
+ return dslogic_set_voltage_threshold(sdi, (low + high) / 2.0);
}
break;
case SR_CONF_EXTERNAL_CLOCK:
devc->continuous_mode = g_variant_get_boolean(data);
break;
case SR_CONF_CLOCK_EDGE:
- i = lookup_index(data, ARRAY_AND_SIZE(signal_edge_names));
- if (i < 0)
+ if ((idx = std_str_idx(data, ARRAY_AND_SIZE(signal_edges))) < 0)
return SR_ERR_ARG;
- devc->clock_edge = i;
+ devc->clock_edge = idx;
break;
default:
- ret = SR_ERR_NA;
+ return SR_ERR_NA;
}
- return ret;
+ return SR_OK;
}
static int config_list(uint32_t key, GVariant **data,
case SR_CONF_DEVICE_OPTIONS:
return STD_CONFIG_LIST(key, data, sdi, cg, scanopts, drvopts, devopts);
case SR_CONF_VOLTAGE_THRESHOLD:
+ if (!devc || !devc->profile)
+ return SR_ERR_ARG;
if (!strcmp(devc->profile->model, "DSLogic"))
- *data = std_gvar_thresholds(ARRAY_AND_SIZE(voltage_thresholds));
+ *data = std_gvar_thresholds(ARRAY_AND_SIZE(thresholds));
else
*data = std_gvar_min_max_step_thresholds(0.0, 5.0, 0.1);
break;
case SR_CONF_SAMPLERATE:
+ if (!devc)
+ return SR_ERR_ARG;
*data = std_gvar_samplerates(devc->samplerates, devc->num_samplerates);
break;
+ case SR_CONF_TRIGGER_MATCH:
+ *data = std_gvar_array_i32(ARRAY_AND_SIZE(trigger_matches));
+ break;
case SR_CONF_CLOCK_EDGE:
- *data = g_variant_new_strv(ARRAY_AND_SIZE(signal_edge_names));
+ *data = g_variant_new_strv(ARRAY_AND_SIZE(signal_edges));
break;
default:
return SR_ERR_NA;
projects / libsigrok.git / blobdiff