src/hardware/sysclk-lwla/protocol.c

   1 /*
   2  * This file is part of the libsigrok project.
   3  *
   4  * Copyright (C) 2014 Daniel Elstner <daniel.kitta@gmail.com>
   5  *
   6  * This program is free software: you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation, either version 3 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <config.h>
  21 #include <string.h>
  22 #include "protocol.h"
  23
  24 /* Bit mask for the RLE repeat-count-follows flag. */
  25 #define RLE_FLAG_LEN_FOLLOWS ((uint64_t)1 << 35)
  26
  27 /* Start address of capture status memory area to read. */
  28 #define CAP_STAT_ADDR 5
  29
  30 /* Number of 64-bit words read from the capture status memory. */
  31 #define CAP_STAT_LEN 5
  32
  33 /* The bitstream filenames are indexed by the clock_config enumeration.
  34  */
  35 static const char bitstream_map[][32] = {
  36         "sysclk-lwla1034-off.rbf",
  37         "sysclk-lwla1034-int.rbf",
  38         "sysclk-lwla1034-extpos.rbf",
  39         "sysclk-lwla1034-extneg.rbf",
  40 };
  41
  42 /* Submit an already filled-in USB transfer.
  43  */
  44 static int submit_transfer(struct dev_context *devc,
  45                            struct libusb_transfer *xfer)
  46 {
  47         int ret;
  48
  49         ret = libusb_submit_transfer(xfer);
  50
  51         if (ret != 0) {
  52                 sr_err("Submit transfer failed: %s.", libusb_error_name(ret));
  53                 devc->transfer_error = TRUE;
  54                 return SR_ERR;
  55         }
  56
  57         return SR_OK;
  58 }
  59
  60 /* Set up the LWLA in preparation for an acquisition session.
  61  */
  62 static int capture_setup(const struct sr_dev_inst *sdi)
  63 {
  64         struct dev_context *devc;
  65         struct acquisition_state *acq;
  66         uint64_t divider_count;
  67         uint64_t trigger_mask;
  68         uint64_t memory_limit;
  69         uint16_t command[3 + (10 * 4)];
  70
  71         devc = sdi->priv;
  72         acq  = devc->acquisition;
  73
  74         command[0] = LWLA_WORD(CMD_CAP_SETUP);
  75         command[1] = LWLA_WORD(0); /* address */
  76         command[2] = LWLA_WORD(10); /* length */
  77
  78         command[3] = LWLA_WORD_0(devc->channel_mask);
  79         command[4] = LWLA_WORD_1(devc->channel_mask);
  80         command[5] = LWLA_WORD_2(devc->channel_mask);
  81         command[6] = LWLA_WORD_3(devc->channel_mask);
  82
  83         /* Set the clock divide counter maximum for samplerates of up to
  84          * 100 MHz. At the highest samplerate of 125 MHz the clock divider
  85          * is bypassed.
  86          */
  87         if (!acq->bypass_clockdiv && devc->samplerate > 0)
  88                 divider_count = SR_MHZ(100) / devc->samplerate - 1;
  89         else
  90                 divider_count = 0;
  91
  92         command[7]  = LWLA_WORD_0(divider_count);
  93         command[8]  = LWLA_WORD_1(divider_count);
  94         command[9]  = LWLA_WORD_2(divider_count);
  95         command[10] = LWLA_WORD_3(divider_count);
  96
  97         command[11] = LWLA_WORD_0(devc->trigger_values);
  98         command[12] = LWLA_WORD_1(devc->trigger_values);
  99         command[13] = LWLA_WORD_2(devc->trigger_values);
 100         command[14] = LWLA_WORD_3(devc->trigger_values);
 101
 102         command[15] = LWLA_WORD_0(devc->trigger_edge_mask);
 103         command[16] = LWLA_WORD_1(devc->trigger_edge_mask);
 104         command[17] = LWLA_WORD_2(devc->trigger_edge_mask);
 105         command[18] = LWLA_WORD_3(devc->trigger_edge_mask);
 106
 107         trigger_mask = devc->trigger_mask;
 108         /* Set bits to select external TRG input edge. */
 109         if (devc->cfg_trigger_source == TRIGGER_EXT_TRG)
 110                 switch (devc->cfg_trigger_slope) {
 111                 case EDGE_POSITIVE:
 112                         trigger_mask |= (uint64_t)1 << 35;
 113                         break;
 114                 case EDGE_NEGATIVE:
 115                         trigger_mask |= (uint64_t)1 << 34;
 116                         break;
 117                 }
 118
 119         command[19] = LWLA_WORD_0(trigger_mask);
 120         command[20] = LWLA_WORD_1(trigger_mask);
 121         command[21] = LWLA_WORD_2(trigger_mask);
 122         command[22] = LWLA_WORD_3(trigger_mask);
 123
 124         /* Set the capture memory full threshold. This is slightly less
 125          * than the actual maximum, most likely in order to compensate for
 126          * pipeline latency.
 127          */
 128         memory_limit = MEMORY_DEPTH - 16;
 129
 130         command[23] = LWLA_WORD_0(memory_limit);
 131         command[24] = LWLA_WORD_1(memory_limit);
 132         command[25] = LWLA_WORD_2(memory_limit);
 133         command[26] = LWLA_WORD_3(memory_limit);
 134
 135         /* Fill remaining words with zeroes. */
 136         memset(&command[27], 0, sizeof(command) - 27 * sizeof(command[0]));
 137
 138         return lwla_send_command(sdi->conn, command, ARRAY_SIZE(command));
 139 }
 140
 141 /* Issue a register write command as an asynchronous USB transfer.
 142  */
 143 static int issue_write_reg(const struct sr_dev_inst *sdi,
 144                            unsigned int reg, unsigned int value)
 145 {
 146         struct dev_context *devc;
 147         struct acquisition_state *acq;
 148
 149         devc = sdi->priv;
 150         acq  = devc->acquisition;
 151
 152         acq->xfer_buf_out[0] = LWLA_WORD(CMD_WRITE_REG);
 153         acq->xfer_buf_out[1] = LWLA_WORD(reg);
 154         acq->xfer_buf_out[2] = LWLA_WORD_0(value);
 155         acq->xfer_buf_out[3] = LWLA_WORD_1(value);
 156
 157         acq->xfer_out->length = 4 * sizeof(uint16_t);
 158
 159         return submit_transfer(devc, acq->xfer_out);
 160 }
 161
 162 /* Issue a register write command as an asynchronous USB transfer for the
 163  * next register/value pair of the currently active register write sequence.
 164  */
 165 static int issue_next_write_reg(const struct sr_dev_inst *sdi)
 166 {
 167         struct dev_context *devc;
 168         struct regval_pair *regval;
 169         int ret;
 170
 171         devc = sdi->priv;
 172
 173         if (devc->reg_write_pos >= devc->reg_write_len) {
 174                 sr_err("Already written all registers in sequence.");
 175                 return SR_ERR_BUG;
 176         }
 177         regval = &devc->reg_write_seq[devc->reg_write_pos];
 178
 179         ret = issue_write_reg(sdi, regval->reg, regval->val);
 180         if (ret != SR_OK)
 181                 return ret;
 182
 183         ++devc->reg_write_pos;
 184         return SR_OK;
 185 }
 186
 187 /* Issue a capture status request as an asynchronous USB transfer.
 188  */
 189 static void request_capture_status(const struct sr_dev_inst *sdi)
 190 {
 191         struct dev_context *devc;
 192         struct acquisition_state *acq;
 193
 194         devc = sdi->priv;
 195         acq  = devc->acquisition;
 196
 197         acq->xfer_buf_out[0] = LWLA_WORD(CMD_CAP_STATUS);
 198         acq->xfer_buf_out[1] = LWLA_WORD(CAP_STAT_ADDR);
 199         acq->xfer_buf_out[2] = LWLA_WORD(CAP_STAT_LEN);
 200
 201         acq->xfer_out->length = 3 * sizeof(uint16_t);
 202
 203         if (submit_transfer(devc, acq->xfer_out) == SR_OK)
 204                 devc->state = STATE_STATUS_REQUEST;
 205 }
 206
 207 /* Issue a request for the capture buffer fill level as
 208  * an asynchronous USB transfer.
 209  */
 210 static void request_capture_length(const struct sr_dev_inst *sdi)
 211 {
 212         struct dev_context *devc;
 213         struct acquisition_state *acq;
 214
 215         devc = sdi->priv;
 216         acq  = devc->acquisition;
 217
 218         acq->xfer_buf_out[0] = LWLA_WORD(CMD_READ_REG);
 219         acq->xfer_buf_out[1] = LWLA_WORD(REG_MEM_FILL);
 220
 221         acq->xfer_out->length = 2 * sizeof(uint16_t);
 222
 223         if (submit_transfer(devc, acq->xfer_out) == SR_OK)
 224                 devc->state = STATE_LENGTH_REQUEST;
 225 }
 226
 227 /* Initiate the capture memory read operation:  Reset the acquisition state
 228  * and start a sequence of register writes in order to set up the device for
 229  * reading from the capture buffer.
 230  */
 231 static void issue_read_start(const struct sr_dev_inst *sdi)
 232 {
 233         struct dev_context *devc;
 234         struct acquisition_state *acq;
 235         struct regval_pair *regvals;
 236
 237         devc = sdi->priv;
 238         acq  = devc->acquisition;
 239
 240         /* Reset RLE state. */
 241         acq->rle = RLE_STATE_DATA;
 242         acq->sample  = 0;
 243         acq->run_len = 0;
 244
 245         acq->samples_done = 0;
 246
 247         /* For some reason, the start address is 4 rather than 0. */
 248         acq->mem_addr_done = 4;
 249         acq->mem_addr_next = 4;
 250         acq->mem_addr_stop = acq->mem_addr_fill;
 251
 252         /* Sample position in the packet output buffer. */
 253         acq->out_index = 0;
 254
 255         regvals = devc->reg_write_seq;
 256
 257         regvals[0].reg = REG_DIV_BYPASS;
 258         regvals[0].val = 1;
 259
 260         regvals[1].reg = REG_MEM_CTRL;
 261         regvals[1].val = MEM_CTRL_CLR_IDX;
 262
 263         regvals[2].reg = REG_MEM_START;
 264         regvals[2].val = 4;
 265
 266         devc->reg_write_pos = 0;
 267         devc->reg_write_len = 3;
 268
 269         if (issue_next_write_reg(sdi) == SR_OK)
 270                 devc->state = STATE_READ_PREPARE;
 271 }
 272
 273 /* Issue a command as an asynchronous USB transfer which returns the device
 274  * to normal state after a read operation.  Sets a new device context state
 275  * on success.
 276  */
 277 static void issue_read_end(const struct sr_dev_inst *sdi)
 278 {
 279         struct dev_context *devc;
 280
 281         devc = sdi->priv;
 282
 283         if (issue_write_reg(sdi, REG_DIV_BYPASS, 0) == SR_OK)
 284                 devc->state = STATE_READ_END;
 285 }
 286
 287 /* Decode an incoming response to a buffer fill level request and act on it
 288  * as appropriate.  Note that this function changes the device context state.
 289  */
 290 static void process_capture_length(const struct sr_dev_inst *sdi)
 291 {
 292         struct dev_context *devc;
 293         struct acquisition_state *acq;
 294
 295         devc = sdi->priv;
 296         acq  = devc->acquisition;
 297
 298         if (acq->xfer_in->actual_length != 4) {
 299                 sr_err("Received size %d doesn't match expected size 4.",
 300                        acq->xfer_in->actual_length);
 301                 devc->transfer_error = TRUE;
 302                 return;
 303         }
 304         acq->mem_addr_fill = LWLA_TO_UINT32(acq->xfer_buf_in[0]);
 305
 306         sr_dbg("%zu words in capture buffer.", acq->mem_addr_fill);
 307
 308         if (acq->mem_addr_fill > 0 && !devc->cancel_requested)
 309                 issue_read_start(sdi);
 310         else
 311                 issue_read_end(sdi);
 312 }
 313
 314 /* Initiate a sequence of register write commands with the effect of
 315  * cancelling a running capture operation.  This sets a new device state
 316  * if issuing the first command succeeds.
 317  */
 318 static void issue_stop_capture(const struct sr_dev_inst *sdi)
 319 {
 320         struct dev_context *devc;
 321         struct regval_pair *regvals;
 322
 323         devc = sdi->priv;
 324
 325         if (devc->stopping_in_progress)
 326                 return;
 327
 328         regvals = devc->reg_write_seq;
 329
 330         regvals[0].reg = REG_LONG_ADDR;
 331         regvals[0].val = LREG_CAP_CTRL;
 332
 333         regvals[1].reg = REG_LONG_LOW;
 334         regvals[1].val = 0;
 335
 336         regvals[2].reg = REG_LONG_HIGH;
 337         regvals[2].val = 0;
 338
 339         regvals[3].reg = REG_LONG_STROBE;
 340         regvals[3].val = 0;
 341
 342         regvals[4].reg = REG_DIV_BYPASS;
 343         regvals[4].val = 0;
 344
 345         devc->reg_write_pos = 0;
 346         devc->reg_write_len = 5;
 347
 348         if (issue_next_write_reg(sdi) == SR_OK) {
 349                 devc->stopping_in_progress = TRUE;
 350                 devc->state = STATE_STOP_CAPTURE;
 351         }
 352 }
 353
 354 /* Decode an incoming capture status response and act on it as appropriate.
 355  * Note that this function changes the device state.
 356  */
 357 static void process_capture_status(const struct sr_dev_inst *sdi)
 358 {
 359         uint64_t duration;
 360         struct dev_context *devc;
 361         struct acquisition_state *acq;
 362         unsigned int mem_fill;
 363         unsigned int flags;
 364
 365         devc = sdi->priv;
 366         acq  = devc->acquisition;
 367
 368         if (acq->xfer_in->actual_length != CAP_STAT_LEN * 8) {
 369                 sr_err("Received size %d doesn't match expected size %d.",
 370                        acq->xfer_in->actual_length, CAP_STAT_LEN * 8);
 371                 devc->transfer_error = TRUE;
 372                 return;
 373         }
 374
 375         mem_fill = LWLA_TO_UINT32(acq->xfer_buf_in[0]);
 376         duration = LWLA_TO_UINT32(acq->xfer_buf_in[4])
 377                 | ((uint64_t)LWLA_TO_UINT32(acq->xfer_buf_in[5]) << 32);
 378         flags = LWLA_TO_UINT32(acq->xfer_buf_in[8]) & STATUS_FLAG_MASK;
 379
 380         /* The LWLA1034 runs at 125 MHz if the clock divider is bypassed.
 381          * However, the time base used for the duration is apparently not
 382          * adjusted for this "boost" mode.  Whereas normally the duration
 383          * unit is 1 ms, it is 0.8 ms when the clock divider is bypassed.
 384          * As 0.8 = 100 MHz / 125 MHz, it seems that the internal cycle
 385          * counter period is the same as at the 100 MHz setting.
 386          */
 387         if (acq->bypass_clockdiv)
 388                 acq->duration_now = duration * 4 / 5;
 389         else
 390                 acq->duration_now = duration;
 391
 392         sr_spew("Captured %u words, %" PRIu64 " ms, flags 0x%02X.",
 393                 mem_fill, acq->duration_now, flags);
 394
 395         if ((flags & STATUS_TRIGGERED) > (acq->capture_flags & STATUS_TRIGGERED))
 396                 sr_info("Capture triggered.");
 397
 398         acq->capture_flags = flags;
 399
 400         if (acq->duration_now >= acq->duration_max) {
 401                 sr_dbg("Time limit reached, stopping capture.");
 402                 issue_stop_capture(sdi);
 403                 return;
 404         }
 405         devc->state = STATE_STATUS_WAIT;
 406
 407         if ((acq->capture_flags & STATUS_TRIGGERED) == 0) {
 408                 sr_spew("Waiting for trigger.");
 409         } else if ((acq->capture_flags & STATUS_MEM_AVAIL) == 0) {
 410                 sr_dbg("Capture memory filled.");
 411                 request_capture_length(sdi);
 412         } else if ((acq->capture_flags & STATUS_CAPTURING) != 0) {
 413                 sr_spew("Sampling in progress.");
 414         }
 415 }
 416
 417 /* Issue a capture buffer read request as an asynchronous USB transfer.
 418  * The address and size of the memory area to read are derived from the
 419  * current acquisition state.
 420  */
 421 static void request_read_mem(const struct sr_dev_inst *sdi)
 422 {
 423         struct dev_context *devc;
 424         struct acquisition_state *acq;
 425         size_t count;
 426
 427         devc = sdi->priv;
 428         acq  = devc->acquisition;
 429
 430         if (acq->mem_addr_next >= acq->mem_addr_stop)
 431                 return;
 432
 433         /* Always read a multiple of 8 device words. */
 434         count = (acq->mem_addr_stop - acq->mem_addr_next + 7) / 8 * 8;
 435         count = MIN(count, READ_CHUNK_LEN);
 436
 437         acq->xfer_buf_out[0] = LWLA_WORD(CMD_READ_MEM);
 438         acq->xfer_buf_out[1] = LWLA_WORD_0(acq->mem_addr_next);
 439         acq->xfer_buf_out[2] = LWLA_WORD_1(acq->mem_addr_next);
 440         acq->xfer_buf_out[3] = LWLA_WORD_0(count);
 441         acq->xfer_buf_out[4] = LWLA_WORD_1(count);
 442
 443         acq->xfer_out->length = 5 * sizeof(uint16_t);
 444
 445         if (submit_transfer(devc, acq->xfer_out) == SR_OK) {
 446                 acq->mem_addr_next += count;
 447                 devc->state = STATE_READ_REQUEST;
 448         }
 449 }
 450
 451 /* Demangle and decompress incoming sample data from the capture buffer.
 452  * The data chunk is taken from the acquisition state, and is expected to
 453  * contain a multiple of 8 device words.
 454  * All data currently in the acquisition buffer will be processed.  Packets
 455  * of decoded samples are sent off to the session bus whenever the output
 456  * buffer becomes full while decoding.
 457  */
 458 static int process_sample_data(const struct sr_dev_inst *sdi)
 459 {
 460         uint64_t sample;
 461         uint64_t high_nibbles;
 462         uint64_t word;
 463         struct dev_context *devc;
 464         struct acquisition_state *acq;
 465         uint8_t *out_p;
 466         uint32_t *slice;
 467         struct sr_datafeed_packet packet;
 468         struct sr_datafeed_logic logic;
 469         size_t expect_len;
 470         size_t actual_len;
 471         size_t out_max_samples;
 472         size_t out_run_samples;
 473         size_t ri;
 474         size_t in_words_left;
 475         size_t si;
 476
 477         devc = sdi->priv;
 478         acq  = devc->acquisition;
 479
 480         if (acq->mem_addr_done >= acq->mem_addr_stop
 481                         || acq->samples_done >= acq->samples_max)
 482                 return SR_OK;
 483
 484         in_words_left = MIN(acq->mem_addr_stop - acq->mem_addr_done,
 485                             READ_CHUNK_LEN);
 486         expect_len = LWLA1034_MEMBUF_LEN(in_words_left) * sizeof(uint32_t);
 487         actual_len = acq->xfer_in->actual_length;
 488
 489         if (actual_len != expect_len) {
 490                 sr_err("Received size %zu does not match expected size %zu.",
 491                        actual_len, expect_len);
 492                 devc->transfer_error = TRUE;
 493                 return SR_ERR;
 494         }
 495         acq->mem_addr_done += in_words_left;
 496
 497         /* Prepare session packet. */
 498         packet.type    = SR_DF_LOGIC;
 499         packet.payload = &logic;
 500         logic.unitsize = UNIT_SIZE;
 501         logic.data     = acq->out_packet;
 502
 503         slice = acq->xfer_buf_in;
 504         si = 0; /* word index within slice */
 505
 506         for (;;) {
 507                 /* Calculate number of samples to write into packet. */
 508                 out_max_samples = MIN(acq->samples_max - acq->samples_done,
 509                                       PACKET_LENGTH - acq->out_index);
 510                 out_run_samples = MIN(acq->run_len, out_max_samples);
 511
 512                 /* Expand run-length samples into session packet. */
 513                 sample = acq->sample;
 514                 out_p = &acq->out_packet[acq->out_index * UNIT_SIZE];
 515
 516                 for (ri = 0; ri < out_run_samples; ++ri) {
 517                         out_p[0] =  sample        & 0xFF;
 518                         out_p[1] = (sample >>  8) & 0xFF;
 519                         out_p[2] = (sample >> 16) & 0xFF;
 520                         out_p[3] = (sample >> 24) & 0xFF;
 521                         out_p[4] = (sample >> 32) & 0xFF;
 522                         out_p += UNIT_SIZE;
 523                 }
 524                 acq->run_len -= out_run_samples;
 525                 acq->out_index += out_run_samples;
 526                 acq->samples_done += out_run_samples;
 527
 528                 /* Packet full or sample count limit reached? */
 529                 if (out_run_samples == out_max_samples) {
 530                         logic.length = acq->out_index * UNIT_SIZE;
 531                         sr_session_send(sdi, &packet);
 532                         acq->out_index = 0;
 533
 534                         if (acq->samples_done >= acq->samples_max)
 535                                 return SR_OK; /* sample limit reached */
 536                         if (acq->run_len > 0)
 537                                 continue; /* need another packet */
 538                 }
 539
 540                 if (in_words_left == 0)
 541                         break; /* done with current chunk */
 542
 543                 /* Now work on the current slice. */
 544                 high_nibbles = LWLA_TO_UINT32(slice[8]);
 545                 word = LWLA_TO_UINT32(slice[si]);
 546                 word |= (high_nibbles << (4 * si + 4)) & ((uint64_t)0xF << 32);
 547
 548                 if (acq->rle == RLE_STATE_DATA) {
 549                         acq->sample = word & ALL_CHANNELS_MASK;
 550                         acq->run_len = ((word >> NUM_CHANNELS) & 1) + 1;
 551                         if (word & RLE_FLAG_LEN_FOLLOWS)
 552                                 acq->rle = RLE_STATE_LEN;
 553                 } else {
 554                         acq->run_len += word << 1;
 555                         acq->rle = RLE_STATE_DATA;
 556                 }
 557
 558                 /* Move to next word. */
 559                 si = (si + 1) % 8;
 560                 if (si == 0)
 561                         slice += 9;
 562                 --in_words_left;
 563         }
 564
 565         /* Send out partially filled packet if this was the last chunk. */
 566         if (acq->mem_addr_done >= acq->mem_addr_stop && acq->out_index > 0) {
 567                 logic.length = acq->out_index * UNIT_SIZE;
 568                 sr_session_send(sdi, &packet);
 569                 acq->out_index = 0;
 570         }
 571         return SR_OK;
 572 }
 573
 574 /* Finish an acquisition session.  This sends the end packet to the session
 575  * bus and removes the listener for asynchronous USB transfers.
 576  */
 577 static void end_acquisition(struct sr_dev_inst *sdi)
 578 {
 579         struct drv_context *drvc;
 580         struct dev_context *devc;
 581         struct sr_datafeed_packet packet;
 582
 583         drvc = sdi->driver->context;
 584         devc = sdi->priv;
 585
 586         if (devc->state == STATE_IDLE)
 587                 return;
 588
 589         devc->state = STATE_IDLE;
 590
 591         /* Remove USB file descriptors from polling. */
 592         usb_source_remove(sdi->session, drvc->sr_ctx);
 593
 594         packet.type = SR_DF_END;
 595         sr_session_send(sdi, &packet);
 596
 597         lwla_free_acquisition_state(devc->acquisition);
 598         devc->acquisition = NULL;
 599         devc->cancel_requested = FALSE;
 600 }
 601
 602 /* USB output transfer completion callback.
 603  */
 604 static void LIBUSB_CALL receive_transfer_out(struct libusb_transfer *transfer)
 605 {
 606         struct sr_dev_inst *sdi;
 607         struct dev_context *devc;
 608
 609         sdi  = transfer->user_data;
 610         devc = sdi->priv;
 611
 612         if (transfer->status != LIBUSB_TRANSFER_COMPLETED) {
 613                 sr_err("Transfer to device failed: %d.", transfer->status);
 614                 devc->transfer_error = TRUE;
 615                 return;
 616         }
 617
 618         if (devc->reg_write_pos < devc->reg_write_len) {
 619                 issue_next_write_reg(sdi);
 620         } else {
 621                 switch (devc->state) {
 622                 case STATE_START_CAPTURE:
 623                         devc->state = STATE_STATUS_WAIT;
 624                         break;
 625                 case STATE_STATUS_REQUEST:
 626                         devc->state = STATE_STATUS_RESPONSE;
 627                         submit_transfer(devc, devc->acquisition->xfer_in);
 628                         break;
 629                 case STATE_STOP_CAPTURE:
 630                         if (!devc->cancel_requested)
 631                                 request_capture_length(sdi);
 632                         else
 633                                 end_acquisition(sdi);
 634                         break;
 635                 case STATE_LENGTH_REQUEST:
 636                         devc->state = STATE_LENGTH_RESPONSE;
 637                         submit_transfer(devc, devc->acquisition->xfer_in);
 638                         break;
 639                 case STATE_READ_PREPARE:
 640                         request_read_mem(sdi);
 641                         break;
 642                 case STATE_READ_REQUEST:
 643                         devc->state = STATE_READ_RESPONSE;
 644                         submit_transfer(devc, devc->acquisition->xfer_in);
 645                         break;
 646                 case STATE_READ_END:
 647                         end_acquisition(sdi);
 648                         break;
 649                 default:
 650                         sr_err("Unexpected device state %d.", devc->state);
 651                         break;
 652                 }
 653         }
 654 }
 655
 656 /* USB input transfer completion callback.
 657  */
 658 static void LIBUSB_CALL receive_transfer_in(struct libusb_transfer *transfer)
 659 {
 660         struct sr_dev_inst *sdi;
 661         struct dev_context *devc;
 662         struct acquisition_state *acq;
 663
 664         sdi  = transfer->user_data;
 665         devc = sdi->priv;
 666         acq  = devc->acquisition;
 667
 668         if (transfer->status != LIBUSB_TRANSFER_COMPLETED) {
 669                 sr_err("Transfer from device failed: %d.", transfer->status);
 670                 devc->transfer_error = TRUE;
 671                 return;
 672         }
 673
 674         switch (devc->state) {
 675         case STATE_STATUS_RESPONSE:
 676                 process_capture_status(sdi);
 677                 break;
 678         case STATE_LENGTH_RESPONSE:
 679                 process_capture_length(sdi);
 680                 break;
 681         case STATE_READ_RESPONSE:
 682                 if (process_sample_data(sdi) == SR_OK
 683                                 && acq->mem_addr_next < acq->mem_addr_stop
 684                                 && acq->samples_done < acq->samples_max)
 685                         request_read_mem(sdi);
 686                 else
 687                         issue_read_end(sdi);
 688                 break;
 689         default:
 690                 sr_err("Unexpected device state %d.", devc->state);
 691                 break;
 692         }
 693 }
 694
 695 /* Initialize the LWLA.  This downloads a bitstream into the FPGA
 696  * and executes a simple device test sequence.
 697  */
 698 SR_PRIV int lwla_init_device(const struct sr_dev_inst *sdi)
 699 {
 700         uint64_t value;
 701         struct dev_context *devc;
 702         int ret;
 703
 704         devc = sdi->priv;
 705
 706         /* Force reload of bitstream */
 707         devc->cur_clock_config = CONF_CLOCK_NONE;
 708
 709         ret = lwla_set_clock_config(sdi);
 710         if (ret != SR_OK)
 711                 return ret;
 712
 713         ret = lwla_read_long_reg(sdi->conn, LREG_TEST_ID, &value);
 714         if (ret != SR_OK)
 715                 return ret;
 716
 717         /* Ignore the value returned by the first read */
 718         ret = lwla_read_long_reg(sdi->conn, LREG_TEST_ID, &value);
 719         if (ret != SR_OK)
 720                 return ret;
 721
 722         if (value != UINT64_C(0x1234567887654321)) {
 723                 sr_err("Received invalid test word 0x%016" PRIX64 ".", value);
 724                 return SR_ERR;
 725         }
 726         return SR_OK;
 727 }
 728
 729 /* Select the LWLA clock configuration.  If the clock source changed from
 730  * the previous setting, this will download a new bitstream to the FPGA.
 731  */
 732 SR_PRIV int lwla_set_clock_config(const struct sr_dev_inst *sdi)
 733 {
 734         struct dev_context *devc;
 735         struct drv_context *drvc;
 736         int ret;
 737         enum clock_config choice;
 738
 739         devc = sdi->priv;
 740         drvc = sdi->driver->context;
 741
 742         if (sdi->status == SR_ST_INACTIVE)
 743                 choice = CONF_CLOCK_NONE;
 744         else if (devc->cfg_clock_source == CLOCK_INTERNAL)
 745                 choice = CONF_CLOCK_INT;
 746         else if (devc->cfg_clock_edge == EDGE_POSITIVE)
 747                 choice = CONF_CLOCK_EXT_RISE;
 748         else
 749                 choice = CONF_CLOCK_EXT_FALL;
 750
 751         if (choice != devc->cur_clock_config) {
 752                 devc->cur_clock_config = CONF_CLOCK_NONE;
 753                 ret = lwla_send_bitstream(drvc->sr_ctx, sdi->conn,
 754                                           bitstream_map[choice]);
 755                 if (ret == SR_OK)
 756                         devc->cur_clock_config = choice;
 757                 return ret;
 758         }
 759         return SR_OK;
 760 }
 761
 762 /* Configure the LWLA in preparation for an acquisition session.
 763  */
 764 SR_PRIV int lwla_setup_acquisition(const struct sr_dev_inst *sdi)
 765 {
 766         struct dev_context *devc;
 767         struct sr_usb_dev_inst *usb;
 768         struct acquisition_state *acq;
 769         struct regval_pair regvals[7];
 770         int ret;
 771
 772         devc = sdi->priv;
 773         usb  = sdi->conn;
 774         acq  = devc->acquisition;
 775
 776         if (devc->limit_msec > 0) {
 777                 acq->duration_max = devc->limit_msec;
 778                 sr_info("Acquisition time limit %" PRIu64 " ms.",
 779                         devc->limit_msec);
 780         } else
 781                 acq->duration_max = MAX_LIMIT_MSEC;
 782
 783         if (devc->limit_samples > 0) {
 784                 acq->samples_max = devc->limit_samples;
 785                 sr_info("Acquisition sample count limit %" PRIu64 ".",
 786                         devc->limit_samples);
 787         } else
 788                 acq->samples_max = MAX_LIMIT_SAMPLES;
 789
 790         if (devc->cfg_clock_source == CLOCK_INTERNAL) {
 791                 sr_info("Internal clock, samplerate %" PRIu64 ".",
 792                         devc->samplerate);
 793                 if (devc->samplerate == 0)
 794                         return SR_ERR_BUG;
 795                 /* At 125 MHz, the clock divider is bypassed. */
 796                 acq->bypass_clockdiv = (devc->samplerate > SR_MHZ(100));
 797
 798                 /* If only one of the limits is set, derive the other one. */
 799                 if (devc->limit_msec == 0 && devc->limit_samples > 0)
 800                         acq->duration_max = devc->limit_samples
 801                                         * 1000 / devc->samplerate + 1;
 802                 else if (devc->limit_samples == 0 && devc->limit_msec > 0)
 803                         acq->samples_max = devc->limit_msec
 804                                         * devc->samplerate / 1000;
 805         } else {
 806                 acq->bypass_clockdiv = TRUE;
 807
 808                 if (devc->cfg_clock_edge == EDGE_NEGATIVE)
 809                         sr_info("External clock, falling edge.");
 810                 else
 811                         sr_info("External clock, rising edge.");
 812         }
 813
 814         regvals[0].reg = REG_MEM_CTRL;
 815         regvals[0].val = MEM_CTRL_CLR_IDX;
 816
 817         regvals[1].reg = REG_MEM_CTRL;
 818         regvals[1].val = MEM_CTRL_WRITE;
 819
 820         regvals[2].reg = REG_LONG_ADDR;
 821         regvals[2].val = LREG_CAP_CTRL;
 822
 823         regvals[3].reg = REG_LONG_LOW;
 824         regvals[3].val = CAP_CTRL_CLR_TIMEBASE | CAP_CTRL_FLUSH_FIFO
 825                        | CAP_CTRL_CLR_FIFOFULL | CAP_CTRL_CLR_COUNTER;
 826         regvals[4].reg = REG_LONG_HIGH;
 827         regvals[4].val = 0;
 828
 829         regvals[5].reg = REG_LONG_STROBE;
 830         regvals[5].val = 0;
 831
 832         regvals[6].reg = REG_DIV_BYPASS;
 833         regvals[6].val = acq->bypass_clockdiv;
 834
 835         ret = lwla_write_regs(usb, regvals, ARRAY_SIZE(regvals));
 836         if (ret != SR_OK)
 837                 return ret;
 838
 839         return capture_setup(sdi);
 840 }
 841
 842 /* Start the capture operation on the LWLA device.  Beginning with this
 843  * function, all USB transfers will be asynchronous until the end of the
 844  * acquisition session.
 845  */
 846 SR_PRIV int lwla_start_acquisition(const struct sr_dev_inst *sdi)
 847 {
 848         struct dev_context *devc;
 849         struct sr_usb_dev_inst *usb;
 850         struct acquisition_state *acq;
 851         struct regval_pair *regvals;
 852
 853         devc = sdi->priv;
 854         usb  = sdi->conn;
 855         acq  = devc->acquisition;
 856
 857         acq->duration_now  = 0;
 858         acq->mem_addr_fill = 0;
 859         acq->capture_flags = 0;
 860
 861         libusb_fill_bulk_transfer(acq->xfer_out, usb->devhdl, EP_COMMAND,
 862                                   (unsigned char *)acq->xfer_buf_out, 0,
 863                                   &receive_transfer_out,
 864                                   (struct sr_dev_inst *)sdi, USB_TIMEOUT_MS);
 865
 866         libusb_fill_bulk_transfer(acq->xfer_in, usb->devhdl, EP_REPLY,
 867                                   (unsigned char *)acq->xfer_buf_in,
 868                                   sizeof acq->xfer_buf_in,
 869                                   &receive_transfer_in,
 870                                   (struct sr_dev_inst *)sdi, USB_TIMEOUT_MS);
 871
 872         regvals = devc->reg_write_seq;
 873
 874         regvals[0].reg = REG_LONG_ADDR;
 875         regvals[0].val = LREG_CAP_CTRL;
 876
 877         regvals[1].reg = REG_LONG_LOW;
 878         regvals[1].val = CAP_CTRL_TRG_EN;
 879
 880         regvals[2].reg = REG_LONG_HIGH;
 881         regvals[2].val = 0;
 882
 883         regvals[3].reg = REG_LONG_STROBE;
 884         regvals[3].val = 0;
 885
 886         devc->reg_write_pos = 0;
 887         devc->reg_write_len = 4;
 888
 889         devc->state = STATE_START_CAPTURE;
 890
 891         return issue_next_write_reg(sdi);
 892 }
 893
 894 /* Allocate an acquisition state object.
 895  */
 896 SR_PRIV struct acquisition_state *lwla_alloc_acquisition_state(void)
 897 {
 898         struct acquisition_state *acq;
 899
 900         acq = g_malloc0(sizeof(struct acquisition_state));
 901
 902         acq->xfer_in = libusb_alloc_transfer(0);
 903         if (!acq->xfer_in) {
 904                 sr_err("Transfer malloc failed.");
 905                 g_free(acq);
 906                 return NULL;
 907         }
 908
 909         acq->xfer_out = libusb_alloc_transfer(0);
 910         if (!acq->xfer_out) {
 911                 sr_err("Transfer malloc failed.");
 912                 libusb_free_transfer(acq->xfer_in);
 913                 g_free(acq);
 914                 return NULL;
 915         }
 916
 917         return acq;
 918 }
 919
 920 /* Deallocate an acquisition state object.
 921  */
 922 SR_PRIV void lwla_free_acquisition_state(struct acquisition_state *acq)
 923 {
 924         if (acq) {
 925                 libusb_free_transfer(acq->xfer_out);
 926                 libusb_free_transfer(acq->xfer_in);
 927                 g_free(acq);
 928         }
 929 }
 930
 931 /* USB I/O source callback.
 932  */
 933 SR_PRIV int lwla_receive_data(int fd, int revents, void *cb_data)
 934 {
 935         struct sr_dev_inst *sdi;
 936         struct dev_context *devc;
 937         struct drv_context *drvc;
 938         struct timeval tv;
 939         int ret;
 940
 941         (void)fd;
 942
 943         sdi  = cb_data;
 944         devc = sdi->priv;
 945         drvc = sdi->driver->context;
 946
 947         if (!devc || !drvc)
 948                 return FALSE;
 949
 950         /* No timeout: return immediately. */
 951         tv.tv_sec  = 0;
 952         tv.tv_usec = 0;
 953
 954         ret = libusb_handle_events_timeout_completed(drvc->sr_ctx->libusb_ctx,
 955                                                      &tv, NULL);
 956         if (ret != 0)
 957                 sr_err("Event handling failed: %s.", libusb_error_name(ret));
 958
 959         /* If no event flags are set the timeout must have expired. */
 960         if (revents == 0 && devc->state == STATE_STATUS_WAIT) {
 961                 if (devc->cancel_requested)
 962                         issue_stop_capture(sdi);
 963                 else
 964                         request_capture_status(sdi);
 965         }
 966
 967         /* Check if an error occurred on a transfer. */
 968         if (devc->transfer_error)
 969                 end_acquisition(sdi);
 970
 971         return TRUE;
 972 }