2 * This file is part of the libsigrok project.
4 * Copyright (C) 2015 Daniel Elstner <daniel.kitta@gmail.com>
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 /* Number of logic channels.
26 #define NUM_CHANNELS 34
28 /* Bit mask covering all logic channels.
30 #define ALL_CHANNELS_MASK ((UINT64_C(1) << NUM_CHANNELS) - 1)
32 /* Unit size for the sigrok logic datafeed.
34 #define UNIT_SIZE ((NUM_CHANNELS + 7) / 8)
36 /* Size of the acquisition buffer in device memory units.
38 #define MEMORY_DEPTH (256 * 1024) /* 256k x 36 bit */
40 /* Capture memory read start address.
42 #define READ_START_ADDR 4
44 /* Number of device memory units (36 bit) to read at a time. Slices of 8
45 * consecutive 36-bit words are mapped to 9 32-bit words each, so the chunk
46 * length should be a multiple of 8 to ensure alignment to slice boundaries.
48 * Experimentation has shown that reading chunks larger than about 1024 bytes
49 * is unreliable. The threshold seems to relate to the buffer size on the FX2
50 * USB chip: The configured endpoint buffer size is 512, and with double or
51 * triple buffering enabled a multiple of 512 bytes can be kept in fly.
53 * The vendor software limits reads to 120 words (15 slices, 540 bytes) at
54 * a time. So far, it appears safe to increase this to 224 words (28 slices,
55 * 1008 bytes), thus making the most of two 512 byte buffers.
57 #define READ_CHUNK_LEN (28 * 8)
59 /* Bit mask for the RLE repeat-count-follows flag.
61 #define RLE_FLAG_LEN_FOLLOWS (UINT64_C(1) << 35)
63 /* Start index and count for bulk long register reads.
64 * The first five long registers do not return useful values when read,
65 * so skip over them to reduce the transfer size of status poll responses.
67 #define READ_LREGS_START LREG_MEM_FILL
68 #define READ_LREGS_COUNT (LREG_STATUS + 1 - READ_LREGS_START)
70 /** LWLA1034 register addresses.
73 REG_MEM_CTRL = 0x1074, /* capture buffer control */
74 REG_MEM_FILL = 0x1078, /* capture buffer fill level */
75 REG_MEM_START = 0x107C, /* capture buffer start address */
77 REG_CLK_BOOST = 0x1094, /* logic clock boost flag */
79 REG_LONG_STROBE = 0x10B0, /* long register read/write strobe */
80 REG_LONG_ADDR = 0x10B4, /* long register address */
81 REG_LONG_LOW = 0x10B8, /* long register low word */
82 REG_LONG_HIGH = 0x10BC, /* long register high word */
85 /** Flag bits for REG_MEM_CTRL.
88 MEM_CTRL_WRITE = 1 << 0, /* "wr1rd0" bit */
89 MEM_CTRL_CLR_IDX = 1 << 1, /* "clr_idx" bit */
92 /* LWLA1034 long register addresses.
95 LREG_CHAN_MASK = 0, /* channel enable mask */
96 LREG_DIV_COUNT = 1, /* clock divider max count */
97 LREG_TRG_VALUE = 2, /* trigger level/slope bits */
98 LREG_TRG_TYPE = 3, /* trigger type bits (level or edge) */
99 LREG_TRG_ENABLE = 4, /* trigger enable mask */
100 LREG_MEM_FILL = 5, /* capture memory fill level or limit */
102 LREG_DURATION = 7, /* elapsed time in ms (0.8 ms at 125 MS/s) */
103 LREG_CHAN_STATE = 8, /* current logic levels at the inputs */
104 LREG_STATUS = 9, /* capture status flags */
106 LREG_CAP_CTRL = 10, /* capture control bits */
107 LREG_TEST_ID = 100, /* constant test ID */
110 /** Flag bits for LREG_CAP_CTRL.
113 CAP_CTRL_TRG_EN = 1 << 0, /* "trg_en" bit */
114 CAP_CTRL_CLR_TIMEBASE = 1 << 2, /* "do_clr_timebase" bit */
115 CAP_CTRL_FLUSH_FIFO = 1 << 4, /* "flush_fifo" bit */
116 CAP_CTRL_CLR_FIFOFULL = 1 << 5, /* "clr_fifo32_ful" bit */
117 CAP_CTRL_CLR_COUNTER = 1 << 6, /* "clr_cntr0" bit */
120 /* Available FPGA configurations.
123 FPGA_OFF = 0, /* FPGA shutdown config */
124 FPGA_INT, /* internal clock config */
125 FPGA_EXTPOS, /* external clock, rising edge config */
126 FPGA_EXTNEG, /* external clock, falling edge config */
129 /* FPGA bitstream resource filenames.
131 static const char bitstream_map[][32] = {
132 [FPGA_OFF] = "sysclk-lwla1034-off.rbf",
133 [FPGA_INT] = "sysclk-lwla1034-int.rbf",
134 [FPGA_EXTPOS] = "sysclk-lwla1034-extpos.rbf",
135 [FPGA_EXTNEG] = "sysclk-lwla1034-extneg.rbf",
138 /* Read 64-bit long register.
140 static int read_long_reg(const struct sr_usb_dev_inst *usb,
141 uint32_t addr, uint64_t *value)
143 uint32_t low, high, dummy;
146 ret = lwla_write_reg(usb, REG_LONG_ADDR, addr);
150 ret = lwla_read_reg(usb, REG_LONG_STROBE, &dummy);
154 ret = lwla_read_reg(usb, REG_LONG_HIGH, &high);
158 ret = lwla_read_reg(usb, REG_LONG_LOW, &low);
162 *value = ((uint64_t)high << 32) | low;
167 /* Queue access sequence for a long register write.
169 static void queue_long_regval(struct acquisition_state *acq,
170 uint32_t addr, uint64_t value)
172 lwla_queue_regval(acq, REG_LONG_ADDR, addr);
173 lwla_queue_regval(acq, REG_LONG_LOW, value & 0xFFFFFFFF);
174 lwla_queue_regval(acq, REG_LONG_HIGH, value >> 32);
175 lwla_queue_regval(acq, REG_LONG_STROBE, 0);
178 /* Helper to fill in the long register bulk write command.
180 static inline void bulk_long_set(struct acquisition_state *acq,
181 unsigned int idx, uint64_t value)
183 acq->xfer_buf_out[4 * idx + 3] = LWLA_WORD_0(value);
184 acq->xfer_buf_out[4 * idx + 4] = LWLA_WORD_1(value);
185 acq->xfer_buf_out[4 * idx + 5] = LWLA_WORD_2(value);
186 acq->xfer_buf_out[4 * idx + 6] = LWLA_WORD_3(value);
189 /* Helper for dissecting the response to a long register bulk read.
191 static inline uint64_t bulk_long_get(const struct acquisition_state *acq,
196 low = LWLA_TO_UINT32(acq->xfer_buf_in[2 * (idx - READ_LREGS_START)]);
197 high = LWLA_TO_UINT32(acq->xfer_buf_in[2 * (idx - READ_LREGS_START) + 1]);
199 return (high << 32) | low;
202 /* Demangle and decompress incoming sample data from the transfer buffer.
203 * The data chunk is taken from the acquisition state, and is expected to
204 * contain a multiple of 8 packed 36-bit words.
206 static void read_response(struct acquisition_state *acq)
208 uint64_t sample, high_nibbles, word;
211 unsigned int words_left;
212 unsigned int max_samples, run_samples;
213 unsigned int wi, ri, si;
215 /* Number of 36-bit words remaining in the transfer buffer. */
216 words_left = MIN(acq->mem_addr_next, acq->mem_addr_stop)
217 - acq->mem_addr_done;
219 for (wi = 0;; wi++) {
220 /* Calculate number of samples to write into packet. */
221 max_samples = MIN(acq->samples_max - acq->samples_done,
222 PACKET_SIZE / UNIT_SIZE - acq->out_index);
223 run_samples = MIN(max_samples, acq->run_len);
225 /* Expand run-length samples into session packet. */
226 sample = acq->sample;
227 out_p = &acq->out_packet[acq->out_index * UNIT_SIZE];
229 for (ri = 0; ri < run_samples; ri++) {
230 out_p[0] = sample & 0xFF;
231 out_p[1] = (sample >> 8) & 0xFF;
232 out_p[2] = (sample >> 16) & 0xFF;
233 out_p[3] = (sample >> 24) & 0xFF;
234 out_p[4] = (sample >> 32) & 0xFF;
237 acq->run_len -= run_samples;
238 acq->out_index += run_samples;
239 acq->samples_done += run_samples;
241 if (run_samples == max_samples)
242 break; /* packet full or sample limit reached */
243 if (wi >= words_left)
244 break; /* done with current transfer */
246 /* Get the current slice of 8 packed 36-bit words. */
247 slice = &acq->xfer_buf_in[(acq->in_index + wi) / 8 * 9];
248 si = (acq->in_index + wi) % 8; /* word index within slice */
250 /* Extract the next 36-bit word. */
251 high_nibbles = LWLA_TO_UINT32(slice[8]);
252 word = LWLA_TO_UINT32(slice[si]);
253 word |= (high_nibbles << (4 * si + 4)) & (UINT64_C(0xF) << 32);
255 if (acq->rle == RLE_STATE_DATA) {
256 acq->sample = word & ALL_CHANNELS_MASK;
257 acq->run_len = ((word >> NUM_CHANNELS) & 1) + 1;
258 acq->rle = ((word & RLE_FLAG_LEN_FOLLOWS) != 0)
259 ? RLE_STATE_LEN : RLE_STATE_DATA;
261 acq->run_len += word << 1;
262 acq->rle = RLE_STATE_DATA;
266 acq->mem_addr_done += wi;
269 /* Check whether we can receive responses of more than 64 bytes.
270 * The FX2 firmware of the LWLA1034 has a bug in the reset logic which
271 * sometimes causes the response endpoint to be limited to transfers of
272 * 64 bytes at a time, instead of the expected 2*512 bytes. The problem
273 * can be worked around by never requesting more than 64 bytes.
274 * This quirk manifests itself only under certain conditions, and some
275 * users seem to see it more frequently than others. Detect it here in
276 * order to avoid paying the penalty unnecessarily.
278 static int detect_short_transfer_quirk(const struct sr_dev_inst *sdi)
280 struct dev_context *devc;
281 struct sr_usb_dev_inst *usb;
285 unsigned char buf[512];
287 const int lreg_count = 10;
292 command[0] = LWLA_WORD(CMD_READ_LREGS);
293 command[1] = LWLA_WORD(0);
294 command[2] = LWLA_WORD(lreg_count);
296 ret = lwla_send_command(usb, command, ARRAY_SIZE(command));
300 ret = lwla_receive_reply(usb, buf, sizeof(buf), &xfer_len);
304 devc->short_transfer_quirk = (xfer_len == 64);
306 if (xfer_len == 8 * lreg_count)
309 if (xfer_len == 64) {
310 /* Drain the tailing portion of the split transfer. */
311 ret = lwla_receive_reply(usb, buf, sizeof(buf), &xfer_len);
315 if (xfer_len == 8 * lreg_count - 64)
318 sr_err("Received response of unexpected length %d.", xfer_len);
323 /* Select and transfer FPGA bitstream for the current configuration.
325 static int apply_fpga_config(const struct sr_dev_inst *sdi)
327 struct dev_context *devc;
328 struct drv_context *drvc;
333 drvc = sdi->driver->context;
335 if (sdi->status == SR_ST_INACTIVE)
337 else if (devc->cfg_clock_source == CLOCK_INTERNAL)
339 else if (devc->cfg_clock_edge == EDGE_POSITIVE)
340 config = FPGA_EXTPOS;
342 config = FPGA_EXTNEG;
344 if (config == devc->active_fpga_config)
345 return SR_OK; /* no change */
347 ret = lwla_send_bitstream(drvc->sr_ctx, sdi->conn,
348 bitstream_map[config]);
349 devc->active_fpga_config = (ret == SR_OK) ? config : FPGA_NOCONF;
354 /* Perform initialization self test.
356 static int device_init_check(const struct sr_dev_inst *sdi)
361 read_long_reg(sdi->conn, LREG_TEST_ID, &value);
363 /* Ignore the value returned by the first read. */
364 ret = read_long_reg(sdi->conn, LREG_TEST_ID, &value);
368 if (value != UINT64_C(0x1234567887654321)) {
369 sr_err("Received invalid test word 0x%016" PRIX64 ".", value);
373 return detect_short_transfer_quirk(sdi);
376 /* Set up the device in preparation for an acquisition session.
378 static int setup_acquisition(const struct sr_dev_inst *sdi)
380 static const struct regval capture_init[] = {
381 {REG_MEM_CTRL, MEM_CTRL_CLR_IDX},
382 {REG_MEM_CTRL, MEM_CTRL_WRITE},
383 {REG_LONG_ADDR, LREG_CAP_CTRL},
384 {REG_LONG_LOW, CAP_CTRL_CLR_TIMEBASE | CAP_CTRL_FLUSH_FIFO |
385 CAP_CTRL_CLR_FIFOFULL | CAP_CTRL_CLR_COUNTER},
387 {REG_LONG_STROBE, 0},
389 uint64_t divider_count;
390 uint64_t trigger_mask;
391 struct dev_context *devc;
392 struct sr_usb_dev_inst *usb;
393 struct acquisition_state *acq;
398 acq = devc->acquisition;
400 ret = lwla_write_regs(usb, capture_init, ARRAY_SIZE(capture_init));
404 ret = lwla_write_reg(usb, REG_CLK_BOOST, acq->clock_boost);
408 acq->xfer_buf_out[0] = LWLA_WORD(CMD_WRITE_LREGS);
409 acq->xfer_buf_out[1] = LWLA_WORD(0);
410 acq->xfer_buf_out[2] = LWLA_WORD(LREG_STATUS + 1);
412 bulk_long_set(acq, LREG_CHAN_MASK, devc->channel_mask);
414 if (devc->samplerate > 0 && devc->samplerate <= SR_MHZ(100)
415 && !acq->clock_boost)
416 divider_count = SR_MHZ(100) / devc->samplerate - 1;
420 bulk_long_set(acq, LREG_DIV_COUNT, divider_count);
421 bulk_long_set(acq, LREG_TRG_VALUE, devc->trigger_values);
422 bulk_long_set(acq, LREG_TRG_TYPE, devc->trigger_edge_mask);
424 trigger_mask = devc->trigger_mask;
426 /* Set bits to select external TRG input edge. */
427 if (devc->cfg_trigger_source == TRIGGER_EXT_TRG)
428 switch (devc->cfg_trigger_slope) {
430 trigger_mask |= UINT64_C(1) << 35;
433 trigger_mask |= UINT64_C(1) << 34;
437 bulk_long_set(acq, LREG_TRG_ENABLE, trigger_mask);
439 /* Set the capture memory full threshold. This is slightly less
440 * than the actual maximum, most likely in order to compensate for
443 bulk_long_set(acq, LREG_MEM_FILL, MEMORY_DEPTH - 16);
445 /* Fill remaining words with zeroes. */
446 bulk_long_set(acq, 6, 0);
447 bulk_long_set(acq, LREG_DURATION, 0);
448 bulk_long_set(acq, LREG_CHAN_STATE, 0);
449 bulk_long_set(acq, LREG_STATUS, 0);
451 return lwla_send_command(sdi->conn, acq->xfer_buf_out,
452 3 + (LREG_STATUS + 1) * 4);
455 static int prepare_request(const struct sr_dev_inst *sdi)
457 struct dev_context *devc;
458 struct acquisition_state *acq;
459 unsigned int chunk_len, remaining, count;
462 acq = devc->acquisition;
464 acq->xfer_out->length = 0;
465 acq->reg_seq_pos = 0;
466 acq->reg_seq_len = 0;
468 switch (devc->state) {
469 case STATE_START_CAPTURE:
470 queue_long_regval(acq, LREG_CAP_CTRL, CAP_CTRL_TRG_EN);
472 case STATE_STOP_CAPTURE:
473 queue_long_regval(acq, LREG_CAP_CTRL, 0);
474 lwla_queue_regval(acq, REG_CLK_BOOST, 0);
476 case STATE_READ_PREPARE:
477 lwla_queue_regval(acq, REG_CLK_BOOST, 1);
478 lwla_queue_regval(acq, REG_MEM_CTRL, MEM_CTRL_CLR_IDX);
479 lwla_queue_regval(acq, REG_MEM_START, READ_START_ADDR);
481 case STATE_READ_FINISH:
482 lwla_queue_regval(acq, REG_CLK_BOOST, 0);
484 case STATE_STATUS_REQUEST:
485 acq->xfer_buf_out[0] = LWLA_WORD(CMD_READ_LREGS);
486 acq->xfer_buf_out[1] = LWLA_WORD(READ_LREGS_START);
487 acq->xfer_buf_out[2] = LWLA_WORD(READ_LREGS_COUNT);
488 acq->xfer_out->length = 3 * sizeof(acq->xfer_buf_out[0]);
490 case STATE_LENGTH_REQUEST:
491 lwla_queue_regval(acq, REG_MEM_FILL, 0);
493 case STATE_READ_REQUEST:
494 /* Limit reads to 8 device words (36 bytes) at a time if the
495 * device firmware has the short transfer quirk. */
496 chunk_len = (devc->short_transfer_quirk) ? 8 : READ_CHUNK_LEN;
497 /* Always read a multiple of 8 device words. */
498 remaining = (acq->mem_addr_stop - acq->mem_addr_next + 7) / 8 * 8;
499 count = MIN(chunk_len, remaining);
501 acq->xfer_buf_out[0] = LWLA_WORD(CMD_READ_MEM36);
502 acq->xfer_buf_out[1] = LWLA_WORD_0(acq->mem_addr_next);
503 acq->xfer_buf_out[2] = LWLA_WORD_1(acq->mem_addr_next);
504 acq->xfer_buf_out[3] = LWLA_WORD_0(count);
505 acq->xfer_buf_out[4] = LWLA_WORD_1(count);
506 acq->xfer_out->length = 5 * sizeof(acq->xfer_buf_out[0]);
508 acq->mem_addr_next += count;
511 sr_err("BUG: unhandled request state %d.", devc->state);
518 static int handle_response(const struct sr_dev_inst *sdi)
520 struct dev_context *devc;
521 struct acquisition_state *acq;
525 acq = devc->acquisition;
527 switch (devc->state) {
528 case STATE_STATUS_REQUEST:
529 if (acq->xfer_in->actual_length != READ_LREGS_COUNT * 8) {
530 sr_err("Received size %d doesn't match expected size %d.",
531 acq->xfer_in->actual_length, READ_LREGS_COUNT * 8);
534 acq->mem_addr_fill = bulk_long_get(acq, LREG_MEM_FILL) & 0xFFFFFFFF;
535 acq->duration_now = bulk_long_get(acq, LREG_DURATION);
536 /* Shift left by one so the bit positions match the LWLA1016. */
537 acq->status = (bulk_long_get(acq, LREG_STATUS) & 0x3F) << 1;
539 * It seems that the 125 MS/s mode is implemented simply by
540 * running the FPGA logic at a 25% higher clock rate. As a
541 * result, the millisecond counter for the capture duration
542 * is also off by 25%, and thus needs to be corrected here.
544 if (acq->clock_boost)
545 acq->duration_now = acq->duration_now * 4 / 5;
547 case STATE_LENGTH_REQUEST:
548 acq->mem_addr_next = READ_START_ADDR;
549 acq->mem_addr_stop = acq->reg_sequence[0].val;
551 case STATE_READ_REQUEST:
552 /* Expect a multiple of 8 36-bit words packed into 9 32-bit
554 expect_len = (acq->mem_addr_next - acq->mem_addr_done
555 + acq->in_index + 7) / 8 * 9 * sizeof(acq->xfer_buf_in[0]);
557 if (acq->xfer_in->actual_length != expect_len) {
558 sr_err("Received size %d does not match expected size %d.",
559 acq->xfer_in->actual_length, expect_len);
560 devc->transfer_error = TRUE;
566 sr_err("BUG: unhandled response state %d.", devc->state);
573 /** Model descriptor for the LWLA1034.
575 SR_PRIV const struct model_info lwla1034_info = {
577 .num_channels = NUM_CHANNELS,
581 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
582 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
583 SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
584 SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
585 SR_CONF_EXTERNAL_CLOCK | SR_CONF_GET | SR_CONF_SET,
586 SR_CONF_CLOCK_EDGE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
587 SR_CONF_TRIGGER_SOURCE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
588 SR_CONF_TRIGGER_SLOPE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
590 .num_samplerates = 20,
592 SR_MHZ(125), SR_MHZ(100),
593 SR_MHZ(50), SR_MHZ(20), SR_MHZ(10),
594 SR_MHZ(5), SR_MHZ(2), SR_MHZ(1),
595 SR_KHZ(500), SR_KHZ(200), SR_KHZ(100),
596 SR_KHZ(50), SR_KHZ(20), SR_KHZ(10),
597 SR_KHZ(5), SR_KHZ(2), SR_KHZ(1),
598 SR_HZ(500), SR_HZ(200), SR_HZ(100),
601 .apply_fpga_config = &apply_fpga_config,
602 .device_init_check = &device_init_check,
603 .setup_acquisition = &setup_acquisition,
605 .prepare_request = &prepare_request,
606 .handle_response = &handle_response,