src/hardware/sysclk-lwla/lwla1016.c

   1 /*
   2  * This file is part of the libsigrok project.
   3  *
   4  * Copyright (C) 2015 Daniel Elstner <daniel.kitta@gmail.com>
   5  *
   6  * This program is free software: you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation, either version 3 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <config.h>
  21 #include "lwla.h"
  22 #include "protocol.h"
  23
  24 /* Number of logic channels. */
  25 #define NUM_CHANNELS    16
  26
  27 /* Unit size for the sigrok logic datafeed. */
  28 #define UNIT_SIZE       ((NUM_CHANNELS + 7) / 8)
  29
  30 /* Size of the acquisition buffer in device memory units. */
  31 #define MEMORY_DEPTH    (256 * 1024)    /* 256k x 32 bit */
  32
  33 /* Capture memory read start address. */
  34 #define READ_START_ADDR 2
  35
  36 /* Number of device memory units (32 bit) to read at a time. */
  37 #define READ_CHUNK_LEN  250
  38
  39 /** LWLA1016 register addresses. */
  40 enum reg_addr {
  41         REG_CHAN_MASK   = 0x1000, /* bit mask of enabled channels */
  42
  43         REG_DURATION    = 0x1010, /* capture duration in ms */
  44
  45         REG_MEM_WR_PTR  = 0x1070,
  46         REG_MEM_RD_PTR  = 0x1074,
  47         REG_MEM_DATA    = 0x1078,
  48         REG_MEM_CTRL    = 0x107C,
  49
  50         REG_CAP_COUNT   = 0x10B0,
  51
  52         REG_TEST_ID     = 0x10B4, /* read */
  53         REG_TRG_SEL     = 0x10B4, /* write */
  54
  55         REG_CAP_CTRL    = 0x10B8,
  56
  57         REG_CAP_TOTAL   = 0x10BC, /* read */
  58         REG_DIV_COUNT   = 0x10BC, /* write */
  59 };
  60
  61 /** Flag bits for REG_MEM_CTRL. */
  62 enum mem_ctrl_flag {
  63         MEM_CTRL_RESET  = 1 << 0,
  64         MEM_CTRL_WRITE  = 1 << 1,
  65 };
  66
  67 /** Flag bits for REG_CAP_CTRL. */
  68 enum cap_ctrl_flag {
  69         CAP_CTRL_FIFO32_FULL    = 1 << 0, /* "fifo32_ful" bit */
  70         CAP_CTRL_FIFO64_FULL    = 1 << 1, /* "fifo64_ful" bit */
  71         CAP_CTRL_TRG_EN         = 1 << 2, /* "trg_en" bit */
  72         CAP_CTRL_CLR_TIMEBASE   = 1 << 3, /* "do_clr_timebase" bit */
  73         CAP_CTRL_FIFO_EMPTY     = 1 << 4, /* "fifo_empty" bit */
  74         CAP_CTRL_SAMPLE_EN      = 1 << 5, /* "sample_en" bit */
  75         CAP_CTRL_CNTR_NOT_ENDR  = 1 << 6, /* "cntr_not_endr" bit */
  76 };
  77
  78 /* Available FPGA configurations. */
  79 enum fpga_config {
  80         FPGA_100 = 0,   /* 100 MS/s, no compression */
  81         FPGA_100_TS,    /* 100 MS/s, timing-state mode */
  82 };
  83
  84 /* FPGA bitstream resource filenames. */
  85 static const char bitstream_map[][32] = {
  86         [FPGA_100]      = "sysclk-lwla1016-100.rbf",
  87         [FPGA_100_TS]   = "sysclk-lwla1016-100-ts.rbf",
  88 };
  89
  90 /* Demangle incoming sample data from the transfer buffer. */
  91 static void read_response(struct acquisition_state *acq)
  92 {
  93         uint32_t *in_p, *out_p;
  94         unsigned int words_left, num_words;
  95         unsigned int max_samples, run_samples;
  96         unsigned int i;
  97
  98         words_left = MIN(acq->mem_addr_next, acq->mem_addr_stop)
  99                         - acq->mem_addr_done;
 100         /* Calculate number of samples to write into packet. */
 101         max_samples = MIN(acq->samples_max - acq->samples_done,
 102                           PACKET_SIZE / UNIT_SIZE - acq->out_index);
 103         run_samples = MIN(max_samples, 2 * words_left);
 104
 105         /* Round up in case the samples limit is an odd number. */
 106         num_words = (run_samples + 1) / 2;
 107         /*
 108          * Without RLE the output index will always be a multiple of two
 109          * samples (at least before reaching the samples limit), thus 32-bit
 110          * alignment is guaranteed.
 111          */
 112         out_p = (uint32_t *)&acq->out_packet[acq->out_index * UNIT_SIZE];
 113         in_p = &acq->xfer_buf_in[acq->in_index];
 114         /*
 115          * Transfer two samples at a time, taking care to swap the 16-bit
 116          * halves of each input word but keeping the samples themselves in
 117          * the original Little Endian order.
 118          */
 119         for (i = 0; i < num_words; i++)
 120                 out_p[i] = LROTATE(in_p[i], 16);
 121
 122         acq->in_index += num_words;
 123         acq->mem_addr_done += num_words;
 124         acq->out_index += run_samples;
 125         acq->samples_done += run_samples;
 126 }
 127
 128 /* Demangle and decompress incoming sample data from the transfer buffer. */
 129 static void read_response_rle(struct acquisition_state *acq)
 130 {
 131         uint32_t *in_p;
 132         uint16_t *out_p;
 133         unsigned int words_left, max_samples, run_samples, wi, ri;
 134         uint32_t word;
 135         uint16_t sample;
 136
 137         words_left = MIN(acq->mem_addr_next, acq->mem_addr_stop)
 138                         - acq->mem_addr_done;
 139         in_p = &acq->xfer_buf_in[acq->in_index];
 140
 141         for (wi = 0;; wi++) {
 142                 /* Calculate number of samples to write into packet. */
 143                 max_samples = MIN(acq->samples_max - acq->samples_done,
 144                                   PACKET_SIZE / UNIT_SIZE - acq->out_index);
 145                 run_samples = MIN(max_samples, acq->run_len);
 146
 147                 /* Expand run-length samples into session packet. */
 148                 sample = GUINT16_TO_LE(acq->sample);
 149                 out_p = &((uint16_t *)acq->out_packet)[acq->out_index];
 150
 151                 for (ri = 0; ri < run_samples; ri++)
 152                         out_p[ri] = sample;
 153
 154                 acq->run_len -= run_samples;
 155                 acq->out_index += run_samples;
 156                 acq->samples_done += run_samples;
 157
 158                 if (run_samples == max_samples)
 159                         break; /* Packet full or sample limit reached. */
 160                 if (wi >= words_left)
 161                         break; /* Done with current transfer. */
 162
 163                 word = GUINT32_FROM_LE(in_p[wi]);
 164                 acq->sample = word >> 16;
 165                 acq->run_len = (word & 0xFFFF) + 1;
 166         }
 167
 168         acq->in_index += wi;
 169         acq->mem_addr_done += wi;
 170 }
 171
 172 /* Check whether we can receive responses of more than 64 bytes.
 173  * The FX2 firmware of the LWLA1016 has a bug in the reset logic which
 174  * sometimes causes the response endpoint to be limited to transfers of
 175  * 64 bytes at a time, instead of the expected 2*512 bytes. The problem
 176  * can be worked around by never requesting more than 64 bytes.
 177  * This quirk manifests itself only under certain conditions, and some
 178  * users seem to see it more frequently than others. Detect it here in
 179  * order to avoid paying the penalty unnecessarily.
 180  */
 181 static int test_read_memory(const struct sr_dev_inst *sdi,
 182                             unsigned int start, unsigned int count)
 183 {
 184         struct dev_context *devc;
 185         struct sr_usb_dev_inst *usb;
 186         unsigned int i;
 187         int xfer_len, ret;
 188         uint16_t command[5];
 189         unsigned char reply[512];
 190
 191         devc = sdi->priv;
 192         usb = sdi->conn;
 193
 194         command[0] = LWLA_WORD(CMD_READ_MEM32);
 195         command[1] = LWLA_WORD_0(start);
 196         command[2] = LWLA_WORD_1(start);
 197         command[3] = LWLA_WORD_0(count);
 198         command[4] = LWLA_WORD_1(count);
 199
 200         ret = lwla_send_command(usb, ARRAY_AND_SIZE(command));
 201         if (ret != SR_OK)
 202                 return ret;
 203
 204         ret = lwla_receive_reply(usb, reply, sizeof(reply), &xfer_len);
 205         if (ret != SR_OK)
 206                 return ret;
 207
 208         devc->short_transfer_quirk = (xfer_len == 64);
 209
 210         for (i = xfer_len; i < 4 * count && xfer_len == 64; i += xfer_len) {
 211                 ret = lwla_receive_reply(usb, reply, sizeof(reply), &xfer_len);
 212                 if (ret != SR_OK)
 213                         return ret;
 214         }
 215         if (i != 4 * count) {
 216                 sr_err("Invalid read response of unexpected length %d.",
 217                        xfer_len);
 218                 return SR_ERR;
 219         }
 220
 221         return SR_OK;
 222 }
 223
 224 /* Select and transfer FPGA bitstream for the current configuration. */
 225 static int apply_fpga_config(const struct sr_dev_inst *sdi)
 226 {
 227         struct dev_context *devc;
 228         struct drv_context *drvc;
 229         int config, ret;
 230
 231         devc = sdi->priv;
 232         drvc = sdi->driver->context;
 233
 234         if (sdi->status == SR_ST_INACTIVE)
 235                 return SR_OK; /* The LWLA1016 has no off state. */
 236
 237         config = (devc->cfg_rle) ? FPGA_100_TS : FPGA_100;
 238
 239         if (config == devc->active_fpga_config)
 240                 return SR_OK; /* No change. */
 241
 242         ret = lwla_send_bitstream(drvc->sr_ctx, sdi->conn,
 243                                   bitstream_map[config]);
 244         devc->active_fpga_config = (ret == SR_OK) ? config : FPGA_NOCONF;
 245
 246         return ret;
 247 }
 248
 249 /* Perform initialization self test. */
 250 static int device_init_check(const struct sr_dev_inst *sdi)
 251 {
 252         static const struct regval mem_reset[] = {
 253                 {REG_MEM_CTRL, MEM_CTRL_RESET},
 254                 {REG_MEM_CTRL, 0},
 255         };
 256         uint32_t value;
 257         int ret;
 258         const unsigned int test_count = 24;
 259
 260         lwla_read_reg(sdi->conn, REG_TEST_ID, &value);
 261
 262         /* Ignore the value returned by the first read. */
 263         ret = lwla_read_reg(sdi->conn, REG_TEST_ID, &value);
 264         if (ret != SR_OK)
 265                 return ret;
 266
 267         if (value != 0x12345678) {
 268                 sr_err("Received invalid test word 0x%08X.", value);
 269                 return SR_ERR;
 270         }
 271
 272         ret = lwla_write_regs(sdi->conn, ARRAY_AND_SIZE(mem_reset));
 273         if (ret != SR_OK)
 274                 return ret;
 275
 276         ret = test_read_memory(sdi, 0, test_count);
 277         if (ret != SR_OK)
 278                 return ret;
 279
 280         /*
 281          * Issue another read request or the device will stall, for whatever
 282          * reason. This happens both with and without the short transfer quirk.
 283          */
 284         return test_read_memory(sdi, test_count, test_count);
 285 }
 286
 287 static int setup_acquisition(const struct sr_dev_inst *sdi)
 288 {
 289         static const struct regval capture_init[] = {
 290                 {REG_CAP_CTRL,  0},
 291                 {REG_DURATION,  0},
 292                 {REG_MEM_CTRL,  MEM_CTRL_RESET},
 293                 {REG_MEM_CTRL,  0},
 294                 {REG_MEM_CTRL,  MEM_CTRL_WRITE},
 295                 {REG_CAP_CTRL,  CAP_CTRL_FIFO32_FULL | CAP_CTRL_FIFO64_FULL},
 296                 {REG_CAP_CTRL,  CAP_CTRL_FIFO_EMPTY},
 297                 {REG_CAP_CTRL,  0},
 298                 {REG_CAP_COUNT, MEMORY_DEPTH - 5},
 299         };
 300         struct dev_context *devc;
 301         struct sr_usb_dev_inst *usb;
 302         uint32_t divider_count, trigger_setup;
 303         int ret;
 304
 305         devc = sdi->priv;
 306         usb = sdi->conn;
 307
 308         ret = lwla_write_reg(usb, REG_CHAN_MASK, devc->channel_mask);
 309         if (ret != SR_OK)
 310                 return ret;
 311
 312         if (devc->samplerate > 0 && devc->samplerate < SR_MHZ(100))
 313                 divider_count = SR_MHZ(100) / devc->samplerate - 1;
 314         else
 315                 divider_count = 0;
 316
 317         ret = lwla_write_reg(usb, REG_DIV_COUNT, divider_count);
 318         if (ret != SR_OK)
 319                 return ret;
 320
 321         ret = lwla_write_regs(usb, ARRAY_AND_SIZE(capture_init));
 322         if (ret != SR_OK)
 323                 return ret;
 324
 325         trigger_setup = ((devc->trigger_edge_mask & 0xFFFF) << 16)
 326                         | (devc->trigger_values & 0xFFFF);
 327
 328         return lwla_write_reg(usb, REG_TRG_SEL, trigger_setup);
 329 }
 330
 331 static int prepare_request(const struct sr_dev_inst *sdi)
 332 {
 333         struct dev_context *devc;
 334         struct acquisition_state *acq;
 335         unsigned int chunk_len, count;
 336
 337         devc = sdi->priv;
 338         acq = devc->acquisition;
 339
 340         acq->xfer_out->length = 0;
 341         acq->reg_seq_pos = 0;
 342         acq->reg_seq_len = 0;
 343
 344         switch (devc->state) {
 345         case STATE_START_CAPTURE:
 346                 lwla_queue_regval(acq, REG_CAP_CTRL, CAP_CTRL_TRG_EN
 347                                 | ((devc->trigger_mask & 0xFFFF) << 16));
 348                 break;
 349         case STATE_STOP_CAPTURE:
 350                 lwla_queue_regval(acq, REG_CAP_CTRL, 0);
 351                 lwla_queue_regval(acq, REG_DIV_COUNT, 0);
 352                 break;
 353         case STATE_READ_PREPARE:
 354                 lwla_queue_regval(acq, REG_MEM_CTRL, 0);
 355                 break;
 356         case STATE_READ_FINISH:
 357                 lwla_queue_regval(acq, REG_MEM_CTRL, MEM_CTRL_RESET);
 358                 lwla_queue_regval(acq, REG_MEM_CTRL, 0);
 359                 break;
 360         case STATE_STATUS_REQUEST:
 361                 lwla_queue_regval(acq, REG_CAP_CTRL, 0);
 362                 lwla_queue_regval(acq, REG_MEM_WR_PTR, 0);
 363                 lwla_queue_regval(acq, REG_DURATION, 0);
 364                 break;
 365         case STATE_LENGTH_REQUEST:
 366                 lwla_queue_regval(acq, REG_CAP_COUNT, 0);
 367                 break;
 368         case STATE_READ_REQUEST:
 369                 /* Limit reads to 16 device words (64 bytes) at a time if the
 370                  * device firmware has the short transfer quirk. */
 371                 chunk_len = (devc->short_transfer_quirk) ? 16 : READ_CHUNK_LEN;
 372                 count = MIN(chunk_len, acq->mem_addr_stop - acq->mem_addr_next);
 373
 374                 acq->xfer_buf_out[0] = LWLA_WORD(CMD_READ_MEM32);
 375                 acq->xfer_buf_out[1] = LWLA_WORD_0(acq->mem_addr_next);
 376                 acq->xfer_buf_out[2] = LWLA_WORD_1(acq->mem_addr_next);
 377                 acq->xfer_buf_out[3] = LWLA_WORD_0(count);
 378                 acq->xfer_buf_out[4] = LWLA_WORD_1(count);
 379                 acq->xfer_out->length = 5 * sizeof(acq->xfer_buf_out[0]);
 380
 381                 acq->mem_addr_next += count;
 382                 break;
 383         default:
 384                 sr_err("BUG: unhandled request state %d.", devc->state);
 385                 return SR_ERR_BUG;
 386         }
 387
 388         return SR_OK;
 389 }
 390
 391 static int handle_response(const struct sr_dev_inst *sdi)
 392 {
 393         struct dev_context *devc;
 394         struct acquisition_state *acq;
 395         int expect_len;
 396
 397         devc = sdi->priv;
 398         acq = devc->acquisition;
 399
 400         switch (devc->state) {
 401         case STATE_STATUS_REQUEST:
 402                 acq->status = acq->reg_sequence[0].val & 0x7F;
 403                 acq->mem_addr_fill = acq->reg_sequence[1].val;
 404                 acq->duration_now  = acq->reg_sequence[2].val;
 405                 break;
 406         case STATE_LENGTH_REQUEST:
 407                 acq->mem_addr_next = READ_START_ADDR;
 408                 acq->mem_addr_stop = acq->reg_sequence[0].val + READ_START_ADDR - 1;
 409                 break;
 410         case STATE_READ_REQUEST:
 411                 expect_len = (acq->mem_addr_next - acq->mem_addr_done
 412                                 + acq->in_index) * sizeof(acq->xfer_buf_in[0]);
 413                 if (acq->xfer_in->actual_length != expect_len) {
 414                         sr_err("Received size %d does not match expected size %d.",
 415                                acq->xfer_in->actual_length, expect_len);
 416                         devc->transfer_error = TRUE;
 417                         return SR_ERR;
 418                 }
 419                 if (acq->rle_enabled)
 420                         read_response_rle(acq);
 421                 else
 422                         read_response(acq);
 423                 break;
 424         default:
 425                 sr_err("BUG: unhandled response state %d.", devc->state);
 426                 return SR_ERR_BUG;
 427         }
 428
 429         return SR_OK;
 430 }
 431
 432 /* Model descriptor for the LWLA1016. */
 433 SR_PRIV const struct model_info lwla1016_info = {
 434         .name = "LWLA1016",
 435         .num_channels = NUM_CHANNELS,
 436
 437         .num_devopts = 5,
 438         .devopts = {
 439                 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
 440                 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
 441                 SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
 442                 SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
 443                 SR_CONF_RLE | SR_CONF_GET | SR_CONF_SET,
 444         },
 445         .num_samplerates = 19,
 446         .samplerates = {
 447                 SR_MHZ(100),
 448                 SR_MHZ(50),  SR_MHZ(20),  SR_MHZ(10),
 449                 SR_MHZ(5),   SR_MHZ(2),   SR_MHZ(1),
 450                 SR_KHZ(500), SR_KHZ(200), SR_KHZ(100),
 451                 SR_KHZ(50),  SR_KHZ(20),  SR_KHZ(10),
 452                 SR_KHZ(5),   SR_KHZ(2),   SR_KHZ(1),
 453                 SR_HZ(500),  SR_HZ(200),  SR_HZ(100),
 454         },
 455
 456         .apply_fpga_config = &apply_fpga_config,
 457         .device_init_check = &device_init_check,
 458         .setup_acquisition = &setup_acquisition,
 459
 460         .prepare_request = &prepare_request,
 461         .handle_response = &handle_response,
 462 };