2 * This file is part of the libsigrok project.
4 * Copyright (C) 2020 Florian Schmidt <schmidt_florian@gmx.de>
5 * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se>
6 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
7 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 3 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
25 #include <libsigrok/libsigrok.h>
28 #include "libsigrok-internal.h"
31 /* USB PID dependent MCU firmware. Model dependent FPGA bitstream. */
32 #define MCU_FWFILE_FMT "kingst-la-%04x.fw"
33 #define FPGA_FWFILE_FMT "kingst-%s-fpga.bitstream"
36 * List of supported devices and their features. See @ref kingst_model
37 * for the fields' type and meaning. Table is sorted by EEPROM magic.
40 * - Below LA1016 properties were guessed, need verification.
41 * - Add LA5016 and LA5032 devices when their EEPROM magic is known.
42 * - Does LA1010 fit the driver implementation? Samplerates vary with
43 * channel counts, lack of local sample memory. Most probably not.
45 static const struct kingst_model models[] = {
46 { 2, "LA2016", "la2016", SR_MHZ(200), 16, 1, },
47 { 3, "LA1016", "la1016", SR_MHZ(100), 16, 1, },
48 { 8, "LA2016", "la2016a1", SR_MHZ(200), 16, 1, },
49 { 9, "LA1016", "la1016a1", SR_MHZ(100), 16, 1, },
52 /* USB vendor class control requests, executed by the Cypress FX2 MCU. */
53 #define CMD_FPGA_ENABLE 0x10
54 #define CMD_FPGA_SPI 0x20 /* R/W access to FPGA registers via SPI. */
55 #define CMD_BULK_START 0x30 /* Start sample data download via USB EP6 IN. */
56 #define CMD_BULK_RESET 0x38 /* Flush FIFO of FX2 USB EP6 IN. */
57 #define CMD_FPGA_INIT 0x50 /* Used before and after FPGA bitstream upload. */
58 #define CMD_KAUTH 0x60 /* Communicate to auth IC (U10). Not used. */
59 #define CMD_EEPROM 0xa2 /* R/W access to EEPROM content. */
62 * FPGA register addresses (base addresses when registers span multiple
63 * bytes, in that case data is kept in little endian format). Passed to
64 * CMD_FPGA_SPI requests. The FX2 MCU transparently handles the detail
65 * of SPI transfers encoding the read (1) or write (0) direction in the
66 * MSB of the address field. There are some 60 byte-wide FPGA registers.
68 * Unfortunately the FPGA registers change their meaning between the
69 * read and write directions of access, or exclusively provide one of
70 * these directions and not the other. This is an arbitrary vendor's
71 * choice, there is nothing which the sigrok driver could do about it.
72 * Values written to registers typically cannot get read back, neither
73 * verified after writing a configuration, nor queried upon startup for
74 * automatic detection of the current configuration. Neither appear to
75 * be there echo registers for presence and communication checks, nor
76 * version identifying registers, as far as we know.
78 #define REG_RUN 0x00 /* Read capture status, write start capture. */
79 #define REG_PWM_EN 0x02 /* User PWM channels on/off. */
80 #define REG_CAPT_MODE 0x03 /* Write 0x00 capture to SDRAM, 0x01 streaming. */
81 #define REG_BULK 0x08 /* Write start addr, byte count to download samples. */
82 #define REG_SAMPLING 0x10 /* Write capture config, read capture SDRAM location. */
83 #define REG_TRIGGER 0x20 /* Write level and edge trigger config. */
84 #define REG_UNKNOWN_30 0x30
85 #define REG_THRESHOLD 0x68 /* Write PWM config to setup input threshold DAC. */
86 #define REG_PWM1 0x70 /* Write config for user PWM1. */
87 #define REG_PWM2 0x78 /* Write config for user PWM2. */
89 /* Bit patterns to write to REG_RUN, setup run mode. */
90 #define RUNMODE_HALT 0x00
91 #define RUNMODE_RUN 0x03
93 /* Bit patterns when reading from REG_RUN, get run state. */
94 #define RUNSTATE_IDLE_BIT (1UL << 0)
95 #define RUNSTATE_DRAM_BIT (1UL << 1)
96 #define RUNSTATE_TRGD_BIT (1UL << 2)
97 #define RUNSTATE_POST_BIT (1UL << 3)
100 * Properties related to the layout of capture data downloads.
102 * TODO Check the layout of 32 channel models' capture data. Could it be
103 * 3x (u32 + u8) instead of 5x (u16 + u8) perhaps? Same 16 bytes chunk
104 * but fewer packets per chunk and thus per transfer? Which questions
105 * the NUM_PACKETS_IN_CHUNK literal, maybe needs to be a runtime value?
107 #define NUM_PACKETS_IN_CHUNK 5
108 #define TRANSFER_PACKET_LENGTH 16
110 static int ctrl_in(const struct sr_dev_inst *sdi,
111 uint8_t bRequest, uint16_t wValue, uint16_t wIndex,
112 void *data, uint16_t wLength)
114 struct sr_usb_dev_inst *usb;
119 ret = libusb_control_transfer(usb->devhdl,
120 LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_IN,
121 bRequest, wValue, wIndex, data, wLength,
123 if (ret != wLength) {
124 sr_dbg("USB ctrl in: %d bytes, req %d val %#x idx %d: %s.",
125 wLength, bRequest, wValue, wIndex,
126 libusb_error_name(ret));
127 sr_err("Cannot read %d bytes from USB: %s.",
128 wLength, libusb_error_name(ret));
135 static int ctrl_out(const struct sr_dev_inst *sdi,
136 uint8_t bRequest, uint16_t wValue, uint16_t wIndex,
137 void *data, uint16_t wLength)
139 struct sr_usb_dev_inst *usb;
144 ret = libusb_control_transfer(usb->devhdl,
145 LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT,
146 bRequest, wValue, wIndex, data, wLength,
148 if (ret != wLength) {
149 sr_dbg("USB ctrl out: %d bytes, req %d val %#x idx %d: %s.",
150 wLength, bRequest, wValue, wIndex,
151 libusb_error_name(ret));
152 sr_err("Cannot write %d bytes to USB: %s.",
153 wLength, libusb_error_name(ret));
161 * Check the necessity for FPGA bitstream upload, because another upload
162 * would take some 600ms which is undesirable after program startup. Try
163 * to access some FPGA registers and check the values' plausibility. The
164 * check should fail on the safe side, request another upload when in
165 * doubt. A positive response (the request to continue operation with the
166 * currently active bitstream) should be conservative. Accessing multiple
167 * registers is considered cheap compared to the cost of bitstream upload.
169 * It helps though that both the vendor software and the sigrok driver
170 * use the same bundle of MCU firmware and FPGA bitstream for any of the
171 * supported models. We don't expect to successfully communicate to the
172 * device yet disagree on its protocol. Ideally we would access version
173 * identifying registers for improved robustness, but are not aware of
174 * any. A bitstream reload can always be forced by a power cycle.
176 static int check_fpga_bitstream(const struct sr_dev_inst *sdi)
179 uint8_t buff[REG_PWM_EN - REG_RUN]; /* Larger of REG_RUN, REG_PWM_EN. */
184 const uint8_t *rdptr;
186 sr_dbg("Checking operation of the FPGA bitstream.");
189 ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &init_rsp, sizeof(init_rsp));
190 if (ret != SR_OK || init_rsp != 0) {
191 sr_dbg("FPGA init query failed, or unexpected response.");
195 read_len = sizeof(run_state);
196 ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, buff, read_len);
198 sr_dbg("FPGA register access failed (run state).");
202 run_state = read_u16le_inc(&rdptr);
203 sr_spew("FPGA register: run state 0x%04x.", run_state);
204 if (run_state && (run_state & 0x3) != 0x1) {
205 sr_dbg("Unexpected FPGA register content (run state).");
208 if (run_state && (run_state & ~0xf) != 0x85e0) {
209 sr_dbg("Unexpected FPGA register content (run state).");
213 read_len = sizeof(pwm_en);
214 ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, buff, read_len);
216 sr_dbg("FPGA register access failed (PWM enable).");
220 pwm_en = read_u8_inc(&rdptr);
221 sr_spew("FPGA register: PWM enable 0x%02x.", pwm_en);
222 if ((pwm_en & 0x3) != 0x0) {
223 sr_dbg("Unexpected FPGA register content (PWM enable).");
227 sr_info("Could re-use current FPGA bitstream. No upload required.");
231 static int upload_fpga_bitstream(const struct sr_dev_inst *sdi,
232 const char *bitstream_fname)
234 struct drv_context *drvc;
235 struct sr_usb_dev_inst *usb;
236 struct sr_resource bitstream;
237 uint32_t bitstream_size;
238 uint8_t buffer[sizeof(uint32_t)];
244 unsigned int zero_pad_to;
246 drvc = sdi->driver->context;
249 sr_info("Uploading FPGA bitstream '%s'.", bitstream_fname);
251 ret = sr_resource_open(drvc->sr_ctx, &bitstream,
252 SR_RESOURCE_FIRMWARE, bitstream_fname);
254 sr_err("Cannot find FPGA bitstream %s.", bitstream_fname);
258 bitstream_size = (uint32_t)bitstream.size;
260 write_u32le_inc(&wrptr, bitstream_size);
261 ret = ctrl_out(sdi, CMD_FPGA_INIT, 0x00, 0, buffer, wrptr - buffer);
263 sr_err("Cannot initiate FPGA bitstream upload.");
264 sr_resource_close(drvc->sr_ctx, &bitstream);
267 zero_pad_to = bitstream_size;
268 zero_pad_to += LA2016_EP2_PADDING - 1;
269 zero_pad_to /= LA2016_EP2_PADDING;
270 zero_pad_to *= LA2016_EP2_PADDING;
274 if (pos < bitstream.size) {
275 len = (int)sr_resource_read(drvc->sr_ctx, &bitstream,
276 block, sizeof(block));
278 sr_err("Cannot read FPGA bitstream.");
279 sr_resource_close(drvc->sr_ctx, &bitstream);
283 /* Zero-pad until 'zero_pad_to'. */
284 len = zero_pad_to - pos;
285 if ((unsigned)len > sizeof(block))
287 memset(&block, 0, len);
292 ret = libusb_bulk_transfer(usb->devhdl, USB_EP_FPGA_BITSTREAM,
293 &block[0], len, &act_len, DEFAULT_TIMEOUT_MS);
295 sr_dbg("Cannot write FPGA bitstream, block %#x len %d: %s.",
296 pos, (int)len, libusb_error_name(ret));
300 if (act_len != len) {
301 sr_dbg("Short write for FPGA bitstream, block %#x len %d: got %d.",
302 pos, (int)len, act_len);
308 sr_resource_close(drvc->sr_ctx, &bitstream);
311 sr_info("FPGA bitstream upload (%" PRIu64 " bytes) done.",
317 static int enable_fpga_bitstream(const struct sr_dev_inst *sdi)
322 ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &resp, sizeof(resp));
324 sr_err("Cannot read response after FPGA bitstream upload.");
328 sr_err("Unexpected FPGA bitstream upload response, got 0x%02x, want 0.",
334 ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x01, 0, NULL, 0);
336 sr_err("Cannot enable FPGA after bitstream upload.");
344 static int set_threshold_voltage(const struct sr_dev_inst *sdi, float voltage)
347 uint16_t duty_R79, duty_R56;
348 uint8_t buf[REG_PWM1 - REG_THRESHOLD]; /* Width of REG_THRESHOLD. */
351 /* Clamp threshold setting to valid range for LA2016. */
352 if (voltage > LA2016_THR_VOLTAGE_MAX) {
353 voltage = LA2016_THR_VOLTAGE_MAX;
354 } else if (voltage < -LA2016_THR_VOLTAGE_MAX) {
355 voltage = -LA2016_THR_VOLTAGE_MAX;
359 * Two PWM output channels feed one DAC which generates a bias
360 * voltage, which offsets the input probe's voltage level, and
361 * in combination with the FPGA pins' fixed threshold result in
362 * a programmable input threshold from the user's perspective.
363 * The PWM outputs can be seen on R79 and R56 respectively, the
364 * frequency is 100kHz and the duty cycle varies. The R79 PWM
365 * uses three discrete settings. The R56 PWM varies with desired
366 * thresholds and depends on the R79 PWM configuration. See the
367 * schematics comments which discuss the formulae.
369 if (voltage >= 2.9) {
370 duty_R79 = 0; /* PWM off (0V). */
371 duty_R56 = (uint16_t)(302 * voltage - 363);
372 } else if (voltage > -0.4) {
373 duty_R79 = 0x00f2; /* 25% duty cycle. */
374 duty_R56 = (uint16_t)(302 * voltage + 121);
376 duty_R79 = 0x02d7; /* 72% duty cycle. */
377 duty_R56 = (uint16_t)(302 * voltage + 1090);
380 /* Clamp duty register values to sensible limits. */
383 } else if (duty_R56 > 1100) {
387 sr_dbg("Set threshold voltage %.2fV.", voltage);
388 sr_dbg("Duty cycle values: R56 0x%04x, R79 0x%04x.", duty_R56, duty_R79);
391 write_u16le_inc(&wrptr, duty_R56);
392 write_u16le_inc(&wrptr, duty_R79);
394 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_THRESHOLD, 0, buf, wrptr - buf);
396 sr_err("Cannot set threshold voltage %.2fV.", voltage);
404 * Communicates a channel's configuration to the device after the
405 * parameters may have changed. Configuration of one channel may
406 * interfere with other channels since they share FPGA registers.
408 static int set_pwm_config(const struct sr_dev_inst *sdi, size_t idx)
410 static uint8_t reg_bases[] = { REG_PWM1, REG_PWM2, };
412 struct dev_context *devc;
413 struct pwm_setting *params;
417 uint32_t period, duty;
420 uint8_t enable_all, enable_cfg, reg_val;
421 uint8_t buf[REG_PWM2 - REG_PWM1]; /* Width of one REG_PWMx. */
425 if (idx >= ARRAY_SIZE(devc->pwm_setting))
427 params = &devc->pwm_setting[idx];
428 if (idx >= ARRAY_SIZE(reg_bases))
430 reg_base = reg_bases[idx];
433 * Map application's specs to hardware register values. Do math
434 * in floating point initially, but convert to u32 eventually.
436 sr_dbg("PWM config, app spec, ch %zu, en %d, freq %.1f, duty %.1f.",
437 idx, params->enabled ? 1 : 0, params->freq, params->duty);
439 val_f /= params->freq;
443 val_f *= params->duty;
448 sr_dbg("PWM config, reg 0x%04x, freq %u, duty %u.",
449 (unsigned)reg_base, (unsigned)period, (unsigned)duty);
451 /* Get the "enabled" state of all supported PWM channels. */
453 for (ch = 0; ch < ARRAY_SIZE(devc->pwm_setting); ch++) {
454 if (!devc->pwm_setting[ch].enabled)
456 enable_all |= 1U << ch;
458 enable_cfg = 1U << idx;
459 sr_spew("PWM config, enable all 0x%02hhx, cfg 0x%02hhx.",
460 enable_all, enable_cfg);
463 * Disable the to-get-configured channel before its parameters
464 * will change. Or disable and exit when the channel is supposed
467 sr_spew("PWM config, disabling before param change.");
468 reg_val = enable_all & ~enable_cfg;
469 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0,
470 ®_val, sizeof(reg_val));
472 sr_err("Cannot adjust PWM enabled state.");
475 if (!params->enabled)
478 /* Write register values to device. */
479 sr_spew("PWM config, sending new parameters.");
481 write_u32le_inc(&wrptr, period);
482 write_u32le_inc(&wrptr, duty);
483 ret = ctrl_out(sdi, CMD_FPGA_SPI, reg_base, 0, buf, wrptr - buf);
485 sr_err("Cannot change PWM parameters.");
489 /* Enable configured channel after write completion. */
490 sr_spew("PWM config, enabling after param change.");
491 reg_val = enable_all | enable_cfg;
492 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0,
493 ®_val, sizeof(reg_val));
495 sr_err("Cannot adjust PWM enabled state.");
502 static uint32_t get_channels_mask(const struct sr_dev_inst *sdi)
506 struct sr_channel *ch;
509 for (l = sdi->channels; l; l = l->next) {
511 if (ch->type != SR_CHANNEL_LOGIC)
515 channels |= 1UL << ch->index;
521 static int set_trigger_config(const struct sr_dev_inst *sdi)
523 struct dev_context *devc;
524 struct sr_trigger *trigger;
529 uint32_t high_or_falling;
533 struct sr_trigger_stage *stage1;
534 struct sr_trigger_match *match;
537 uint8_t buf[REG_UNKNOWN_30 - REG_TRIGGER]; /* Width of REG_TRIGGER. */
541 trigger = sr_session_trigger_get(sdi->session);
543 memset(&cfg, 0, sizeof(cfg));
545 cfg.channels = get_channels_mask(sdi);
547 if (trigger && trigger->stages) {
548 stages = trigger->stages;
549 stage1 = stages->data;
551 sr_err("Only one trigger stage supported for now.");
554 channel = stage1->matches;
556 match = channel->data;
557 ch_mask = 1UL << match->channel->index;
559 switch (match->match) {
560 case SR_TRIGGER_ZERO:
561 cfg.level |= ch_mask;
562 cfg.high_or_falling &= ~ch_mask;
565 cfg.level |= ch_mask;
566 cfg.high_or_falling |= ch_mask;
568 case SR_TRIGGER_RISING:
569 if ((cfg.enabled & ~cfg.level)) {
570 sr_err("Device only supports one edge trigger.");
573 cfg.level &= ~ch_mask;
574 cfg.high_or_falling &= ~ch_mask;
576 case SR_TRIGGER_FALLING:
577 if ((cfg.enabled & ~cfg.level)) {
578 sr_err("Device only supports one edge trigger.");
581 cfg.level &= ~ch_mask;
582 cfg.high_or_falling |= ch_mask;
585 sr_err("Unknown trigger condition.");
588 cfg.enabled |= ch_mask;
589 channel = channel->next;
592 sr_dbg("Set trigger config: "
593 "channels 0x%04x, trigger-enabled 0x%04x, "
594 "level-triggered 0x%04x, high/falling 0x%04x.",
595 cfg.channels, cfg.enabled, cfg.level, cfg.high_or_falling);
597 devc->trigger_involved = cfg.enabled != 0;
600 write_u32le_inc(&wrptr, cfg.channels);
601 write_u32le_inc(&wrptr, cfg.enabled);
602 write_u32le_inc(&wrptr, cfg.level);
603 write_u32le_inc(&wrptr, cfg.high_or_falling);
605 * Comment on this literal 16. Origin, meaning? Cannot be the
606 * register offset, nor the transfer length. Is it a channels
607 * count that is relevant for 16 and 32 channel models? Is it
608 * an obsolete experiment?
610 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_TRIGGER, 16, buf, wrptr - buf);
612 sr_err("Cannot setup trigger configuration.");
619 static int set_sample_config(const struct sr_dev_inst *sdi)
621 struct dev_context *devc;
622 uint64_t min_samplerate, eff_samplerate;
623 uint16_t divider_u16;
624 uint64_t limit_samples;
625 uint64_t pre_trigger_samples;
626 uint64_t pre_trigger_memory;
627 uint8_t buf[REG_TRIGGER - REG_SAMPLING]; /* Width of REG_SAMPLING. */
633 if (devc->samplerate > devc->model->samplerate) {
634 sr_err("Too high a sample rate: %" PRIu64 ".",
638 min_samplerate = devc->model->samplerate;
639 min_samplerate /= 65536;
640 if (devc->samplerate < min_samplerate) {
641 sr_err("Too low a sample rate: %" PRIu64 ".",
645 divider_u16 = devc->model->samplerate / devc->samplerate;
646 eff_samplerate = devc->model->samplerate / divider_u16;
648 ret = sr_sw_limits_get_remain(&devc->sw_limits,
649 &limit_samples, NULL, NULL, NULL);
651 sr_err("Cannot get acquisition limits.");
654 if (limit_samples > LA2016_NUM_SAMPLES_MAX) {
655 sr_warn("Too high a sample depth: %" PRIu64 ", capping.",
657 limit_samples = LA2016_NUM_SAMPLES_MAX;
659 if (limit_samples == 0) {
660 limit_samples = LA2016_NUM_SAMPLES_MAX;
661 sr_dbg("Passing %" PRIu64 " to HW for unlimited samples.",
666 * The acquisition configuration communicates "pre-trigger"
667 * specs in several formats. sigrok users provide a percentage
668 * (0-100%), which translates to a pre-trigger samples count
669 * (assuming that a total samples count limit was specified).
670 * The device supports hardware compression, which depends on
671 * slowly changing input data to be effective. Fast changing
672 * input data may occupy more space in sample memory than its
673 * uncompressed form would. This is why a third parameter can
674 * limit the amount of sample memory to use for pre-trigger
675 * data. Only the upper 24 bits of that memory size spec get
676 * communicated to the device (written to its FPGA register).
678 * TODO Determine whether the pre-trigger memory size gets
679 * specified in samples or in bytes. A previous implementation
680 * suggests bytes but this is suspicious when every other spec
681 * is in terms of samples.
683 if (devc->trigger_involved) {
684 pre_trigger_samples = limit_samples;
685 pre_trigger_samples *= devc->capture_ratio;
686 pre_trigger_samples /= 100;
687 pre_trigger_memory = devc->model->memory_bits;
688 pre_trigger_memory *= UINT64_C(1024 * 1024 * 1024);
689 pre_trigger_memory /= 8; /* devc->model->channel_count ? */
690 pre_trigger_memory *= devc->capture_ratio;
691 pre_trigger_memory /= 100;
693 sr_dbg("No trigger setup, skipping pre-trigger config.");
694 pre_trigger_samples = 1;
695 pre_trigger_memory = 0;
697 /* Ensure non-zero value after LSB shift out in HW reg. */
698 if (pre_trigger_memory < 0x100) {
699 pre_trigger_memory = 0x100;
702 sr_dbg("Set sample config: %" PRIu64 "kHz, %" PRIu64 " samples.",
703 eff_samplerate / SR_KHZ(1), limit_samples);
704 sr_dbg("Capture ratio %" PRIu64 "%%, count %" PRIu64 ", mem %" PRIu64 ".",
705 devc->capture_ratio, pre_trigger_samples, pre_trigger_memory);
708 * The acquisition configuration occupies a total of 16 bytes:
709 * - A 34bit total samples count limit (up to 10 billions) that
710 * is kept in a 40bit register.
711 * - A 34bit pre-trigger samples count limit (up to 10 billions)
712 * in another 40bit register.
713 * - A 32bit pre-trigger memory space limit (in bytes) of which
714 * the upper 24bits are kept in an FPGA register.
715 * - A 16bit clock divider which gets applied to the maximum
716 * samplerate of the device.
717 * - An 8bit register of unknown meaning. Currently always 0.
720 write_u40le_inc(&wrptr, limit_samples);
721 write_u40le_inc(&wrptr, pre_trigger_samples);
722 write_u24le_inc(&wrptr, pre_trigger_memory >> 8);
723 write_u16le_inc(&wrptr, divider_u16);
724 write_u8_inc(&wrptr, 0);
725 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, wrptr - buf);
727 sr_err("Cannot setup acquisition configuration.");
735 * FPGA register REG_RUN holds the run state (u16le format). Bit fields
737 * bit 0: value 1 = idle
738 * bit 1: value 1 = writing to SDRAM
739 * bit 2: value 0 = waiting for trigger, 1 = trigger seen
740 * bit 3: value 0 = pretrigger sampling, 1 = posttrigger sampling
741 * The meaning of other bit fields is unknown.
743 * Typical values in order of appearance during execution:
744 * 0x85e1: idle, no acquisition pending
745 * IDLE set, TRGD don't care, POST don't care; DRAM don't care
746 * "In idle state." Takes precedence over all others.
747 * 0x85e2: pre-sampling, samples before the trigger position,
748 * when capture ratio > 0%
749 * IDLE clear, TRGD clear, POST clear; DRAM don't care
750 * "Not idle any more, no post yet, not triggered yet."
751 * 0x85ea: pre-sampling complete, now waiting for the trigger
752 * (whilst sampling continuously)
753 * IDLE clear, TRGD clear, POST set; DRAM don't care
754 * "Post set thus after pre, not triggered yet"
755 * 0x85ee: trigger seen, capturing post-trigger samples, running
756 * IDLE clear, TRGD set, POST set; DRAM don't care
757 * "Triggered and in post, not idle yet."
759 * IDLE set, TRGD don't care, POST don't care; DRAM don't care
760 * "In idle state." TRGD/POST don't care, same meaning as above.
762 static const uint16_t runstate_mask_idle = RUNSTATE_IDLE_BIT;
763 static const uint16_t runstate_patt_idle = RUNSTATE_IDLE_BIT;
764 static const uint16_t runstate_mask_step =
765 RUNSTATE_IDLE_BIT | RUNSTATE_TRGD_BIT | RUNSTATE_POST_BIT;
766 static const uint16_t runstate_patt_pre_trig = 0;
767 static const uint16_t runstate_patt_wait_trig = RUNSTATE_POST_BIT;
768 static const uint16_t runstate_patt_post_trig =
769 RUNSTATE_TRGD_BIT | RUNSTATE_POST_BIT;
771 static uint16_t run_state(const struct sr_dev_inst *sdi)
773 static uint16_t previous_state;
777 uint8_t buff[REG_PWM_EN - REG_RUN]; /* Width of REG_RUN. */
778 const uint8_t *rdptr;
781 ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, buff, sizeof(state));
783 sr_err("Cannot read run state.");
787 state = read_u16le_inc(&rdptr);
790 * Avoid flooding the log, only dump values as they change.
791 * The routine is called about every 50ms.
793 if (state == previous_state)
796 previous_state = state;
798 if ((state & runstate_mask_idle) == runstate_patt_idle)
800 if ((state & runstate_mask_step) == runstate_patt_pre_trig)
801 label = "pre-trigger sampling";
802 if ((state & runstate_mask_step) == runstate_patt_wait_trig)
803 label = "sampling, waiting for trigger";
804 if ((state & runstate_mask_step) == runstate_patt_post_trig)
805 label = "post-trigger sampling";
807 sr_dbg("Run state: 0x%04x (%s).", state, label);
809 sr_dbg("Run state: 0x%04x.", state);
814 static int la2016_is_idle(const struct sr_dev_inst *sdi)
818 state = run_state(sdi);
819 if ((state & runstate_mask_idle) == runstate_patt_idle)
825 static int set_run_mode(const struct sr_dev_inst *sdi, uint8_t mode)
829 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_RUN, 0, &mode, sizeof(mode));
831 sr_err("Cannot configure run mode %d.", mode);
838 static int get_capture_info(const struct sr_dev_inst *sdi)
840 struct dev_context *devc;
842 uint8_t buf[REG_TRIGGER - REG_SAMPLING]; /* Width of REG_SAMPLING. */
843 const uint8_t *rdptr;
847 ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, sizeof(buf));
849 sr_err("Cannot read capture info.");
854 devc->info.n_rep_packets = read_u32le_inc(&rdptr);
855 devc->info.n_rep_packets_before_trigger = read_u32le_inc(&rdptr);
856 devc->info.write_pos = read_u32le_inc(&rdptr);
858 sr_dbg("Capture info: n_rep_packets: 0x%08x/%d, before_trigger: 0x%08x/%d, write_pos: 0x%08x/%d.",
859 devc->info.n_rep_packets, devc->info.n_rep_packets,
860 devc->info.n_rep_packets_before_trigger,
861 devc->info.n_rep_packets_before_trigger,
862 devc->info.write_pos, devc->info.write_pos);
864 if (devc->info.n_rep_packets % NUM_PACKETS_IN_CHUNK) {
865 sr_warn("Unexpected packets count %lu, not a multiple of %d.",
866 (unsigned long)devc->info.n_rep_packets,
867 NUM_PACKETS_IN_CHUNK);
873 SR_PRIV int la2016_upload_firmware(const struct sr_dev_inst *sdi,
874 struct sr_context *sr_ctx, libusb_device *dev, uint16_t product_id)
876 struct dev_context *devc;
880 devc = sdi ? sdi->priv : NULL;
882 fw_file = g_strdup_printf(MCU_FWFILE_FMT, product_id);
883 sr_info("USB PID %04hx, MCU firmware '%s'.", product_id, fw_file);
885 ret = ezusb_upload_firmware(sr_ctx, dev, USB_CONFIGURATION, fw_file);
892 devc->mcu_firmware = fw_file;
900 SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi,
906 ret = set_threshold_voltage(sdi, voltage);
911 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_CAPT_MODE, 0, &cmd, sizeof(cmd));
913 sr_err("Cannot send command to stop sampling.");
917 ret = set_trigger_config(sdi);
921 ret = set_sample_config(sdi);
928 SR_PRIV int la2016_start_acquisition(const struct sr_dev_inst *sdi)
932 ret = set_run_mode(sdi, RUNMODE_RUN);
939 static int la2016_stop_acquisition(const struct sr_dev_inst *sdi)
943 ret = set_run_mode(sdi, RUNMODE_HALT);
950 SR_PRIV int la2016_abort_acquisition(const struct sr_dev_inst *sdi)
953 struct dev_context *devc;
955 ret = la2016_stop_acquisition(sdi);
959 devc = sdi ? sdi->priv : NULL;
960 if (devc && devc->transfer)
961 libusb_cancel_transfer(devc->transfer);
966 static int la2016_start_download(const struct sr_dev_inst *sdi,
967 libusb_transfer_cb_fn cb)
969 struct dev_context *devc;
970 struct sr_usb_dev_inst *usb;
972 uint8_t wrbuf[REG_SAMPLING - REG_BULK]; /* Width of REG_BULK. */
980 ret = get_capture_info(sdi);
984 devc->n_transfer_packets_to_read = devc->info.n_rep_packets / NUM_PACKETS_IN_CHUNK;
985 devc->n_bytes_to_read = devc->n_transfer_packets_to_read * TRANSFER_PACKET_LENGTH;
986 devc->read_pos = devc->info.write_pos - devc->n_bytes_to_read;
987 devc->n_reps_until_trigger = devc->info.n_rep_packets_before_trigger;
989 sr_dbg("Want to read %u xfer-packets starting from pos %" PRIu32 ".",
990 devc->n_transfer_packets_to_read, devc->read_pos);
992 ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0);
994 sr_err("Cannot reset USB bulk state.");
997 sr_dbg("Will read from 0x%08lx, 0x%08x bytes.",
998 (unsigned long)devc->read_pos, devc->n_bytes_to_read);
1000 write_u32le_inc(&wrptr, devc->read_pos);
1001 write_u32le_inc(&wrptr, devc->n_bytes_to_read);
1002 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_BULK, 0, wrbuf, wrptr - wrbuf);
1004 sr_err("Cannot send USB bulk config.");
1007 ret = ctrl_out(sdi, CMD_BULK_START, 0x00, 0, NULL, 0);
1009 sr_err("Cannot unblock USB bulk transfers.");
1014 * Pick a buffer size for all USB transfers. The buffer size
1015 * must be a multiple of the endpoint packet size. And cannot
1016 * exceed a maximum value.
1018 to_read = devc->n_bytes_to_read;
1019 if (to_read >= LA2016_USB_BUFSZ) /* Multiple transfers. */
1020 to_read = LA2016_USB_BUFSZ;
1021 to_read += LA2016_EP6_PKTSZ - 1;
1022 to_read /= LA2016_EP6_PKTSZ;
1023 to_read *= LA2016_EP6_PKTSZ;
1024 buffer = g_try_malloc(to_read);
1026 sr_dbg("USB bulk transfer size %d bytes.", (int)to_read);
1027 sr_err("Cannot allocate buffer for USB bulk transfer.");
1028 return SR_ERR_MALLOC;
1031 devc->transfer = libusb_alloc_transfer(0);
1032 libusb_fill_bulk_transfer(devc->transfer,
1033 usb->devhdl, USB_EP_CAPTURE_DATA | LIBUSB_ENDPOINT_IN,
1034 buffer, to_read, cb, (void *)sdi, DEFAULT_TIMEOUT_MS);
1036 ret = libusb_submit_transfer(devc->transfer);
1038 sr_err("Cannot submit USB transfer: %s.", libusb_error_name(ret));
1039 libusb_free_transfer(devc->transfer);
1040 devc->transfer = NULL;
1049 * A chunk (received via USB) contains a number of transfers (USB length
1050 * divided by 16) which contain a number of packets (5 per transfer) which
1051 * contain a number of samples (8bit repeat count per 16bit sample data).
1053 static void send_chunk(struct sr_dev_inst *sdi,
1054 const uint8_t *packets, size_t num_xfers)
1056 struct dev_context *devc;
1059 uint32_t sample_value;
1061 uint8_t sample_buff[sizeof(sample_value)];
1065 /* Ignore incoming USB data after complete sample data download. */
1066 if (devc->download_finished)
1069 if (devc->trigger_involved && !devc->trigger_marked && devc->info.n_rep_packets_before_trigger == 0) {
1070 feed_queue_logic_send_trigger(devc->feed_queue);
1071 devc->trigger_marked = TRUE;
1076 while (num_xfers--) {
1077 /* XXX model dependent? 5 or 3? */
1078 num_pkts = NUM_PACKETS_IN_CHUNK;
1079 while (num_pkts--) {
1081 /* TODO Verify 32channel layout. */
1082 if (devc->model->channel_count == 32)
1083 sample_value = read_u32le_inc(&rp);
1084 else if (devc->model->channel_count == 16)
1085 sample_value = read_u16le_inc(&rp);
1086 repetitions = read_u8_inc(&rp);
1088 devc->total_samples += repetitions;
1090 write_u32le(sample_buff, sample_value);
1091 feed_queue_logic_submit(devc->feed_queue,
1092 sample_buff, repetitions);
1093 sr_sw_limits_update_samples_read(&devc->sw_limits,
1096 if (devc->trigger_involved && !devc->trigger_marked) {
1097 if (!--devc->n_reps_until_trigger) {
1098 feed_queue_logic_send_trigger(devc->feed_queue);
1099 devc->trigger_marked = TRUE;
1100 sr_dbg("Trigger position after %" PRIu64 " samples, %.6fms.",
1101 devc->total_samples,
1102 (double)devc->total_samples / devc->samplerate * 1e3);
1106 (void)read_u8_inc(&rp); /* Skip sequence number. */
1109 if (!devc->download_finished && sr_sw_limits_check(&devc->sw_limits)) {
1110 sr_dbg("Acquisition limit reached.");
1111 devc->download_finished = TRUE;
1113 if (devc->download_finished) {
1114 sr_dbg("Download finished, flushing session feed queue.");
1115 feed_queue_logic_flush(devc->feed_queue);
1117 sr_dbg("Total samples after chunk: %" PRIu64 ".", devc->total_samples);
1120 static void LIBUSB_CALL receive_transfer(struct libusb_transfer *transfer)
1122 struct sr_dev_inst *sdi;
1123 struct dev_context *devc;
1124 struct sr_usb_dev_inst *usb;
1128 sdi = transfer->user_data;
1132 sr_dbg("receive_transfer(): status %s received %d bytes.",
1133 libusb_error_name(transfer->status), transfer->actual_length);
1135 * Implementation detail: A USB transfer timeout is not fatal
1136 * here. We just process whatever was received, empty input is
1137 * perfectly acceptable. Reaching (or exceeding) the sw limits
1138 * or exhausting the device's captured data will complete the
1139 * sample data download.
1141 num_xfers = transfer->actual_length / TRANSFER_PACKET_LENGTH;
1142 send_chunk(sdi, transfer->buffer, num_xfers);
1144 devc->n_bytes_to_read -= transfer->actual_length;
1145 if (devc->n_bytes_to_read) {
1146 uint32_t to_read = devc->n_bytes_to_read;
1148 * Determine read size for the next USB transfer. Make
1149 * the buffer size a multiple of the endpoint packet
1150 * size. Don't exceed a maximum value.
1152 if (to_read >= LA2016_USB_BUFSZ)
1153 to_read = LA2016_USB_BUFSZ;
1154 to_read += LA2016_EP6_PKTSZ - 1;
1155 to_read /= LA2016_EP6_PKTSZ;
1156 to_read *= LA2016_EP6_PKTSZ;
1157 libusb_fill_bulk_transfer(transfer,
1158 usb->devhdl, USB_EP_CAPTURE_DATA | LIBUSB_ENDPOINT_IN,
1159 transfer->buffer, to_read,
1160 receive_transfer, (void *)sdi, DEFAULT_TIMEOUT_MS);
1162 ret = libusb_submit_transfer(transfer);
1165 sr_err("Cannot submit another USB transfer: %s.",
1166 libusb_error_name(ret));
1169 g_free(transfer->buffer);
1170 libusb_free_transfer(transfer);
1171 devc->download_finished = TRUE;
1174 SR_PRIV int la2016_receive_data(int fd, int revents, void *cb_data)
1176 const struct sr_dev_inst *sdi;
1177 struct dev_context *devc;
1178 struct drv_context *drvc;
1187 drvc = sdi->driver->context;
1190 * Wait for the acquisition to complete in hardware.
1191 * Periodically check a potentially configured msecs timeout.
1193 if (!devc->completion_seen) {
1194 if (!la2016_is_idle(sdi)) {
1195 if (sr_sw_limits_check(&devc->sw_limits)) {
1196 devc->sw_limits.limit_msec = 0;
1197 sr_dbg("Limit reached. Stopping acquisition.");
1198 la2016_stop_acquisition(sdi);
1200 /* Not yet ready for sample data download. */
1203 sr_dbg("Acquisition completion seen (hardware).");
1204 devc->sw_limits.limit_msec = 0;
1205 devc->completion_seen = TRUE;
1206 devc->download_finished = FALSE;
1207 devc->trigger_marked = FALSE;
1208 devc->total_samples = 0;
1210 /* Initiate the download of acquired sample data. */
1211 std_session_send_df_frame_begin(sdi);
1212 ret = la2016_start_download(sdi, receive_transfer);
1214 sr_err("Cannot start acquisition data download.");
1217 sr_dbg("Acquisition data download started.");
1222 /* Handle USB reception. Drives sample data download. */
1223 tv.tv_sec = tv.tv_usec = 0;
1224 libusb_handle_events_timeout(drvc->sr_ctx->libusb_ctx, &tv);
1226 /* Postprocess completion of sample data download. */
1227 if (devc->download_finished) {
1228 sr_dbg("Download finished, post processing.");
1230 la2016_stop_acquisition(sdi);
1231 usb_source_remove(sdi->session, drvc->sr_ctx);
1232 devc->transfer = NULL;
1234 feed_queue_logic_flush(devc->feed_queue);
1235 feed_queue_logic_free(devc->feed_queue);
1236 devc->feed_queue = NULL;
1237 std_session_send_df_frame_end(sdi);
1238 std_session_send_df_end(sdi);
1240 sr_dbg("Download finished, done post processing.");
1246 SR_PRIV int la2016_identify_device(const struct sr_dev_inst *sdi,
1247 gboolean show_message)
1249 struct dev_context *devc;
1250 uint8_t buf[8]; /* Larger size of manuf date and device type magic. */
1251 size_t rdoff, rdlen;
1252 const uint8_t *rdptr;
1253 uint8_t date_yy, date_mm;
1254 uint8_t dinv_yy, dinv_mm;
1257 const struct kingst_model *model;
1263 * Four EEPROM bytes at offset 0x20 are the manufacturing date,
1264 * year and month in BCD format, followed by inverted values for
1265 * consistency checks. For example bytes 20 04 df fb translate
1266 * to 2020-04. This information can help identify the vintage of
1267 * devices when unknown magic numbers are seen.
1270 rdlen = 4 * sizeof(uint8_t);
1271 ret = ctrl_in(sdi, CMD_EEPROM, rdoff, 0, buf, rdlen);
1272 if (ret != SR_OK && !show_message) {
1273 /* Non-fatal weak attempt during probe. Not worth logging. */
1274 sr_dbg("Cannot access EEPROM.");
1276 } else if (ret != SR_OK) {
1277 /* Failed attempt in regular use. Non-fatal. Worth logging. */
1278 sr_err("Cannot read manufacture date in EEPROM.");
1280 if (sr_log_loglevel_get() >= SR_LOG_SPEW) {
1282 txt = sr_hexdump_new(buf, rdlen);
1283 sr_spew("Manufacture date bytes %s.", txt->str);
1284 sr_hexdump_free(txt);
1287 date_yy = read_u8_inc(&rdptr);
1288 date_mm = read_u8_inc(&rdptr);
1289 dinv_yy = read_u8_inc(&rdptr);
1290 dinv_mm = read_u8_inc(&rdptr);
1291 sr_info("Manufacture date: 20%02hx-%02hx.", date_yy, date_mm);
1292 if ((date_mm ^ dinv_mm) != 0xff || (date_yy ^ dinv_yy) != 0xff)
1293 sr_warn("Manufacture date fails checksum test.");
1297 * Several Kingst logic analyzer devices share the same USB VID
1298 * and PID. The product ID determines which MCU firmware to load.
1299 * The MCU firmware provides access to EEPROM content which then
1300 * allows to identify the device model. Which in turn determines
1301 * which FPGA bitstream to load. Eight bytes at offset 0x08 are
1304 * EEPROM content for model identification is kept redundantly
1305 * in memory. The values are stored in verbatim and in inverted
1306 * form, multiple copies are kept at different offsets. Example
1317 * Exclusively inspecting the magic byte appears to be sufficient,
1318 * other fields seem to be 'don't care'.
1320 * magic 2 == LA2016 using "kingst-la2016-fpga.bitstream"
1321 * magic 3 == LA1016 using "kingst-la1016-fpga.bitstream"
1322 * magic 8 == LA2016a using "kingst-la2016a1-fpga.bitstream"
1323 * (latest v1.3.0 PCB, perhaps others)
1324 * magic 9 == LA1016a using "kingst-la1016a1-fpga.bitstream"
1325 * (latest v1.3.0 PCB, perhaps others)
1327 * When EEPROM content does not match the hardware configuration
1328 * (the board layout), the software may load but yield incorrect
1329 * results (like swapped channels). The FPGA bitstream itself
1330 * will authenticate with IC U10 and fail when its capabilities
1331 * do not match the hardware model. An LA1016 won't become a
1332 * LA2016 by faking its EEPROM content.
1334 devc->identify_magic = 0;
1336 rdlen = 8 * sizeof(uint8_t);
1337 ret = ctrl_in(sdi, CMD_EEPROM, rdoff, 0, &buf, rdlen);
1339 sr_err("Cannot read EEPROM device identifier bytes.");
1342 if (sr_log_loglevel_get() >= SR_LOG_SPEW) {
1344 txt = sr_hexdump_new(buf, rdlen);
1345 sr_spew("EEPROM magic bytes %s.", txt->str);
1346 sr_hexdump_free(txt);
1348 if ((buf[0] ^ buf[1]) == 0xff) {
1349 /* Primary copy of magic passes complement check. */
1351 sr_dbg("Using primary magic, value %d.", (int)magic);
1352 } else if ((buf[4] ^ buf[5]) == 0xff) {
1353 /* Backup copy of magic passes complement check. */
1355 sr_dbg("Using backup magic, value %d.", (int)magic);
1357 sr_err("Cannot find consistent device type identification.");
1360 devc->identify_magic = magic;
1363 for (model_idx = 0; model_idx < ARRAY_SIZE(models); model_idx++) {
1364 model = &models[model_idx];
1365 if (model->magic != magic)
1367 devc->model = model;
1368 sr_info("Model '%s', %zu channels, max %" PRIu64 "MHz.",
1369 model->name, model->channel_count,
1370 model->samplerate / SR_MHZ(1));
1371 devc->fpga_bitstream = g_strdup_printf(FPGA_FWFILE_FMT,
1373 sr_info("FPGA bitstream file '%s'.", devc->fpga_bitstream);
1377 sr_err("Cannot identify as one of the supported models.");
1384 SR_PRIV int la2016_init_hardware(const struct sr_dev_inst *sdi)
1386 struct dev_context *devc;
1387 const char *bitstream_fn;
1392 bitstream_fn = devc ? devc->fpga_bitstream : "";
1394 ret = check_fpga_bitstream(sdi);
1396 ret = upload_fpga_bitstream(sdi, bitstream_fn);
1398 sr_err("Cannot upload FPGA bitstream.");
1402 ret = enable_fpga_bitstream(sdi);
1404 sr_err("Cannot enable FPGA bitstream after upload.");
1408 state = run_state(sdi);
1409 if (state != 0x85e9) {
1410 sr_warn("Unexpected run state, want 0x85e9, got 0x%04x.", state);
1413 ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0);
1415 sr_err("Cannot reset USB bulk transfer.");
1419 sr_dbg("Device should be initialized.");
1424 SR_PRIV int la2016_deinit_hardware(const struct sr_dev_inst *sdi)
1428 ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x00, 0, NULL, 0);
1430 sr_err("Cannot deinitialize device's FPGA.");
1437 SR_PRIV int la2016_write_pwm_config(const struct sr_dev_inst *sdi, size_t idx)
1439 return set_pwm_config(sdi, idx);