2 * This file is part of the libsigrok project.
4 * Copyright (C) 2016 Andreas Zschunke <andreas.zschunke@gmx.net>
5 * Copyright (C) 2017 Andrej Valek <andy@skyrain.eu>
6 * Copyright (C) 2017 Uwe Hermann <uwe@hermann-uwe.de>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
25 #define USB_INTERFACE 0
26 #define NUM_CHANNELS 32
28 static const uint32_t scanopts[] = {
32 static const uint32_t drvopts[] = {
33 SR_CONF_LOGIC_ANALYZER,
36 static const uint32_t devopts[] = {
37 SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
38 SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
39 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
40 SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
41 SR_CONF_CONN | SR_CONF_GET,
42 SR_CONF_EXTERNAL_CLOCK | SR_CONF_GET | SR_CONF_SET,
43 SR_CONF_EXTERNAL_CLOCK_SOURCE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
44 SR_CONF_CLOCK_EDGE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
47 static const uint32_t devopts_fpga_zero[] = {
48 SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
49 SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
50 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
51 SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
52 SR_CONF_CONN | SR_CONF_GET,
55 static const uint32_t devopts_cg[] = {
56 SR_CONF_VOLTAGE_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
59 static const char *signal_edges[] = {
60 [H4032L_CLOCK_EDGE_TYPE_RISE] = "rising",
61 [H4032L_CLOCK_EDGE_TYPE_FALL] = "falling",
62 [H4032L_CLOCK_EDGE_TYPE_BOTH] = "both",
65 static const char *ext_clock_sources[] = {
66 [H4032L_EXT_CLOCK_SOURCE_CHANNEL_A] = "ACLK",
67 [H4032L_EXT_CLOCK_SOURCE_CHANNEL_B] = "BCLK"
70 static const uint8_t ext_clock_edges[2][3] = {
72 H4032L_CLOCK_EDGE_TYPE_RISE_A,
73 H4032L_CLOCK_EDGE_TYPE_FALL_A,
74 H4032L_CLOCK_EDGE_TYPE_BOTH_A
77 H4032L_CLOCK_EDGE_TYPE_RISE_B,
78 H4032L_CLOCK_EDGE_TYPE_FALL_B,
79 H4032L_CLOCK_EDGE_TYPE_BOTH_B
83 static const int32_t trigger_matches[] = {
91 static const uint64_t samplerates[] = {
127 static const uint64_t samplerates_hw[] = {
166 SR_PRIV struct sr_dev_driver hantek_4032l_driver_info;
168 static GSList *scan(struct sr_dev_driver *di, GSList *options)
170 struct drv_context *drvc = di->context;
171 GSList *l, *devices, *conn_devices;
172 libusb_device **devlist;
173 struct libusb_device_descriptor des;
176 char connection_id[64];
177 struct sr_channel_group *cg;
178 struct sr_dev_inst *sdi;
179 struct sr_channel *ch;
183 drvc->instances = NULL;
186 for (l = options; l; l = l->next) {
187 struct sr_config *src = l->data;
188 if (src->key == SR_CONF_CONN) {
189 conn = g_variant_get_string(src->data, NULL);
195 conn_devices = sr_usb_find(drvc->sr_ctx->libusb_ctx, conn);
199 libusb_get_device_list(drvc->sr_ctx->libusb_ctx, &devlist);
200 for (i = 0; devlist[i]; i++) {
202 struct sr_usb_dev_inst *usb = NULL;
203 for (l = conn_devices; l; l = l->next) {
205 if (usb->bus == libusb_get_bus_number(devlist[i]) &&
206 usb->address == libusb_get_device_address(devlist[i]))
210 /* This device matched none of the ones that
211 * matched the conn specification. */
215 libusb_get_device_descriptor(devlist[i], &des);
217 if (des.idVendor != H4032L_USB_VENDOR ||
218 des.idProduct != H4032L_USB_PRODUCT)
221 if (usb_get_port_path(devlist[i], connection_id, sizeof(connection_id)) < 0)
224 sdi = g_malloc0(sizeof(struct sr_dev_inst));
225 sdi->driver = &hantek_4032l_driver_info;
226 sdi->vendor = g_strdup("Hantek");
227 sdi->model = g_strdup("4032L");
228 sdi->connection_id = g_strdup(connection_id);
230 struct sr_channel_group *channel_groups[2];
231 for (int j = 0; j < 2; j++) {
232 cg = g_malloc0(sizeof(struct sr_channel_group));
233 cg->name = g_strdup_printf("%c", 'A' + j);
234 channel_groups[j] = cg;
235 sdi->channel_groups = g_slist_append(sdi->channel_groups, cg);
238 /* Assemble channel list and add channel to channel groups. */
239 for (int j = 0; j < NUM_CHANNELS; j++) {
240 char channel_name[4];
241 sprintf(channel_name, "%c%d", 'A' + (j & 1), j / 2);
242 ch = sr_channel_new(sdi, j, SR_CHANNEL_LOGIC, TRUE, channel_name);
243 cg = channel_groups[j & 1];
244 cg->channels = g_slist_append(cg->channels, ch);
247 struct dev_context *devc = g_malloc0(sizeof(struct dev_context));
249 /* Initialize command packet. */
250 devc->cmd_pkt.magic = H4032L_CMD_PKT_MAGIC;
251 devc->cmd_pkt.sample_size = 16384;
252 devc->sample_rate = 0;
254 devc->status = H4032L_STATUS_IDLE;
256 devc->capture_ratio = 5;
257 devc->external_clock = FALSE;
258 devc->clock_edge = H4032L_CLOCK_EDGE_TYPE_RISE;
260 devc->cur_threshold[0] = 2.5;
261 devc->cur_threshold[1] = 2.5;
264 devices = g_slist_append(devices, sdi);
266 sdi->status = SR_ST_INACTIVE;
267 sdi->inst_type = SR_INST_USB;
268 sdi->conn = sr_usb_dev_inst_new(
269 libusb_get_bus_number(devlist[i]),
270 libusb_get_device_address(devlist[i]), NULL);
273 g_slist_free_full(conn_devices, (GDestroyNotify)sr_usb_dev_inst_free);
274 libusb_free_device_list(devlist, 1);
276 return std_scan_complete(di, devices);
279 static int dev_open(struct sr_dev_inst *sdi)
281 struct sr_usb_dev_inst *usb = sdi->conn;
284 ret = h4032l_dev_open(sdi);
286 sr_err("Unable to open device.");
290 ret = libusb_claim_interface(usb->devhdl, USB_INTERFACE);
293 case LIBUSB_ERROR_BUSY:
294 sr_err("Unable to claim USB interface. Another "
295 "program or driver has already claimed it.");
297 case LIBUSB_ERROR_NO_DEVICE:
298 sr_err("Device has been disconnected.");
301 sr_err("Unable to claim interface: %s.",
302 libusb_error_name(ret));
309 /* Get FPGA version. */
310 if ((ret = h4032l_get_fpga_version(sdi)) != SR_OK)
316 static int dev_close(struct sr_dev_inst *sdi)
318 struct sr_usb_dev_inst *usb;
325 sr_info("Closing device on %d.%d (logical) / %s (physical) interface %d.",
326 usb->bus, usb->address, sdi->connection_id, USB_INTERFACE);
327 libusb_release_interface(usb->devhdl, USB_INTERFACE);
328 libusb_close(usb->devhdl);
334 static int config_get(uint32_t key, GVariant **data,
335 const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
337 struct dev_context *devc = sdi->priv;
338 struct sr_usb_dev_inst *usb;
342 case SR_CONF_VOLTAGE_THRESHOLD:
344 return SR_ERR_CHANNEL_GROUP;
345 if (!strcmp(cg->name, "A"))
346 *data = std_gvar_tuple_double(
347 devc->cur_threshold[0], devc->cur_threshold[0]);
348 else if (!strcmp(cg->name, "B"))
349 *data = std_gvar_tuple_double(
350 devc->cur_threshold[1], devc->cur_threshold[1]);
352 return SR_ERR_CHANNEL_GROUP;
354 case SR_CONF_SAMPLERATE:
355 *data = g_variant_new_uint64(samplerates_hw[devc->sample_rate]);
357 case SR_CONF_CAPTURE_RATIO:
358 *data = g_variant_new_uint64(devc->capture_ratio);
360 case SR_CONF_LIMIT_SAMPLES:
361 *data = g_variant_new_uint64(devc->cmd_pkt.sample_size);
363 case SR_CONF_EXTERNAL_CLOCK:
364 *data = g_variant_new_boolean(devc->external_clock);
366 case SR_CONF_EXTERNAL_CLOCK_SOURCE:
367 idx = devc->external_clock_source;
368 if (idx >= ARRAY_SIZE(ext_clock_sources))
370 *data = g_variant_new_string(ext_clock_sources[idx]);
373 if (!sdi || !(usb = sdi->conn))
375 *data = g_variant_new_printf("%d.%d", usb->bus, usb->address);
377 case SR_CONF_CLOCK_EDGE:
378 idx = devc->clock_edge;
379 if (idx >= ARRAY_SIZE(signal_edges))
381 *data = g_variant_new_string(signal_edges[idx]);
390 static int config_set(uint32_t key, GVariant *data,
391 const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
394 struct dev_context *devc = sdi->priv;
395 struct h4032l_cmd_pkt *cmd_pkt = &devc->cmd_pkt;
396 uint64_t sample_rate, capture_ratio, number_samples;
397 double low, high, threshold;
400 case SR_CONF_SAMPLERATE:
402 sample_rate = g_variant_get_uint64(data);
403 while (idx < ARRAY_SIZE(samplerates_hw) && samplerates_hw[idx] != sample_rate)
405 if (idx == ARRAY_SIZE(samplerates_hw) || sample_rate == 0) {
406 sr_err("Invalid sample rate.");
407 return SR_ERR_SAMPLERATE;
409 devc->sample_rate = idx;
411 case SR_CONF_CAPTURE_RATIO:
412 capture_ratio = g_variant_get_uint64(data);
413 if (capture_ratio > 99) {
414 sr_err("Invalid capture ratio.");
417 devc->capture_ratio = capture_ratio;
419 case SR_CONF_LIMIT_SAMPLES:
420 number_samples = g_variant_get_uint64(data);
421 number_samples += 511;
422 number_samples &= 0xfffffe00;
423 if (number_samples < H4043L_NUM_SAMPLES_MIN ||
424 number_samples > H4032L_NUM_SAMPLES_MAX) {
425 sr_err("Invalid sample range 2k...64M: %"
426 PRIu64 ".", number_samples);
429 cmd_pkt->sample_size = number_samples;
431 case SR_CONF_VOLTAGE_THRESHOLD:
433 return SR_ERR_CHANNEL_GROUP;
434 g_variant_get(data, "(dd)", &low, &high);
435 threshold = (low + high) / 2.0;
436 if (!strcmp(cg->name, "A"))
437 devc->cur_threshold[0] = threshold;
438 else if (!strcmp(cg->name, "B"))
439 devc->cur_threshold[1] = threshold;
441 return SR_ERR_CHANNEL_GROUP;
443 case SR_CONF_EXTERNAL_CLOCK:
444 devc->external_clock = g_variant_get_boolean(data);
446 case SR_CONF_EXTERNAL_CLOCK_SOURCE:
447 if ((idx = std_str_idx(data, ARRAY_AND_SIZE(ext_clock_sources))) < 0)
449 devc->external_clock_source = idx;
451 case SR_CONF_CLOCK_EDGE:
452 if ((idx = std_str_idx(data, ARRAY_AND_SIZE(signal_edges))) < 0)
454 devc->clock_edge = idx;
463 static int config_list(uint32_t key, GVariant **data,
464 const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
466 struct dev_context *devc = (sdi) ? sdi->priv : NULL;
469 case SR_CONF_SCAN_OPTIONS:
470 case SR_CONF_DEVICE_OPTIONS:
472 *data = std_gvar_array_u32(ARRAY_AND_SIZE(devopts_cg));
475 /* Disable external clock and edges for FPGA version 0. */
476 if (devc && (!devc->fpga_version))
477 return STD_CONFIG_LIST(key, data, sdi, cg, scanopts, drvopts, devopts_fpga_zero);
478 return STD_CONFIG_LIST(key, data, sdi, cg, scanopts, drvopts, devopts);
479 case SR_CONF_SAMPLERATE:
480 *data = std_gvar_samplerates(ARRAY_AND_SIZE(samplerates));
482 case SR_CONF_TRIGGER_MATCH:
483 *data = std_gvar_array_i32(ARRAY_AND_SIZE(trigger_matches));
485 case SR_CONF_VOLTAGE_THRESHOLD:
486 *data = std_gvar_min_max_step_thresholds(-6.0, 6.0, 0.1);
488 case SR_CONF_LIMIT_SAMPLES:
489 *data = std_gvar_tuple_u64(H4043L_NUM_SAMPLES_MIN, H4032L_NUM_SAMPLES_MAX);
491 case SR_CONF_CLOCK_EDGE:
492 *data = g_variant_new_strv(ARRAY_AND_SIZE(signal_edges));
494 case SR_CONF_EXTERNAL_CLOCK_SOURCE:
495 *data = g_variant_new_strv(ARRAY_AND_SIZE(ext_clock_sources));
504 static int dev_acquisition_start(const struct sr_dev_inst *sdi)
506 struct sr_dev_driver *di = sdi->driver;
507 struct drv_context *drvc = di->context;
508 struct dev_context *devc = sdi->priv;
509 struct sr_trigger *trigger = sr_session_trigger_get(sdi->session);
510 struct h4032l_cmd_pkt *cmd_pkt = &devc->cmd_pkt;
512 /* Initialize variables. */
513 devc->acq_aborted = FALSE;
514 devc->submitted_transfers = 0;
515 devc->sent_samples = 0;
517 /* Calculate packet ratio. */
518 cmd_pkt->pre_trigger_size = (cmd_pkt->sample_size * devc->capture_ratio) / 100;
519 devc->trigger_pos = cmd_pkt->pre_trigger_size;
521 /* Set clock edge, when external clock is enabled. */
522 if (devc->external_clock)
523 cmd_pkt->sample_rate = ext_clock_edges[devc->external_clock_source][devc->clock_edge];
525 cmd_pkt->sample_rate = devc->sample_rate;
527 /* Set pwm channel values. */
528 devc->cmd_pkt.pwm_a = h4032l_voltage2pwm(devc->cur_threshold[0]);
529 devc->cmd_pkt.pwm_b = h4032l_voltage2pwm(devc->cur_threshold[1]);
531 cmd_pkt->trig_flags.enable_trigger1 = 0;
532 cmd_pkt->trig_flags.enable_trigger2 = 0;
533 cmd_pkt->trig_flags.trigger_and_logic = 0;
535 if (trigger && trigger->stages) {
536 GSList *stages = trigger->stages;
537 struct sr_trigger_stage *stage1 = stages->data;
539 sr_err("Only one trigger stage supported for now.");
542 cmd_pkt->trig_flags.enable_trigger1 = 1;
543 cmd_pkt->trigger[0].flags.edge_type = H4032L_TRIGGER_EDGE_TYPE_DISABLED;
544 cmd_pkt->trigger[0].flags.data_range_enabled = 0;
545 cmd_pkt->trigger[0].flags.time_range_enabled = 0;
546 cmd_pkt->trigger[0].flags.combined_enabled = 0;
547 cmd_pkt->trigger[0].flags.data_range_type = H4032L_TRIGGER_DATA_RANGE_TYPE_MAX;
548 cmd_pkt->trigger[0].data_range_mask = 0;
549 cmd_pkt->trigger[0].data_range_max = 0;
551 /* Initialize range mask values. */
552 uint32_t range_mask = 0;
553 uint32_t range_value = 0;
555 GSList *channel = stage1->matches;
557 struct sr_trigger_match *match = channel->data;
559 switch (match->match) {
560 case SR_TRIGGER_ZERO:
561 range_mask |= (1 << match->channel->index);
564 range_mask |= (1 << match->channel->index);
565 range_value |= (1 << match->channel->index);
567 case SR_TRIGGER_RISING:
568 if (cmd_pkt->trigger[0].flags.edge_type != H4032L_TRIGGER_EDGE_TYPE_DISABLED) {
569 sr_err("Only one trigger signal with fall/rising/edge allowed.");
572 cmd_pkt->trigger[0].flags.edge_type = H4032L_TRIGGER_EDGE_TYPE_RISE;
573 cmd_pkt->trigger[0].flags.edge_signal = match->channel->index;
575 case SR_TRIGGER_FALLING:
576 if (cmd_pkt->trigger[0].flags.edge_type != H4032L_TRIGGER_EDGE_TYPE_DISABLED) {
577 sr_err("Only one trigger signal with fall/rising/edge allowed.");
580 cmd_pkt->trigger[0].flags.edge_type = H4032L_TRIGGER_EDGE_TYPE_FALL;
581 cmd_pkt->trigger[0].flags.edge_signal = match->channel->index;
583 case SR_TRIGGER_EDGE:
584 if (cmd_pkt->trigger[0].flags.edge_type != H4032L_TRIGGER_EDGE_TYPE_DISABLED) {
585 sr_err("Only one trigger signal with fall/rising/edge allowed.");
588 cmd_pkt->trigger[0].flags.edge_type = H4032L_TRIGGER_EDGE_TYPE_TOGGLE;
589 cmd_pkt->trigger[0].flags.edge_signal = match->channel->index;
592 sr_err("Unknown trigger value.");
596 channel = channel->next;
599 /* Compress range mask value and apply range settings. */
601 cmd_pkt->trigger[0].flags.data_range_enabled = 1;
602 cmd_pkt->trigger[0].data_range_mask |= (range_mask);
604 uint32_t new_range_value = 0;
605 uint32_t bit_mask = 1;
607 if ((range_mask & 1) != 0) {
608 new_range_value <<= 1;
609 if ((range_value & 1) != 0)
610 new_range_value |= bit_mask;
616 cmd_pkt->trigger[0].data_range_max |= range_value;
620 usb_source_add(sdi->session, drvc->sr_ctx, 1000,
621 h4032l_receive_data, sdi->driver->context);
623 /* Start capturing. */
624 return h4032l_start(sdi);
627 static int dev_acquisition_stop(struct sr_dev_inst *sdi)
629 /* Stop capturing. */
630 return h4032l_stop(sdi);
633 SR_PRIV struct sr_dev_driver hantek_4032l_driver_info = {
634 .name = "hantek-4032l",
635 .longname = "Hantek 4032L",
638 .cleanup = std_cleanup,
640 .dev_list = std_dev_list,
641 .dev_clear = std_dev_clear,
642 .config_get = config_get,
643 .config_set = config_set,
644 .config_list = config_list,
645 .dev_open = dev_open,
646 .dev_close = dev_close,
647 .dev_acquisition_start = dev_acquisition_start,
648 .dev_acquisition_stop = dev_acquisition_stop,
651 SR_REGISTER_DEV_DRIVER(hantek_4032l_driver_info);