2 * This file is part of the libsigrok project.
4 * Copyright (C) 2016 Andreas Zschunke <andreas.zschunke@gmx.net>
5 * Copyright (C) 2017 Andrej Valek <andy@skyrain.eu>
6 * Copyright (C) 2017 Uwe Hermann <uwe@hermann-uwe.de>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
25 #define USB_INTERFACE 0
26 #define NUM_CHANNELS 32
28 static const uint32_t scanopts[] = {
32 static const uint32_t drvopts[] = {
33 SR_CONF_LOGIC_ANALYZER,
36 static const uint32_t devopts[] = {
37 SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
38 SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
39 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
40 SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
41 SR_CONF_CONN | SR_CONF_GET,
42 SR_CONF_EXTERNAL_CLOCK | SR_CONF_GET | SR_CONF_SET,
43 SR_CONF_EXTERNAL_CLOCK_SOURCE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
44 SR_CONF_CLOCK_EDGE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
47 static const uint32_t devopts_fpga_zero[] = {
48 SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
49 SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
50 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
51 SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
52 SR_CONF_CONN | SR_CONF_GET,
55 static const uint32_t devopts_cg[] = {
56 SR_CONF_VOLTAGE_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
59 static const char *cg_names[] = {
63 static const char *signal_edges[] = {
64 [H4032L_CLOCK_EDGE_TYPE_RISE] = "rising",
65 [H4032L_CLOCK_EDGE_TYPE_FALL] = "falling",
66 [H4032L_CLOCK_EDGE_TYPE_BOTH] = "both",
69 static const char *ext_clock_sources[] = {
70 [H4032L_EXT_CLOCK_SOURCE_CHANNEL_A] = "ACLK",
71 [H4032L_EXT_CLOCK_SOURCE_CHANNEL_B] = "BCLK"
74 static const uint8_t ext_clock_edges[2][3] = {
76 H4032L_CLOCK_EDGE_TYPE_RISE_A,
77 H4032L_CLOCK_EDGE_TYPE_FALL_A,
78 H4032L_CLOCK_EDGE_TYPE_BOTH_A
81 H4032L_CLOCK_EDGE_TYPE_RISE_B,
82 H4032L_CLOCK_EDGE_TYPE_FALL_B,
83 H4032L_CLOCK_EDGE_TYPE_BOTH_B
87 static const int32_t trigger_matches[] = {
95 static const uint64_t samplerates[] = {
131 static const uint64_t samplerates_hw[] = {
170 static struct sr_dev_driver hantek_4032l_driver_info;
172 static GSList *scan(struct sr_dev_driver *di, GSList *options)
174 struct drv_context *drvc = di->context;
175 GSList *l, *devices, *conn_devices;
176 libusb_device **devlist;
177 struct libusb_device_descriptor des;
180 char connection_id[64];
181 struct sr_channel_group *cg;
182 struct sr_dev_inst *sdi;
183 struct sr_channel *ch;
187 drvc->instances = NULL;
190 for (l = options; l; l = l->next) {
191 struct sr_config *src = l->data;
192 if (src->key == SR_CONF_CONN) {
193 conn = g_variant_get_string(src->data, NULL);
199 conn_devices = sr_usb_find(drvc->sr_ctx->libusb_ctx, conn);
203 libusb_get_device_list(drvc->sr_ctx->libusb_ctx, &devlist);
204 for (i = 0; devlist[i]; i++) {
206 struct sr_usb_dev_inst *usb = NULL;
207 for (l = conn_devices; l; l = l->next) {
209 if (usb->bus == libusb_get_bus_number(devlist[i]) &&
210 usb->address == libusb_get_device_address(devlist[i]))
214 /* This device matched none of the ones that
215 * matched the conn specification. */
219 libusb_get_device_descriptor(devlist[i], &des);
221 if (des.idVendor != H4032L_USB_VENDOR ||
222 des.idProduct != H4032L_USB_PRODUCT)
225 if (usb_get_port_path(devlist[i], connection_id, sizeof(connection_id)) < 0)
228 sdi = g_malloc0(sizeof(struct sr_dev_inst));
229 sdi->driver = &hantek_4032l_driver_info;
230 sdi->vendor = g_strdup("Hantek");
231 sdi->model = g_strdup("4032L");
232 sdi->connection_id = g_strdup(connection_id);
234 struct sr_channel_group *channel_groups[2];
235 for (int j = 0; j < 2; j++) {
236 cg = sr_channel_group_new(sdi, NULL, NULL);
237 cg->name = g_strdup_printf("%c", 'A' + j);
238 channel_groups[j] = cg;
241 /* Assemble channel list and add channel to channel groups. */
242 for (int j = 0; j < NUM_CHANNELS; j++) {
243 char channel_name[4];
244 sprintf(channel_name, "%c%d", 'A' + (j & 1), j / 2);
245 ch = sr_channel_new(sdi, j, SR_CHANNEL_LOGIC, TRUE, channel_name);
246 cg = channel_groups[j & 1];
247 cg->channels = g_slist_append(cg->channels, ch);
250 struct dev_context *devc = g_malloc0(sizeof(struct dev_context));
252 /* Initialize command packet. */
253 devc->cmd_pkt.magic = H4032L_CMD_PKT_MAGIC;
254 devc->cmd_pkt.sample_size = 16 * 1024;
255 devc->sample_rate = 0;
257 devc->status = H4032L_STATUS_IDLE;
259 devc->capture_ratio = 5;
260 devc->external_clock = FALSE;
261 devc->clock_edge = H4032L_CLOCK_EDGE_TYPE_RISE;
263 /* Create array of thresholds from min to max. */
264 GVariant *thresholds = std_gvar_min_max_step_thresholds(
265 H4032L_THR_VOLTAGE_MIN, H4032L_THR_VOLTAGE_MAX,
266 H4032L_THR_VOLTAGE_STEP);
267 /* Take default threshold value from array (FP workaround). */
268 g_variant_get_child(thresholds, H4032L_THR_VOLTAGE_DEFAULT,
269 "(dd)", &devc->cur_threshold[0], &devc->cur_threshold[1]);
272 devices = g_slist_append(devices, sdi);
274 sdi->status = SR_ST_INACTIVE;
275 sdi->inst_type = SR_INST_USB;
276 sdi->conn = sr_usb_dev_inst_new(
277 libusb_get_bus_number(devlist[i]),
278 libusb_get_device_address(devlist[i]), NULL);
281 g_slist_free_full(conn_devices, (GDestroyNotify)sr_usb_dev_inst_free);
282 libusb_free_device_list(devlist, 1);
284 return std_scan_complete(di, devices);
287 static int dev_open(struct sr_dev_inst *sdi)
289 struct sr_usb_dev_inst *usb = sdi->conn;
292 ret = h4032l_dev_open(sdi);
294 sr_err("Unable to open device.");
298 ret = libusb_claim_interface(usb->devhdl, USB_INTERFACE);
301 case LIBUSB_ERROR_BUSY:
302 sr_err("Unable to claim USB interface. Another "
303 "program or driver has already claimed it.");
305 case LIBUSB_ERROR_NO_DEVICE:
306 sr_err("Device has been disconnected.");
309 sr_err("Unable to claim interface: %s.",
310 libusb_error_name(ret));
317 /* Get FPGA version. */
318 if ((ret = h4032l_get_fpga_version(sdi)) != SR_OK)
324 static int dev_close(struct sr_dev_inst *sdi)
326 struct sr_usb_dev_inst *usb;
333 sr_info("Closing device on %d.%d (logical) / %s (physical) interface %d.",
334 usb->bus, usb->address, sdi->connection_id, USB_INTERFACE);
335 libusb_release_interface(usb->devhdl, USB_INTERFACE);
336 libusb_close(usb->devhdl);
342 static int config_get(uint32_t key, GVariant **data,
343 const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
345 struct dev_context *devc = sdi->priv;
346 struct sr_usb_dev_inst *usb;
350 case SR_CONF_VOLTAGE_THRESHOLD:
352 return SR_ERR_CHANNEL_GROUP;
353 if ((idx = std_str_idx_s(cg->name, ARRAY_AND_SIZE(cg_names))) < 0)
354 return SR_ERR_CHANNEL_GROUP;
355 *data = std_gvar_tuple_double(
356 devc->cur_threshold[idx], devc->cur_threshold[idx]);
358 case SR_CONF_SAMPLERATE:
359 *data = g_variant_new_uint64(samplerates_hw[devc->sample_rate]);
361 case SR_CONF_CAPTURE_RATIO:
362 *data = g_variant_new_uint64(devc->capture_ratio);
364 case SR_CONF_LIMIT_SAMPLES:
365 *data = g_variant_new_uint64(devc->cmd_pkt.sample_size);
367 case SR_CONF_EXTERNAL_CLOCK:
368 *data = g_variant_new_boolean(devc->external_clock);
370 case SR_CONF_EXTERNAL_CLOCK_SOURCE:
371 *data = g_variant_new_string(ext_clock_sources[devc->external_clock_source]);
374 if (!sdi || !(usb = sdi->conn))
376 *data = g_variant_new_printf("%d.%d", usb->bus, usb->address);
378 case SR_CONF_CLOCK_EDGE:
379 *data = g_variant_new_string(signal_edges[devc->clock_edge]);
388 static int config_set(uint32_t key, GVariant *data,
389 const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
392 struct dev_context *devc = sdi->priv;
393 struct h4032l_cmd_pkt *cmd_pkt = &devc->cmd_pkt;
394 uint64_t sample_rate, num_samples;
398 case SR_CONF_SAMPLERATE:
400 sample_rate = g_variant_get_uint64(data);
401 while (idx < (int)ARRAY_SIZE(samplerates_hw) && samplerates_hw[idx] != sample_rate)
403 if (idx == ARRAY_SIZE(samplerates_hw) || sample_rate == 0) {
404 sr_err("Invalid sample rate.");
405 return SR_ERR_SAMPLERATE;
407 devc->sample_rate = idx;
409 case SR_CONF_CAPTURE_RATIO:
410 devc->capture_ratio = g_variant_get_uint64(data);
412 case SR_CONF_LIMIT_SAMPLES:
413 num_samples = g_variant_get_uint64(data);
415 num_samples &= 0xfffffe00;
416 if (num_samples < H4043L_NUM_SAMPLES_MIN ||
417 num_samples > H4032L_NUM_SAMPLES_MAX) {
418 sr_err("Invalid sample range 2k...64M: %"
419 PRIu64 ".", num_samples);
422 cmd_pkt->sample_size = num_samples;
424 case SR_CONF_VOLTAGE_THRESHOLD:
426 return SR_ERR_CHANNEL_GROUP;
427 if ((idx = std_str_idx_s(cg->name, ARRAY_AND_SIZE(cg_names))) < 0)
428 return SR_ERR_CHANNEL_GROUP;
429 g_variant_get(data, "(dd)", &low, &high);
430 devc->cur_threshold[idx] = (low + high) / 2.0;
432 case SR_CONF_EXTERNAL_CLOCK:
433 devc->external_clock = g_variant_get_boolean(data);
435 case SR_CONF_EXTERNAL_CLOCK_SOURCE:
436 if ((idx = std_str_idx(data, ARRAY_AND_SIZE(ext_clock_sources))) < 0)
438 devc->external_clock_source = idx;
440 case SR_CONF_CLOCK_EDGE:
441 if ((idx = std_str_idx(data, ARRAY_AND_SIZE(signal_edges))) < 0)
443 devc->clock_edge = idx;
452 static int config_list(uint32_t key, GVariant **data,
453 const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
455 struct dev_context *devc = (sdi) ? sdi->priv : NULL;
458 case SR_CONF_SCAN_OPTIONS:
459 case SR_CONF_DEVICE_OPTIONS:
461 *data = std_gvar_array_u32(ARRAY_AND_SIZE(devopts_cg));
464 /* Disable external clock and edges for FPGA version 0. */
465 if (devc && (!devc->fpga_version))
466 return STD_CONFIG_LIST(key, data, sdi, cg, scanopts, drvopts, devopts_fpga_zero);
467 return STD_CONFIG_LIST(key, data, sdi, cg, scanopts, drvopts, devopts);
468 case SR_CONF_SAMPLERATE:
469 *data = std_gvar_samplerates(ARRAY_AND_SIZE(samplerates));
471 case SR_CONF_TRIGGER_MATCH:
472 *data = std_gvar_array_i32(ARRAY_AND_SIZE(trigger_matches));
474 case SR_CONF_VOLTAGE_THRESHOLD:
475 *data = std_gvar_min_max_step_thresholds(H4032L_THR_VOLTAGE_MIN,
476 H4032L_THR_VOLTAGE_MAX, H4032L_THR_VOLTAGE_STEP);
478 case SR_CONF_LIMIT_SAMPLES:
479 *data = std_gvar_tuple_u64(H4043L_NUM_SAMPLES_MIN, H4032L_NUM_SAMPLES_MAX);
481 case SR_CONF_CLOCK_EDGE:
482 *data = g_variant_new_strv(ARRAY_AND_SIZE(signal_edges));
484 case SR_CONF_EXTERNAL_CLOCK_SOURCE:
485 *data = g_variant_new_strv(ARRAY_AND_SIZE(ext_clock_sources));
494 static int dev_acquisition_start(const struct sr_dev_inst *sdi)
496 struct sr_dev_driver *di = sdi->driver;
497 struct drv_context *drvc = di->context;
498 struct dev_context *devc = sdi->priv;
499 struct sr_trigger *trigger = sr_session_trigger_get(sdi->session);
500 struct h4032l_cmd_pkt *cmd_pkt = &devc->cmd_pkt;
502 /* Initialize variables. */
503 devc->acq_aborted = FALSE;
504 devc->submitted_transfers = 0;
505 devc->sent_samples = 0;
507 /* Calculate packet ratio. */
508 cmd_pkt->pre_trigger_size = (cmd_pkt->sample_size * devc->capture_ratio) / 100;
509 devc->trigger_pos = cmd_pkt->pre_trigger_size;
511 /* Set clock edge, when external clock is enabled. */
512 if (devc->external_clock)
513 cmd_pkt->sample_rate = ext_clock_edges[devc->external_clock_source][devc->clock_edge];
515 cmd_pkt->sample_rate = devc->sample_rate;
517 /* Set PWM channel values. */
518 devc->cmd_pkt.pwm_a = h4032l_voltage2pwm(devc->cur_threshold[0]);
519 devc->cmd_pkt.pwm_b = h4032l_voltage2pwm(devc->cur_threshold[1]);
521 cmd_pkt->trig_flags.enable_trigger1 = 0;
522 cmd_pkt->trig_flags.enable_trigger2 = 0;
523 cmd_pkt->trig_flags.trigger_and_logic = 0;
525 if (trigger && trigger->stages) {
526 GSList *stages = trigger->stages;
527 struct sr_trigger_stage *stage1 = stages->data;
529 sr_err("Only one trigger stage supported for now.");
532 cmd_pkt->trig_flags.enable_trigger1 = 1;
533 cmd_pkt->trigger[0].flags.edge_type = H4032L_TRIGGER_EDGE_TYPE_DISABLED;
534 cmd_pkt->trigger[0].flags.data_range_enabled = 0;
535 cmd_pkt->trigger[0].flags.time_range_enabled = 0;
536 cmd_pkt->trigger[0].flags.combined_enabled = 0;
537 cmd_pkt->trigger[0].flags.data_range_type = H4032L_TRIGGER_DATA_RANGE_TYPE_MAX;
538 cmd_pkt->trigger[0].data_range_mask = 0;
539 cmd_pkt->trigger[0].data_range_max = 0;
541 /* Initialize range mask values. */
542 uint32_t range_mask = 0;
543 uint32_t range_value = 0;
545 GSList *channel = stage1->matches;
547 struct sr_trigger_match *match = channel->data;
549 switch (match->match) {
550 case SR_TRIGGER_ZERO:
551 range_mask |= (1 << match->channel->index);
554 range_mask |= (1 << match->channel->index);
555 range_value |= (1 << match->channel->index);
557 case SR_TRIGGER_RISING:
558 if (cmd_pkt->trigger[0].flags.edge_type != H4032L_TRIGGER_EDGE_TYPE_DISABLED) {
559 sr_err("Only one trigger signal with fall/rising/edge allowed.");
562 cmd_pkt->trigger[0].flags.edge_type = H4032L_TRIGGER_EDGE_TYPE_RISE;
563 cmd_pkt->trigger[0].flags.edge_signal = match->channel->index;
565 case SR_TRIGGER_FALLING:
566 if (cmd_pkt->trigger[0].flags.edge_type != H4032L_TRIGGER_EDGE_TYPE_DISABLED) {
567 sr_err("Only one trigger signal with fall/rising/edge allowed.");
570 cmd_pkt->trigger[0].flags.edge_type = H4032L_TRIGGER_EDGE_TYPE_FALL;
571 cmd_pkt->trigger[0].flags.edge_signal = match->channel->index;
573 case SR_TRIGGER_EDGE:
574 if (cmd_pkt->trigger[0].flags.edge_type != H4032L_TRIGGER_EDGE_TYPE_DISABLED) {
575 sr_err("Only one trigger signal with fall/rising/edge allowed.");
578 cmd_pkt->trigger[0].flags.edge_type = H4032L_TRIGGER_EDGE_TYPE_TOGGLE;
579 cmd_pkt->trigger[0].flags.edge_signal = match->channel->index;
582 sr_err("Unknown trigger value.");
586 channel = channel->next;
589 cmd_pkt->trigger[0].flags.data_range_enabled = 1;
590 cmd_pkt->trigger[0].data_range_mask |= range_mask;
591 cmd_pkt->trigger[0].data_range_max = range_value;
594 usb_source_add(sdi->session, drvc->sr_ctx, 1000,
595 h4032l_receive_data, sdi->driver->context);
597 /* Start capturing. */
598 return h4032l_start(sdi);
601 static int dev_acquisition_stop(struct sr_dev_inst *sdi)
603 /* Stop capturing. */
604 return h4032l_stop(sdi);
607 static struct sr_dev_driver hantek_4032l_driver_info = {
608 .name = "hantek-4032l",
609 .longname = "Hantek 4032L",
612 .cleanup = std_cleanup,
614 .dev_list = std_dev_list,
615 .dev_clear = std_dev_clear,
616 .config_get = config_get,
617 .config_set = config_set,
618 .config_list = config_list,
619 .dev_open = dev_open,
620 .dev_close = dev_close,
621 .dev_acquisition_start = dev_acquisition_start,
622 .dev_acquisition_stop = dev_acquisition_stop,
625 SR_REGISTER_DEV_DRIVER(hantek_4032l_driver_info);