src/hardware/hantek-4032l/api.c

   1 /*
   2  * This file is part of the libsigrok project.
   3  *
   4  * Copyright (C) 2016 Andreas Zschunke <andreas.zschunke@gmx.net>
   5  * Copyright (C) 2017 Andrej Valek <andy@skyrain.eu>
   6  * Copyright (C) 2017 Uwe Hermann <uwe@hermann-uwe.de>
   7  *
   8  * This program is free software: you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation, either version 3 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <config.h>
  23 #include "protocol.h"
  24
  25 #define USB_INTERFACE 0
  26 #define NUM_CHANNELS 32
  27
  28 static const uint32_t scanopts[] = {
  29         SR_CONF_CONN,
  30 };
  31
  32 static const uint32_t drvopts[] = {
  33         SR_CONF_LOGIC_ANALYZER,
  34 };
  35
  36 static const uint32_t devopts[] = {
  37         SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
  38         SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
  39         SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
  40         SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
  41         SR_CONF_CONN | SR_CONF_GET,
  42         SR_CONF_EXTERNAL_CLOCK | SR_CONF_GET | SR_CONF_SET,
  43         SR_CONF_EXTERNAL_CLOCK_SOURCE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
  44         SR_CONF_CLOCK_EDGE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
  45 };
  46
  47 static const uint32_t devopts_fpga_zero[] = {
  48         SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
  49         SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
  50         SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
  51         SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
  52         SR_CONF_CONN | SR_CONF_GET,
  53 };
  54
  55 static const uint32_t devopts_cg[] = {
  56         SR_CONF_VOLTAGE_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
  57 };
  58
  59 static const char *cg_names[] = {
  60         "A", "B",
  61 };
  62
  63 static const char *signal_edges[] = {
  64         [H4032L_CLOCK_EDGE_TYPE_RISE] = "rising",
  65         [H4032L_CLOCK_EDGE_TYPE_FALL] = "falling",
  66         [H4032L_CLOCK_EDGE_TYPE_BOTH] = "both",
  67 };
  68
  69 static const char *ext_clock_sources[] = {
  70         [H4032L_EXT_CLOCK_SOURCE_CHANNEL_A] = "ACLK",
  71         [H4032L_EXT_CLOCK_SOURCE_CHANNEL_B] = "BCLK"
  72 };
  73
  74 static const uint8_t ext_clock_edges[2][3] = {
  75         {
  76                 H4032L_CLOCK_EDGE_TYPE_RISE_A,
  77                 H4032L_CLOCK_EDGE_TYPE_FALL_A,
  78                 H4032L_CLOCK_EDGE_TYPE_BOTH_A
  79         },
  80         {
  81                 H4032L_CLOCK_EDGE_TYPE_RISE_B,
  82                 H4032L_CLOCK_EDGE_TYPE_FALL_B,
  83                 H4032L_CLOCK_EDGE_TYPE_BOTH_B
  84         }
  85 };
  86
  87 static const int32_t trigger_matches[] = {
  88         SR_TRIGGER_ZERO,
  89         SR_TRIGGER_ONE,
  90         SR_TRIGGER_RISING,
  91         SR_TRIGGER_FALLING,
  92         SR_TRIGGER_EDGE,
  93 };
  94
  95 static const uint64_t samplerates[] = {
  96         SR_KHZ(1),
  97         SR_KHZ(2),
  98         SR_KHZ(4),
  99         SR_KHZ(8),
 100         SR_KHZ(16),
 101         SR_HZ(31250),
 102         SR_HZ(62500),
 103         SR_KHZ(125),
 104         SR_KHZ(250),
 105         SR_KHZ(500),
 106         SR_KHZ(625),
 107         SR_HZ(781250),
 108         SR_MHZ(1),
 109         SR_KHZ(1250),
 110         SR_HZ(1562500),
 111         SR_MHZ(2),
 112         SR_KHZ(2500),
 113         SR_KHZ(3125),
 114         SR_MHZ(4),
 115         SR_MHZ(5),
 116         SR_KHZ(6250),
 117         SR_MHZ(10),
 118         SR_KHZ(12500),
 119         SR_MHZ(20),
 120         SR_MHZ(25),
 121         SR_MHZ(40),
 122         SR_MHZ(50),
 123         SR_MHZ(80),
 124         SR_MHZ(100),
 125         SR_MHZ(160),
 126         SR_MHZ(200),
 127         SR_MHZ(320),
 128         SR_MHZ(400),
 129 };
 130
 131 static const uint64_t samplerates_hw[] = {
 132         SR_MHZ(100),
 133         SR_MHZ(50),
 134         SR_MHZ(25),
 135         SR_KHZ(12500),
 136         SR_KHZ(6250),
 137         SR_KHZ(3125),
 138         SR_HZ(1562500),
 139         SR_HZ(781250),
 140         SR_MHZ(80),
 141         SR_MHZ(40),
 142         SR_MHZ(20),
 143         SR_MHZ(10),
 144         SR_MHZ(5),
 145         SR_KHZ(2500),
 146         SR_KHZ(1250),
 147         SR_KHZ(625),
 148         SR_MHZ(4),
 149         SR_MHZ(2),
 150         SR_MHZ(1),
 151         SR_KHZ(500),
 152         SR_KHZ(250),
 153         SR_KHZ(125),
 154         SR_HZ(62500),
 155         SR_HZ(31250),
 156         SR_KHZ(16),
 157         SR_KHZ(8),
 158         SR_KHZ(4),
 159         SR_KHZ(2),
 160         SR_KHZ(1),
 161         0,
 162         0,
 163         0,
 164         SR_MHZ(200),
 165         SR_MHZ(160),
 166         SR_MHZ(400),
 167         SR_MHZ(320),
 168 };
 169
 170 SR_PRIV struct sr_dev_driver hantek_4032l_driver_info;
 171
 172 static GSList *scan(struct sr_dev_driver *di, GSList *options)
 173 {
 174         struct drv_context *drvc = di->context;
 175         GSList *l, *devices, *conn_devices;
 176         libusb_device **devlist;
 177         struct libusb_device_descriptor des;
 178         const char *conn;
 179         int i;
 180         char connection_id[64];
 181         struct sr_channel_group *cg;
 182         struct sr_dev_inst *sdi;
 183         struct sr_channel *ch;
 184
 185         devices = NULL;
 186         conn_devices = NULL;
 187         drvc->instances = NULL;
 188         conn = NULL;
 189
 190         for (l = options; l; l = l->next) {
 191                 struct sr_config *src = l->data;
 192                 if (src->key == SR_CONF_CONN) {
 193                         conn = g_variant_get_string(src->data, NULL);
 194                         break;
 195                 }
 196         }
 197
 198         if (conn)
 199                 conn_devices = sr_usb_find(drvc->sr_ctx->libusb_ctx, conn);
 200         else
 201                 conn_devices = NULL;
 202
 203         libusb_get_device_list(drvc->sr_ctx->libusb_ctx, &devlist);
 204         for (i = 0; devlist[i]; i++) {
 205                 if (conn) {
 206                         struct sr_usb_dev_inst *usb = NULL;
 207                         for (l = conn_devices; l; l = l->next) {
 208                                 usb = l->data;
 209                                 if (usb->bus == libusb_get_bus_number(devlist[i]) &&
 210                                     usb->address == libusb_get_device_address(devlist[i]))
 211                                         break;
 212                         }
 213                         if (!l)
 214                                 /* This device matched none of the ones that
 215                                  * matched the conn specification. */
 216                                 continue;
 217                 }
 218
 219                 libusb_get_device_descriptor(devlist[i], &des);
 220
 221                 if (des.idVendor != H4032L_USB_VENDOR ||
 222                     des.idProduct != H4032L_USB_PRODUCT)
 223                         continue;
 224
 225                 if (usb_get_port_path(devlist[i], connection_id, sizeof(connection_id)) < 0)
 226                         continue;
 227
 228                 sdi = g_malloc0(sizeof(struct sr_dev_inst));
 229                 sdi->driver = &hantek_4032l_driver_info;
 230                 sdi->vendor = g_strdup("Hantek");
 231                 sdi->model = g_strdup("4032L");
 232                 sdi->connection_id = g_strdup(connection_id);
 233
 234                 struct sr_channel_group *channel_groups[2];
 235                 for (int j = 0; j < 2; j++) {
 236                         cg = g_malloc0(sizeof(struct sr_channel_group));
 237                         cg->name = g_strdup_printf("%c", 'A' + j);
 238                         channel_groups[j] = cg;
 239                         sdi->channel_groups = g_slist_append(sdi->channel_groups, cg);
 240                 }
 241
 242                 /* Assemble channel list and add channel to channel groups. */
 243                 for (int j = 0; j < NUM_CHANNELS; j++) {
 244                         char channel_name[4];
 245                         sprintf(channel_name, "%c%d", 'A' + (j & 1), j / 2);
 246                         ch = sr_channel_new(sdi, j, SR_CHANNEL_LOGIC, TRUE, channel_name);
 247                         cg = channel_groups[j & 1];
 248                         cg->channels = g_slist_append(cg->channels, ch);
 249                 }
 250
 251                 struct dev_context *devc = g_malloc0(sizeof(struct dev_context));
 252
 253                 /* Initialize command packet. */
 254                 devc->cmd_pkt.magic = H4032L_CMD_PKT_MAGIC;
 255                 devc->cmd_pkt.sample_size = 16 * 1024;
 256                 devc->sample_rate = 0;
 257
 258                 devc->status = H4032L_STATUS_IDLE;
 259
 260                 devc->capture_ratio = 5;
 261                 devc->external_clock = FALSE;
 262                 devc->clock_edge = H4032L_CLOCK_EDGE_TYPE_RISE;
 263
 264                 devc->cur_threshold[0] = 2.5;
 265                 devc->cur_threshold[1] = 2.5;
 266
 267                 sdi->priv = devc;
 268                 devices = g_slist_append(devices, sdi);
 269
 270                 sdi->status = SR_ST_INACTIVE;
 271                 sdi->inst_type = SR_INST_USB;
 272                 sdi->conn = sr_usb_dev_inst_new(
 273                         libusb_get_bus_number(devlist[i]),
 274                         libusb_get_device_address(devlist[i]), NULL);
 275         }
 276
 277         g_slist_free_full(conn_devices, (GDestroyNotify)sr_usb_dev_inst_free);
 278         libusb_free_device_list(devlist, 1);
 279
 280         return std_scan_complete(di, devices);
 281 }
 282
 283 static int dev_open(struct sr_dev_inst *sdi)
 284 {
 285         struct sr_usb_dev_inst *usb = sdi->conn;
 286         int ret;
 287
 288         ret = h4032l_dev_open(sdi);
 289         if (ret != SR_OK) {
 290                 sr_err("Unable to open device.");
 291                 return SR_ERR;
 292         }
 293
 294         ret = libusb_claim_interface(usb->devhdl, USB_INTERFACE);
 295         if (ret != 0) {
 296                 switch (ret) {
 297                 case LIBUSB_ERROR_BUSY:
 298                         sr_err("Unable to claim USB interface. Another "
 299                                "program or driver has already claimed it.");
 300                         break;
 301                 case LIBUSB_ERROR_NO_DEVICE:
 302                         sr_err("Device has been disconnected.");
 303                         break;
 304                 default:
 305                         sr_err("Unable to claim interface: %s.",
 306                                libusb_error_name(ret));
 307                         break;
 308                 }
 309
 310                 return SR_ERR;
 311         }
 312
 313         /* Get FPGA version. */
 314         if ((ret = h4032l_get_fpga_version(sdi)) != SR_OK)
 315                 return ret;
 316
 317         return SR_OK;
 318 }
 319
 320 static int dev_close(struct sr_dev_inst *sdi)
 321 {
 322         struct sr_usb_dev_inst *usb;
 323
 324         usb = sdi->conn;
 325
 326         if (!usb->devhdl)
 327                 return SR_ERR_BUG;
 328
 329         sr_info("Closing device on %d.%d (logical) / %s (physical) interface %d.",
 330                 usb->bus, usb->address, sdi->connection_id, USB_INTERFACE);
 331         libusb_release_interface(usb->devhdl, USB_INTERFACE);
 332         libusb_close(usb->devhdl);
 333         usb->devhdl = NULL;
 334
 335         return SR_OK;
 336 }
 337
 338 static int config_get(uint32_t key, GVariant **data,
 339         const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
 340 {
 341         struct dev_context *devc = sdi->priv;
 342         struct sr_usb_dev_inst *usb;
 343         int idx;
 344
 345         switch (key) {
 346         case SR_CONF_VOLTAGE_THRESHOLD:
 347                 if (!cg)
 348                         return SR_ERR_CHANNEL_GROUP;
 349                 if ((idx = std_str_idx_s(cg->name, ARRAY_AND_SIZE(cg_names))) < 0)
 350                         return SR_ERR_CHANNEL_GROUP;
 351                 *data = std_gvar_tuple_double(
 352                         devc->cur_threshold[idx], devc->cur_threshold[idx]);
 353                 break;
 354         case SR_CONF_SAMPLERATE:
 355                 *data = g_variant_new_uint64(samplerates_hw[devc->sample_rate]);
 356                 break;
 357         case SR_CONF_CAPTURE_RATIO:
 358                 *data = g_variant_new_uint64(devc->capture_ratio);
 359                 break;
 360         case SR_CONF_LIMIT_SAMPLES:
 361                 *data = g_variant_new_uint64(devc->cmd_pkt.sample_size);
 362                 break;
 363         case SR_CONF_EXTERNAL_CLOCK:
 364                 *data = g_variant_new_boolean(devc->external_clock);
 365                 break;
 366         case SR_CONF_EXTERNAL_CLOCK_SOURCE:
 367                 *data = g_variant_new_string(ext_clock_sources[devc->external_clock_source]);
 368                 break;
 369         case SR_CONF_CONN:
 370                 if (!sdi || !(usb = sdi->conn))
 371                         return SR_ERR_ARG;
 372                 *data = g_variant_new_printf("%d.%d", usb->bus, usb->address);
 373                 break;
 374         case SR_CONF_CLOCK_EDGE:
 375                 *data = g_variant_new_string(signal_edges[devc->clock_edge]);
 376                 break;
 377         default:
 378                 return SR_ERR_NA;
 379         }
 380
 381         return SR_OK;
 382 }
 383
 384 static int config_set(uint32_t key, GVariant *data,
 385         const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
 386 {
 387         int idx;
 388         struct dev_context *devc = sdi->priv;
 389         struct h4032l_cmd_pkt *cmd_pkt = &devc->cmd_pkt;
 390         uint64_t sample_rate, num_samples;
 391         double low, high;
 392
 393         switch (key) {
 394         case SR_CONF_SAMPLERATE:
 395                 idx = 0;
 396                 sample_rate = g_variant_get_uint64(data);
 397                 while (idx < (int)ARRAY_SIZE(samplerates_hw) && samplerates_hw[idx] != sample_rate)
 398                         idx++;
 399                 if (idx == ARRAY_SIZE(samplerates_hw) || sample_rate == 0) {
 400                         sr_err("Invalid sample rate.");
 401                         return SR_ERR_SAMPLERATE;
 402                 }
 403                 devc->sample_rate = idx;
 404                 break;
 405         case SR_CONF_CAPTURE_RATIO:
 406                 devc->capture_ratio = g_variant_get_uint64(data);
 407                 break;
 408         case SR_CONF_LIMIT_SAMPLES:
 409                 num_samples = g_variant_get_uint64(data);
 410                 num_samples += 511;
 411                 num_samples &= 0xfffffe00;
 412                 if (num_samples < H4043L_NUM_SAMPLES_MIN ||
 413                     num_samples > H4032L_NUM_SAMPLES_MAX) {
 414                         sr_err("Invalid sample range 2k...64M: %"
 415                                PRIu64 ".", num_samples);
 416                         return SR_ERR;
 417                 }
 418                 cmd_pkt->sample_size = num_samples;
 419                 break;
 420         case SR_CONF_VOLTAGE_THRESHOLD:
 421                 if (!cg)
 422                         return SR_ERR_CHANNEL_GROUP;
 423                 if ((idx = std_str_idx_s(cg->name, ARRAY_AND_SIZE(cg_names))) < 0)
 424                         return SR_ERR_CHANNEL_GROUP;
 425                 g_variant_get(data, "(dd)", &low, &high);
 426                 devc->cur_threshold[idx] = (low + high) / 2.0;
 427                 break;
 428         case SR_CONF_EXTERNAL_CLOCK:
 429                 devc->external_clock = g_variant_get_boolean(data);
 430                 break;
 431         case SR_CONF_EXTERNAL_CLOCK_SOURCE:
 432                 if ((idx = std_str_idx(data, ARRAY_AND_SIZE(ext_clock_sources))) < 0)
 433                         return SR_ERR_ARG;
 434                 devc->external_clock_source = idx;
 435                 break;
 436         case SR_CONF_CLOCK_EDGE:
 437                 if ((idx = std_str_idx(data, ARRAY_AND_SIZE(signal_edges))) < 0)
 438                         return SR_ERR_ARG;
 439                 devc->clock_edge = idx;
 440                 break;
 441         default:
 442                 return SR_ERR_NA;
 443         }
 444
 445         return SR_OK;
 446 }
 447
 448 static int config_list(uint32_t key, GVariant **data,
 449         const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
 450 {
 451         struct dev_context *devc = (sdi) ? sdi->priv : NULL;
 452
 453         switch (key) {
 454         case SR_CONF_SCAN_OPTIONS:
 455         case SR_CONF_DEVICE_OPTIONS:
 456                 if (cg) {
 457                         *data = std_gvar_array_u32(ARRAY_AND_SIZE(devopts_cg));
 458                         break;
 459                 }
 460                 /* Disable external clock and edges for FPGA version 0. */
 461                 if (devc && (!devc->fpga_version))
 462                         return STD_CONFIG_LIST(key, data, sdi, cg, scanopts, drvopts, devopts_fpga_zero);
 463                 return STD_CONFIG_LIST(key, data, sdi, cg, scanopts, drvopts, devopts);
 464         case SR_CONF_SAMPLERATE:
 465                 *data = std_gvar_samplerates(ARRAY_AND_SIZE(samplerates));
 466                 break;
 467         case SR_CONF_TRIGGER_MATCH:
 468                 *data = std_gvar_array_i32(ARRAY_AND_SIZE(trigger_matches));
 469                 break;
 470         case SR_CONF_VOLTAGE_THRESHOLD:
 471                 *data = std_gvar_min_max_step_thresholds(-6.0, 6.0, 0.1);
 472                 break;
 473         case SR_CONF_LIMIT_SAMPLES:
 474                 *data = std_gvar_tuple_u64(H4043L_NUM_SAMPLES_MIN, H4032L_NUM_SAMPLES_MAX);
 475                 break;
 476         case SR_CONF_CLOCK_EDGE:
 477                 *data = g_variant_new_strv(ARRAY_AND_SIZE(signal_edges));
 478                 break;
 479         case SR_CONF_EXTERNAL_CLOCK_SOURCE:
 480                 *data = g_variant_new_strv(ARRAY_AND_SIZE(ext_clock_sources));
 481                 break;
 482         default:
 483                 return SR_ERR_NA;
 484         }
 485
 486         return SR_OK;
 487 }
 488
 489 static int dev_acquisition_start(const struct sr_dev_inst *sdi)
 490 {
 491         struct sr_dev_driver *di = sdi->driver;
 492         struct drv_context *drvc = di->context;
 493         struct dev_context *devc = sdi->priv;
 494         struct sr_trigger *trigger = sr_session_trigger_get(sdi->session);
 495         struct h4032l_cmd_pkt *cmd_pkt = &devc->cmd_pkt;
 496
 497         /* Initialize variables. */
 498         devc->acq_aborted = FALSE;
 499         devc->submitted_transfers = 0;
 500         devc->sent_samples = 0;
 501
 502         /* Calculate packet ratio. */
 503         cmd_pkt->pre_trigger_size = (cmd_pkt->sample_size * devc->capture_ratio) / 100;
 504         devc->trigger_pos = cmd_pkt->pre_trigger_size;
 505
 506         /* Set clock edge, when external clock is enabled. */
 507         if (devc->external_clock)
 508                 cmd_pkt->sample_rate = ext_clock_edges[devc->external_clock_source][devc->clock_edge];
 509         else
 510                 cmd_pkt->sample_rate = devc->sample_rate;
 511
 512         /* Set pwm channel values. */
 513         devc->cmd_pkt.pwm_a = h4032l_voltage2pwm(devc->cur_threshold[0]);
 514         devc->cmd_pkt.pwm_b = h4032l_voltage2pwm(devc->cur_threshold[1]);
 515
 516         cmd_pkt->trig_flags.enable_trigger1 = 0;
 517         cmd_pkt->trig_flags.enable_trigger2 = 0;
 518         cmd_pkt->trig_flags.trigger_and_logic = 0;
 519
 520         if (trigger && trigger->stages) {
 521                 GSList *stages = trigger->stages;
 522                 struct sr_trigger_stage *stage1 = stages->data;
 523                 if (stages->next) {
 524                         sr_err("Only one trigger stage supported for now.");
 525                         return SR_ERR;
 526                 }
 527                 cmd_pkt->trig_flags.enable_trigger1 = 1;
 528                 cmd_pkt->trigger[0].flags.edge_type = H4032L_TRIGGER_EDGE_TYPE_DISABLED;
 529                 cmd_pkt->trigger[0].flags.data_range_enabled = 0;
 530                 cmd_pkt->trigger[0].flags.time_range_enabled = 0;
 531                 cmd_pkt->trigger[0].flags.combined_enabled = 0;
 532                 cmd_pkt->trigger[0].flags.data_range_type = H4032L_TRIGGER_DATA_RANGE_TYPE_MAX;
 533                 cmd_pkt->trigger[0].data_range_mask = 0;
 534                 cmd_pkt->trigger[0].data_range_max = 0;
 535
 536                 /* Initialize range mask values. */
 537                 uint32_t range_mask = 0;
 538                 uint32_t range_value = 0;
 539
 540                 GSList *channel = stage1->matches;
 541                 while (channel) {
 542                         struct sr_trigger_match *match = channel->data;
 543
 544                         switch (match->match) {
 545                         case SR_TRIGGER_ZERO:
 546                                 range_mask |= (1 << match->channel->index);
 547                                 break;
 548                         case SR_TRIGGER_ONE:
 549                                 range_mask |= (1 << match->channel->index);
 550                                 range_value |= (1 << match->channel->index);
 551                                 break;
 552                         case SR_TRIGGER_RISING:
 553                                 if (cmd_pkt->trigger[0].flags.edge_type != H4032L_TRIGGER_EDGE_TYPE_DISABLED) {
 554                                         sr_err("Only one trigger signal with fall/rising/edge allowed.");
 555                                         return SR_ERR;
 556                                 }
 557                                 cmd_pkt->trigger[0].flags.edge_type = H4032L_TRIGGER_EDGE_TYPE_RISE;
 558                                 cmd_pkt->trigger[0].flags.edge_signal = match->channel->index;
 559                                 break;
 560                         case SR_TRIGGER_FALLING:
 561                                 if (cmd_pkt->trigger[0].flags.edge_type != H4032L_TRIGGER_EDGE_TYPE_DISABLED) {
 562                                         sr_err("Only one trigger signal with fall/rising/edge allowed.");
 563                                         return SR_ERR;
 564                                 }
 565                                 cmd_pkt->trigger[0].flags.edge_type = H4032L_TRIGGER_EDGE_TYPE_FALL;
 566                                 cmd_pkt->trigger[0].flags.edge_signal = match->channel->index;
 567                                 break;
 568                         case SR_TRIGGER_EDGE:
 569                                 if (cmd_pkt->trigger[0].flags.edge_type != H4032L_TRIGGER_EDGE_TYPE_DISABLED) {
 570                                         sr_err("Only one trigger signal with fall/rising/edge allowed.");
 571                                         return SR_ERR;
 572                                 }
 573                                 cmd_pkt->trigger[0].flags.edge_type = H4032L_TRIGGER_EDGE_TYPE_TOGGLE;
 574                                 cmd_pkt->trigger[0].flags.edge_signal = match->channel->index;
 575                                 break;
 576                         default:
 577                                 sr_err("Unknown trigger value.");
 578                                 return SR_ERR;
 579                         }
 580
 581                         channel = channel->next;
 582                 }
 583
 584                 /* Compress range mask value and apply range settings. */
 585                 if (range_mask) {
 586                         cmd_pkt->trigger[0].flags.data_range_enabled = 1;
 587                         cmd_pkt->trigger[0].data_range_mask |= (range_mask);
 588
 589                         uint32_t new_range_value = 0;
 590                         uint32_t bit_mask = 1;
 591                         while (range_mask) {
 592                                 if ((range_mask & 1) != 0) {
 593                                         new_range_value <<= 1;
 594                                         if ((range_value & 1) != 0)
 595                                                 new_range_value |= bit_mask;
 596                                         bit_mask <<= 1;
 597                                 }
 598                                 range_mask >>= 1;
 599                                 range_value >>= 1;
 600                         }
 601                         cmd_pkt->trigger[0].data_range_max |= range_value;
 602                 }
 603         }
 604
 605         usb_source_add(sdi->session, drvc->sr_ctx, 1000,
 606                 h4032l_receive_data, sdi->driver->context);
 607
 608         /* Start capturing. */
 609         return h4032l_start(sdi);
 610 }
 611
 612 static int dev_acquisition_stop(struct sr_dev_inst *sdi)
 613 {
 614         /* Stop capturing. */
 615         return h4032l_stop(sdi);
 616 }
 617
 618 SR_PRIV struct sr_dev_driver hantek_4032l_driver_info = {
 619         .name = "hantek-4032l",
 620         .longname = "Hantek 4032L",
 621         .api_version = 1,
 622         .init = std_init,
 623         .cleanup = std_cleanup,
 624         .scan = scan,
 625         .dev_list = std_dev_list,
 626         .dev_clear = std_dev_clear,
 627         .config_get = config_get,
 628         .config_set = config_set,
 629         .config_list = config_list,
 630         .dev_open = dev_open,
 631         .dev_close = dev_close,
 632         .dev_acquisition_start = dev_acquisition_start,
 633         .dev_acquisition_stop = dev_acquisition_stop,
 634         .context = NULL,
 635 };
 636 SR_REGISTER_DEV_DRIVER(hantek_4032l_driver_info);