src/hardware/fx2lafw/dslogic.c

   1 /*
   2  * This file is part of the libsigrok project.
   3  *
   4  * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
   5  * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
   6  *
   7  * This program is free software: you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation, either version 3 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include <config.h>
  22 #include <math.h>
  23 #include <glib.h>
  24 #include <glib/gstdio.h>
  25 #include "protocol.h"
  26 #include "dslogic.h"
  27
  28 /*
  29  * This should be larger than the FPGA bitstream image so that it'll get
  30  * uploaded in one big operation. There seem to be issues when uploading
  31  * it in chunks.
  32  */
  33 #define FW_BUFSIZE (1024 * 1024)
  34
  35 #define FPGA_UPLOAD_DELAY (10 * 1000)
  36
  37 #define USB_TIMEOUT (3 * 1000)
  38
  39 SR_PRIV int dslogic_set_vth(const struct sr_dev_inst *sdi, double vth)
  40 {
  41         struct sr_usb_dev_inst *usb;
  42         usb = sdi->conn;
  43         int ret;
  44         uint8_t cmd;
  45
  46         cmd = vth/5.0 * 255;
  47         /* Send the control command. */
  48         ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
  49         LIBUSB_ENDPOINT_OUT, DS_CMD_VTH, 0x0000, 0x0000,
  50                 (unsigned char *)&cmd, sizeof(cmd), 3000);
  51         if (ret < 0) {
  52                 sr_err("Unable to send VTH command: %s.",
  53                 libusb_error_name(ret));
  54                 return SR_ERR;
  55         }
  56
  57         return SR_OK;
  58 }
  59
  60 SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
  61                 const char *name)
  62 {
  63         uint64_t sum;
  64         struct sr_resource bitstream;
  65         struct drv_context *drvc;
  66         struct sr_usb_dev_inst *usb;
  67         unsigned char *buf;
  68         ssize_t chunksize;
  69         int transferred;
  70         int result, ret;
  71         uint8_t cmd[3];
  72
  73         drvc = sdi->driver->context;
  74         usb = sdi->conn;
  75
  76         sr_dbg("Uploading FPGA firmware '%s'.", name);
  77
  78         result = sr_resource_open(drvc->sr_ctx, &bitstream,
  79                         SR_RESOURCE_FIRMWARE, name);
  80         if (result != SR_OK)
  81                 return result;
  82
  83         /* Tell the device firmware is coming. */
  84         memset(cmd, 0, sizeof(cmd));
  85         if ((ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
  86                         LIBUSB_ENDPOINT_OUT, DS_CMD_FPGA_FW, 0x0000, 0x0000,
  87                         (unsigned char *)&cmd, sizeof(cmd), USB_TIMEOUT)) < 0) {
  88                 sr_err("Failed to upload FPGA firmware: %s.", libusb_error_name(ret));
  89                 sr_resource_close(drvc->sr_ctx, &bitstream);
  90                 return SR_ERR;
  91         }
  92
  93         /* Give the FX2 time to get ready for FPGA firmware upload. */
  94         g_usleep(FPGA_UPLOAD_DELAY);
  95
  96         buf = g_malloc(FW_BUFSIZE);
  97         sum = 0;
  98         result = SR_OK;
  99         while (1) {
 100                 chunksize = sr_resource_read(drvc->sr_ctx, &bitstream,
 101                                 buf, FW_BUFSIZE);
 102                 if (chunksize < 0)
 103                         result = SR_ERR;
 104                 if (chunksize <= 0)
 105                         break;
 106
 107                 if ((ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
 108                                 buf, chunksize, &transferred, USB_TIMEOUT)) < 0) {
 109                         sr_err("Unable to configure FPGA firmware: %s.",
 110                                         libusb_error_name(ret));
 111                         result = SR_ERR;
 112                         break;
 113                 }
 114                 sum += transferred;
 115                 sr_spew("Uploaded %" PRIu64 "/%" PRIu64 " bytes.",
 116                         sum, bitstream.size);
 117
 118                 if (transferred != chunksize) {
 119                         sr_err("Short transfer while uploading FPGA firmware.");
 120                         result = SR_ERR;
 121                         break;
 122                 }
 123         }
 124         g_free(buf);
 125         sr_resource_close(drvc->sr_ctx, &bitstream);
 126
 127         if (result == SR_OK)
 128                 sr_dbg("FPGA firmware upload done.");
 129
 130         return result;
 131 }
 132
 133 SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi)
 134 {
 135         struct dev_context *devc;
 136         struct sr_usb_dev_inst *usb;
 137         struct dslogic_mode mode;
 138         int ret;
 139
 140         devc = sdi->priv;
 141         mode.flags = DS_START_FLAGS_MODE_LA;
 142         mode.sample_delay_h = mode.sample_delay_l = 0;
 143         if (devc->sample_wide)
 144                 mode.flags |= DS_START_FLAGS_SAMPLE_WIDE;
 145
 146         usb = sdi->conn;
 147         ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
 148                         LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
 149                         (unsigned char *)&mode, sizeof(mode), USB_TIMEOUT);
 150         if (ret < 0) {
 151                 sr_err("Failed to send start command: %s.", libusb_error_name(ret));
 152                 return SR_ERR;
 153         }
 154
 155         return SR_OK;
 156 }
 157
 158 SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi)
 159 {
 160         struct sr_usb_dev_inst *usb;
 161         struct dslogic_mode mode;
 162         int ret;
 163
 164         mode.flags = DS_START_FLAGS_STOP;
 165         mode.sample_delay_h = mode.sample_delay_l = 0;
 166
 167         usb = sdi->conn;
 168         ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
 169                         LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
 170                         (unsigned char *)&mode, sizeof(struct dslogic_mode), USB_TIMEOUT);
 171         if (ret < 0) {
 172                 sr_err("Failed to send stop command: %s.", libusb_error_name(ret));
 173                 return SR_ERR;
 174         }
 175
 176         return SR_OK;
 177 }
 178
 179 /*
 180  * Get the session trigger and configure the FPGA structure
 181  * accordingly.
 182  */
 183 static int dslogic_set_trigger(const struct sr_dev_inst *sdi,
 184         struct dslogic_fpga_config *cfg)
 185 {
 186         struct sr_trigger *trigger;
 187         struct sr_trigger_stage *stage;
 188         struct sr_trigger_match *match;
 189
 190         struct dev_context *devc;
 191         devc = sdi->priv;
 192         const GSList *l, *m;
 193         int channelbit, i = 0;
 194         uint16_t v16;
 195
 196         cfg->trig_mask0[0] = 0xffff;
 197         cfg->trig_mask1[0] = 0xffff;
 198
 199         cfg->trig_value0[0] = 0;
 200         cfg->trig_value1[0] = 0;
 201
 202         cfg->trig_edge0[0] = 0;
 203         cfg->trig_edge1[0] = 0;
 204
 205         cfg->trig_logic0[0] = 0;
 206         cfg->trig_logic1[0] = 0;
 207
 208         cfg->trig_count0[0] = 0;
 209         cfg->trig_count1[0] = 0;
 210
 211         cfg->trig_pos = 0;
 212         cfg->trig_sda = 0;
 213         cfg->trig_glb = 0;
 214         cfg->trig_adp = cfg->count - cfg->trig_pos - 1;
 215
 216         for (i = 1; i < 16; i++) {
 217                 cfg->trig_mask0[i] = 0xff;
 218                 cfg->trig_mask1[i] = 0xff;
 219                 cfg->trig_value0[i] = 0;
 220                 cfg->trig_value1[i] = 0;
 221                 cfg->trig_edge0[i] = 0;
 222                 cfg->trig_edge1[i] = 0;
 223                 cfg->trig_count0[i] = 0;
 224                 cfg->trig_count1[i] = 0;
 225                 cfg->trig_logic0[i] = 2;
 226                 cfg->trig_logic1[i] = 2;
 227         }
 228
 229         cfg->trig_pos = (uint32_t)(devc->capture_ratio / 100.0 * devc->limit_samples);
 230         sr_dbg("pos: %d", cfg->trig_pos);
 231
 232         sr_dbg("configuring trigger");
 233
 234         if (!(trigger = sr_session_trigger_get(sdi->session))){
 235                 sr_dbg("No session trigger found");
 236                 return SR_OK;
 237         }
 238
 239         for (l = trigger->stages; l; l = l->next) {
 240                 stage = l->data;
 241                 for (m = stage->matches; m; m = m->next) {
 242                         match = m->data;
 243                         if (!match->channel->enabled)
 244                                 /* Ignore disabled channels with a trigger. */
 245                                 continue;
 246                         channelbit = 1 << (match->channel->index);
 247                         /* Simple trigger support (event). */
 248                         if (match->match == SR_TRIGGER_ONE) {
 249                                 cfg->trig_mask0[0] &= ~channelbit;
 250                                 cfg->trig_mask1[0] &= ~channelbit;
 251                                 cfg->trig_value0[0] |= channelbit;
 252                                 cfg->trig_value1[0] |= channelbit;
 253                         } else if (match->match == SR_TRIGGER_ZERO) {
 254                                 cfg->trig_mask0[0] &= ~channelbit;
 255                                 cfg->trig_mask1[0] &= ~channelbit;
 256                         } else if (match->match == SR_TRIGGER_FALLING) {
 257                                 cfg->trig_mask0[0] &= ~channelbit;
 258                                 cfg->trig_mask1[0] &= ~channelbit;
 259                                 cfg->trig_edge0[0] |= channelbit;
 260                                 cfg->trig_edge1[0] |= channelbit;
 261                         } else if (match->match == SR_TRIGGER_RISING) {
 262                                 cfg->trig_mask0[0] &= ~channelbit;
 263                                 cfg->trig_mask1[0] &= ~channelbit;
 264                                 cfg->trig_value0[0] |= channelbit;
 265                                 cfg->trig_value1[0] |= channelbit;
 266                                 cfg->trig_edge0[0] |= channelbit;
 267                                 cfg->trig_edge1[0] |= channelbit;
 268                         } else if(match->match == SR_TRIGGER_EDGE){
 269                                 cfg->trig_edge0[0] |= channelbit;
 270                                 cfg->trig_edge1[0] |= channelbit;
 271                         }
 272                 }
 273         }
 274         v16 = RL16(&cfg->mode);
 275         v16 |= 1 << 0;
 276         WL16(&cfg->mode, v16);
 277         return SR_OK;
 278 }
 279
 280
 281 SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
 282 {
 283         struct dev_context *devc;
 284         struct sr_usb_dev_inst *usb;
 285         uint8_t c[3];
 286         struct dslogic_fpga_config cfg;
 287         uint16_t v16;
 288         uint32_t v32;
 289         int transferred, len, ret;
 290
 291         sr_dbg("Configuring FPGA.");
 292         usb = sdi->conn;
 293         devc = sdi->priv;
 294
 295         WL32(&cfg.sync, DS_CFG_START);
 296         WL16(&cfg.mode_header, DS_CFG_MODE);
 297         WL32(&cfg.divider_header, DS_CFG_DIVIDER);
 298         WL32(&cfg.count_header, DS_CFG_COUNT);
 299         WL32(&cfg.trig_pos_header, DS_CFG_TRIG_POS);
 300         WL16(&cfg.trig_glb_header, DS_CFG_TRIG_GLB);
 301         WL32(&cfg.trig_adp_header, DS_CFG_TRIG_ADP);
 302         WL32(&cfg.trig_sda_header, DS_CFG_TRIG_SDA);
 303         WL32(&cfg.trig_mask0_header, DS_CFG_TRIG_MASK0);
 304         WL32(&cfg.trig_mask1_header, DS_CFG_TRIG_MASK1);
 305         WL32(&cfg.trig_value0_header, DS_CFG_TRIG_VALUE0);
 306         WL32(&cfg.trig_value1_header, DS_CFG_TRIG_VALUE1);
 307         WL32(&cfg.trig_edge0_header, DS_CFG_TRIG_EDGE0);
 308         WL32(&cfg.trig_edge1_header, DS_CFG_TRIG_EDGE1);
 309         WL32(&cfg.trig_count0_header, DS_CFG_TRIG_COUNT0);
 310         WL32(&cfg.trig_count1_header, DS_CFG_TRIG_COUNT1);
 311         WL32(&cfg.trig_logic0_header, DS_CFG_TRIG_LOGIC0);
 312         WL32(&cfg.trig_logic1_header, DS_CFG_TRIG_LOGIC1);
 313         WL32(&cfg.end_sync, DS_CFG_END);
 314
 315         /* Pass in the length of a fixed-size struct. Really. */
 316         len = sizeof(struct dslogic_fpga_config) / 2;
 317         c[0] = len & 0xff;
 318         c[1] = (len >> 8) & 0xff;
 319         c[2] = (len >> 16) & 0xff;
 320
 321         ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
 322                         LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000,
 323                         c, 3, USB_TIMEOUT);
 324         if (ret < 0) {
 325                 sr_err("Failed to send FPGA configure command: %s.", libusb_error_name(ret));
 326                 return SR_ERR;
 327         }
 328
 329         /*
 330          * 15   1 = internal test mode
 331          * 14   1 = external test mode
 332          * 13   1 = loopback test mode
 333          * 12   1 = stream mode
 334          * 11   1 = serial trigger
 335          * 8-10 unused
 336          * 7    1 = analog mode
 337          * 6    1 = samplerate 400MHz
 338          * 5    1 = samplerate 200MHz or analog mode
 339          * 4    0 = logic, 1 = dso or analog
 340          * 3    unused
 341          * 1-2  00 = internal clock,
 342          *              01 = external clock rising,
 343          *              11 = external clock falling
 344          * 0    1 = trigger enabled
 345          */
 346         v16 = 0x0000;
 347         if (devc->dslogic_mode == DS_OP_INTERNAL_TEST)
 348                 v16 = 1 << 15;
 349         else if (devc->dslogic_mode == DS_OP_EXTERNAL_TEST)
 350                 v16 = 1 << 14;
 351         else if (devc->dslogic_mode == DS_OP_LOOPBACK_TEST)
 352                 v16 = 1 << 13;
 353         if (devc->dslogic_continuous_mode)
 354                 v16 |= 1 << 12;
 355         if (devc->dslogic_external_clock){
 356                 v16 |= 1 << 1;
 357                 if (devc->dslogic_clock_edge == DS_EDGE_FALLING){
 358                         v16 |= 1 << 2;
 359                 }
 360         }
 361
 362         WL16(&cfg.mode, v16);
 363         v32 = ceil(SR_MHZ(100) * 1.0 / devc->cur_samplerate);
 364         WL32(&cfg.divider, v32);
 365         WL32(&cfg.count, devc->limit_samples);
 366
 367         dslogic_set_trigger(sdi, &cfg);
 368
 369         len = sizeof(struct dslogic_fpga_config);
 370         ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
 371                         (unsigned char *)&cfg, len, &transferred, USB_TIMEOUT);
 372         if (ret < 0 || transferred != len) {
 373                 sr_err("Failed to send FPGA configuration: %s.", libusb_error_name(ret));
 374                 return SR_ERR;
 375         }
 376
 377         return SR_OK;
 378 }