src/hardware/fx2lafw/dslogic.c

   1 /*
   2  * This file is part of the libsigrok project.
   3  *
   4  * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
   5  * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
   6  *
   7  * This program is free software: you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation, either version 3 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include <config.h>
  22 #include <math.h>
  23 #include <glib.h>
  24 #include <glib/gstdio.h>
  25 #include "protocol.h"
  26 #include "dslogic.h"
  27
  28 /*
  29  * This should be larger than the FPGA bitstream image so that it'll get
  30  * uploaded in one big operation. There seem to be issues when uploading
  31  * it in chunks.
  32  */
  33 #define FW_BUFSIZE (1024 * 1024)
  34
  35 #define FPGA_UPLOAD_DELAY (10 * 1000)
  36
  37 #define USB_TIMEOUT (3 * 1000)
  38
  39 SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
  40                 const char *name)
  41 {
  42         uint64_t sum;
  43         struct sr_resource bitstream;
  44         struct drv_context *drvc;
  45         struct sr_usb_dev_inst *usb;
  46         unsigned char *buf;
  47         ssize_t chunksize;
  48         int transferred;
  49         int result, ret;
  50         uint8_t cmd[3];
  51
  52         drvc = sdi->driver->context;
  53         usb = sdi->conn;
  54
  55         sr_dbg("Uploading FPGA firmware '%s'.", name);
  56
  57         result = sr_resource_open(drvc->sr_ctx, &bitstream,
  58                         SR_RESOURCE_FIRMWARE, name);
  59         if (result != SR_OK)
  60                 return result;
  61
  62         /* Tell the device firmware is coming. */
  63         memset(cmd, 0, sizeof(cmd));
  64         if ((ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
  65                         LIBUSB_ENDPOINT_OUT, DS_CMD_FPGA_FW, 0x0000, 0x0000,
  66                         (unsigned char *)&cmd, sizeof(cmd), USB_TIMEOUT)) < 0) {
  67                 sr_err("Failed to upload FPGA firmware: %s.", libusb_error_name(ret));
  68                 sr_resource_close(drvc->sr_ctx, &bitstream);
  69                 return SR_ERR;
  70         }
  71
  72         /* Give the FX2 time to get ready for FPGA firmware upload. */
  73         g_usleep(FPGA_UPLOAD_DELAY);
  74
  75         buf = g_malloc(FW_BUFSIZE);
  76         sum = 0;
  77         result = SR_OK;
  78         while (1) {
  79                 chunksize = sr_resource_read(drvc->sr_ctx, &bitstream,
  80                                 buf, FW_BUFSIZE);
  81                 if (chunksize < 0)
  82                         result = SR_ERR;
  83                 if (chunksize <= 0)
  84                         break;
  85
  86                 if ((ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
  87                                 buf, chunksize, &transferred, USB_TIMEOUT)) < 0) {
  88                         sr_err("Unable to configure FPGA firmware: %s.",
  89                                         libusb_error_name(ret));
  90                         result = SR_ERR;
  91                         break;
  92                 }
  93                 sum += transferred;
  94                 sr_spew("Uploaded %" PRIu64 "/%" PRIu64 " bytes.",
  95                         sum, bitstream.size);
  96
  97                 if (transferred != chunksize) {
  98                         sr_err("Short transfer while uploading FPGA firmware.");
  99                         result = SR_ERR;
 100                         break;
 101                 }
 102         }
 103         g_free(buf);
 104         sr_resource_close(drvc->sr_ctx, &bitstream);
 105
 106         if (result == SR_OK)
 107                 sr_dbg("FPGA firmware upload done.");
 108
 109         return result;
 110 }
 111
 112 SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi)
 113 {
 114         struct dev_context *devc;
 115         struct sr_usb_dev_inst *usb;
 116         struct dslogic_mode mode;
 117         int ret;
 118
 119         devc = sdi->priv;
 120         mode.flags = DS_START_FLAGS_MODE_LA;
 121         mode.sample_delay_h = mode.sample_delay_l = 0;
 122         if (devc->sample_wide)
 123                 mode.flags |= DS_START_FLAGS_SAMPLE_WIDE;
 124
 125         usb = sdi->conn;
 126         ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
 127                         LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
 128                         (unsigned char *)&mode, sizeof(mode), USB_TIMEOUT);
 129         if (ret < 0) {
 130                 sr_err("Failed to send start command: %s.", libusb_error_name(ret));
 131                 return SR_ERR;
 132         }
 133
 134         return SR_OK;
 135 }
 136
 137 SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi)
 138 {
 139         struct sr_usb_dev_inst *usb;
 140         struct dslogic_mode mode;
 141         int ret;
 142
 143         mode.flags = DS_START_FLAGS_STOP;
 144         mode.sample_delay_h = mode.sample_delay_l = 0;
 145
 146         usb = sdi->conn;
 147         ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
 148                         LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
 149                         (unsigned char *)&mode, sizeof(struct dslogic_mode), USB_TIMEOUT);
 150         if (ret < 0) {
 151                 sr_err("Failed to send stop command: %s.", libusb_error_name(ret));
 152                 return SR_ERR;
 153         }
 154
 155         return SR_OK;
 156 }
 157
 158 /*
 159  * Get the session trigger and configure the FPGA structure
 160  * accordingly.
 161  */
 162 static int dslogic_set_trigger(const struct sr_dev_inst *sdi,
 163         struct dslogic_fpga_config *cfg)
 164 {
 165         struct sr_trigger *trigger;
 166         struct sr_trigger_stage *stage;
 167         struct sr_trigger_match *match;
 168
 169         struct dev_context *devc;
 170         devc = sdi->priv;
 171         const GSList *l, *m;
 172         int channelbit, i = 0;
 173         uint16_t v16;
 174
 175         cfg->trig_mask0[0] = 0xffff;
 176         cfg->trig_mask1[0] = 0xffff;
 177
 178         cfg->trig_value0[0] = 0;
 179         cfg->trig_value1[0] = 0;
 180
 181         cfg->trig_edge0[0] = 0;
 182         cfg->trig_edge1[0] = 0;
 183
 184         cfg->trig_logic0[0] = 0;
 185         cfg->trig_logic1[0] = 0;
 186
 187         cfg->trig_count0[0] = 0;
 188         cfg->trig_count1[0] = 0;
 189
 190         cfg->trig_pos = 0;
 191         cfg->trig_sda = 0;
 192         cfg->trig_glb = 0;
 193         cfg->trig_adp = cfg->count - cfg->trig_pos - 1;
 194
 195         for (i = 1; i < 16; i++) {
 196                 cfg->trig_mask0[i] = 0xff;
 197                 cfg->trig_mask1[i] = 0xff;
 198                 cfg->trig_value0[i] = 0;
 199                 cfg->trig_value1[i] = 0;
 200                 cfg->trig_edge0[i] = 0;
 201                 cfg->trig_edge1[i] = 0;
 202                 cfg->trig_count0[i] = 0;
 203                 cfg->trig_count1[i] = 0;
 204                 cfg->trig_logic0[i] = 2;
 205                 cfg->trig_logic1[i] = 2;
 206         }
 207
 208         cfg->trig_pos = (uint32_t)(devc->capture_ratio / 100.0 * devc->limit_samples);
 209         sr_dbg("pos: %d", cfg->trig_pos);
 210
 211         sr_dbg("configuring trigger");
 212
 213         if (!(trigger = sr_session_trigger_get(sdi->session))){
 214                 sr_dbg("No session trigger found");
 215                 return SR_OK;
 216         }
 217
 218         for (l = trigger->stages; l; l = l->next) {
 219                 stage = l->data;
 220                 for (m = stage->matches; m; m = m->next) {
 221                         match = m->data;
 222                         if (!match->channel->enabled)
 223                                 /* Ignore disabled channels with a trigger. */
 224                                 continue;
 225                         channelbit = 1 << (match->channel->index);
 226                         /* Simple trigger support (event). */
 227                         if (match->match == SR_TRIGGER_ONE) {
 228                                 cfg->trig_mask0[0] &= ~channelbit;
 229                                 cfg->trig_mask1[0] &= ~channelbit;
 230                                 cfg->trig_value0[0] |= channelbit;
 231                                 cfg->trig_value1[0] |= channelbit;
 232                         } else if (match->match == SR_TRIGGER_ZERO) {
 233                                 cfg->trig_mask0[0] &= ~channelbit;
 234                                 cfg->trig_mask1[0] &= ~channelbit;
 235                         } else if (match->match == SR_TRIGGER_FALLING) {
 236                                 cfg->trig_mask0[0] &= ~channelbit;
 237                                 cfg->trig_mask1[0] &= ~channelbit;
 238                                 cfg->trig_edge0[0] |= channelbit;
 239                                 cfg->trig_edge1[0] |= channelbit;
 240                         } else if (match->match == SR_TRIGGER_RISING) {
 241                                 cfg->trig_mask0[0] &= ~channelbit;
 242                                 cfg->trig_mask1[0] &= ~channelbit;
 243                                 cfg->trig_value0[0] |= channelbit;
 244                                 cfg->trig_value1[0] |= channelbit;
 245                                 cfg->trig_edge0[0] |= channelbit;
 246                                 cfg->trig_edge1[0] |= channelbit;
 247                         } else if(match->match == SR_TRIGGER_EDGE){
 248                                 cfg->trig_edge0[0] |= channelbit;
 249                                 cfg->trig_edge1[0] |= channelbit;
 250                         }
 251                 }
 252         }
 253         v16 = RL16(&cfg->mode);
 254         v16 |= 1 << 0;
 255         WL16(&cfg->mode, v16);
 256         return SR_OK;
 257 }
 258
 259
 260 SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
 261 {
 262         struct dev_context *devc;
 263         struct sr_usb_dev_inst *usb;
 264         uint8_t c[3];
 265         struct dslogic_fpga_config cfg;
 266         uint16_t v16;
 267         uint32_t v32;
 268         int transferred, len, ret;
 269
 270         sr_dbg("Configuring FPGA.");
 271         usb = sdi->conn;
 272         devc = sdi->priv;
 273
 274         WL32(&cfg.sync, DS_CFG_START);
 275         WL16(&cfg.mode_header, DS_CFG_MODE);
 276         WL32(&cfg.divider_header, DS_CFG_DIVIDER);
 277         WL32(&cfg.count_header, DS_CFG_COUNT);
 278         WL32(&cfg.trig_pos_header, DS_CFG_TRIG_POS);
 279         WL16(&cfg.trig_glb_header, DS_CFG_TRIG_GLB);
 280         WL32(&cfg.trig_adp_header, DS_CFG_TRIG_ADP);
 281         WL32(&cfg.trig_sda_header, DS_CFG_TRIG_SDA);
 282         WL32(&cfg.trig_mask0_header, DS_CFG_TRIG_MASK0);
 283         WL32(&cfg.trig_mask1_header, DS_CFG_TRIG_MASK1);
 284         WL32(&cfg.trig_value0_header, DS_CFG_TRIG_VALUE0);
 285         WL32(&cfg.trig_value1_header, DS_CFG_TRIG_VALUE1);
 286         WL32(&cfg.trig_edge0_header, DS_CFG_TRIG_EDGE0);
 287         WL32(&cfg.trig_edge1_header, DS_CFG_TRIG_EDGE1);
 288         WL32(&cfg.trig_count0_header, DS_CFG_TRIG_COUNT0);
 289         WL32(&cfg.trig_count1_header, DS_CFG_TRIG_COUNT1);
 290         WL32(&cfg.trig_logic0_header, DS_CFG_TRIG_LOGIC0);
 291         WL32(&cfg.trig_logic1_header, DS_CFG_TRIG_LOGIC1);
 292         WL32(&cfg.end_sync, DS_CFG_END);
 293
 294         /* Pass in the length of a fixed-size struct. Really. */
 295         len = sizeof(struct dslogic_fpga_config) / 2;
 296         c[0] = len & 0xff;
 297         c[1] = (len >> 8) & 0xff;
 298         c[2] = (len >> 16) & 0xff;
 299
 300         ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
 301                         LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000,
 302                         c, 3, USB_TIMEOUT);
 303         if (ret < 0) {
 304                 sr_err("Failed to send FPGA configure command: %s.", libusb_error_name(ret));
 305                 return SR_ERR;
 306         }
 307
 308         /*
 309          * 15   1 = internal test mode
 310          * 14   1 = external test mode
 311          * 13   1 = loopback test mode
 312          * 12   1 = stream mode
 313          * 11   1 = serial trigger
 314          * 8-12 unused
 315          * 7    1 = analog mode
 316          * 6    1 = samplerate 400MHz
 317          * 5    1 = samplerate 200MHz or analog mode
 318          * 4    0 = logic, 1 = dso or analog
 319          * 2-3  unused
 320          * 1    0 = internal clock, 1 = external clock
 321          * 0    1 = trigger enabled
 322          */
 323         v16 = 0x0000;
 324         if (devc->dslogic_mode == DS_OP_INTERNAL_TEST)
 325                 v16 = 1 << 15;
 326         else if (devc->dslogic_mode == DS_OP_EXTERNAL_TEST)
 327                 v16 = 1 << 14;
 328         else if (devc->dslogic_mode == DS_OP_LOOPBACK_TEST)
 329                 v16 = 1 << 13;
 330         if (devc->dslogic_external_clock)
 331                 v16 |= 1 << 1;
 332         WL16(&cfg.mode, v16);
 333         v32 = ceil(SR_MHZ(100) * 1.0 / devc->cur_samplerate);
 334         WL32(&cfg.divider, v32);
 335         WL32(&cfg.count, devc->limit_samples);
 336
 337         dslogic_set_trigger(sdi, &cfg);
 338
 339         len = sizeof(struct dslogic_fpga_config);
 340         ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
 341                         (unsigned char *)&cfg, len, &transferred, USB_TIMEOUT);
 342         if (ret < 0 || transferred != len) {
 343                 sr_err("Failed to send FPGA configuration: %s.", libusb_error_name(ret));
 344                 return SR_ERR;
 345         }
 346
 347         return SR_OK;
 348 }