src/hardware/dslogic/dslogic.c

   1 /*
   2  * This file is part of the libsigrok project.
   3  *
   4  * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
   5  * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
   6  *
   7  * This program is free software: you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation, either version 3 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include <config.h>
  22 #include <math.h>
  23 #include <glib.h>
  24 #include <glib/gstdio.h>
  25 #include "protocol.h"
  26 #include "dslogic.h"
  27
  28 /*
  29  * This should be larger than the FPGA bitstream image so that it'll get
  30  * uploaded in one big operation. There seem to be issues when uploading
  31  * it in chunks.
  32  */
  33 #define FW_BUFSIZE (1024 * 1024)
  34
  35 #define FPGA_UPLOAD_DELAY (10 * 1000)
  36
  37 #define USB_TIMEOUT (3 * 1000)
  38
  39 SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi)
  40 {
  41         const char *name = NULL;
  42         uint64_t sum;
  43         struct sr_resource bitstream;
  44         struct drv_context *drvc;
  45         struct dev_context *devc;
  46         struct sr_usb_dev_inst *usb;
  47         unsigned char *buf;
  48         ssize_t chunksize;
  49         int transferred;
  50         int result, ret;
  51         const uint8_t cmd[3] = {0, 0, 0};
  52
  53         drvc = sdi->driver->context;
  54         devc = sdi->priv;
  55         usb = sdi->conn;
  56
  57         if (!strcmp(devc->profile->model, "DSLogic")) {
  58                 if (devc->cur_threshold < 1.40)
  59                         name = DSLOGIC_FPGA_FIRMWARE_3V3;
  60                 else
  61                         name = DSLOGIC_FPGA_FIRMWARE_5V;
  62         } else if (!strcmp(devc->profile->model, "DSLogic Pro")){
  63                 name = DSLOGIC_PRO_FPGA_FIRMWARE;
  64         } else if (!strcmp(devc->profile->model, "DSLogic Plus")){
  65                 name = DSLOGIC_PLUS_FPGA_FIRMWARE;
  66         } else if (!strcmp(devc->profile->model, "DSLogic Basic")){
  67                 name = DSLOGIC_BASIC_FPGA_FIRMWARE;
  68         } else if (!strcmp(devc->profile->model, "DSCope")) {
  69                 name = DSCOPE_FPGA_FIRMWARE;
  70         } else {
  71                 sr_err("Failed to select FPGA firmware.");
  72                 return SR_ERR;
  73         }
  74
  75         sr_dbg("Uploading FPGA firmware '%s'.", name);
  76
  77         result = sr_resource_open(drvc->sr_ctx, &bitstream,
  78                         SR_RESOURCE_FIRMWARE, name);
  79         if (result != SR_OK)
  80                 return result;
  81
  82         /* Tell the device firmware is coming. */
  83         if ((ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
  84                         LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000,
  85                         (unsigned char *)&cmd, sizeof(cmd), USB_TIMEOUT)) < 0) {
  86                 sr_err("Failed to upload FPGA firmware: %s.", libusb_error_name(ret));
  87                 sr_resource_close(drvc->sr_ctx, &bitstream);
  88                 return SR_ERR;
  89         }
  90
  91         /* Give the FX2 time to get ready for FPGA firmware upload. */
  92         g_usleep(FPGA_UPLOAD_DELAY);
  93
  94         buf = g_malloc(FW_BUFSIZE);
  95         sum = 0;
  96         result = SR_OK;
  97         while (1) {
  98                 chunksize = sr_resource_read(drvc->sr_ctx, &bitstream,
  99                                 buf, FW_BUFSIZE);
 100                 if (chunksize < 0)
 101                         result = SR_ERR;
 102                 if (chunksize <= 0)
 103                         break;
 104
 105                 if ((ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
 106                                 buf, chunksize, &transferred, USB_TIMEOUT)) < 0) {
 107                         sr_err("Unable to configure FPGA firmware: %s.",
 108                                         libusb_error_name(ret));
 109                         result = SR_ERR;
 110                         break;
 111                 }
 112                 sum += transferred;
 113                 sr_spew("Uploaded %" PRIu64 "/%" PRIu64 " bytes.",
 114                         sum, bitstream.size);
 115
 116                 if (transferred != chunksize) {
 117                         sr_err("Short transfer while uploading FPGA firmware.");
 118                         result = SR_ERR;
 119                         break;
 120                 }
 121         }
 122         g_free(buf);
 123         sr_resource_close(drvc->sr_ctx, &bitstream);
 124
 125         if (result == SR_OK)
 126                 sr_dbg("FPGA firmware upload done.");
 127
 128         return result;
 129 }
 130
 131 SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi)
 132 {
 133         struct sr_usb_dev_inst *usb;
 134         struct dslogic_mode mode;
 135         int ret;
 136
 137         mode.flags = DS_START_FLAGS_MODE_LA | DS_START_FLAGS_SAMPLE_WIDE;
 138         mode.sample_delay_h = mode.sample_delay_l = 0;
 139
 140         usb = sdi->conn;
 141         ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
 142                         LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
 143                         (unsigned char *)&mode, sizeof(mode), USB_TIMEOUT);
 144         if (ret < 0) {
 145                 sr_err("Failed to send start command: %s.", libusb_error_name(ret));
 146                 return SR_ERR;
 147         }
 148
 149         return SR_OK;
 150 }
 151
 152 SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi)
 153 {
 154         struct sr_usb_dev_inst *usb;
 155         struct dslogic_mode mode;
 156         int ret;
 157
 158         mode.flags = DS_START_FLAGS_STOP;
 159         mode.sample_delay_h = mode.sample_delay_l = 0;
 160
 161         usb = sdi->conn;
 162         ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
 163                         LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
 164                         (unsigned char *)&mode, sizeof(struct dslogic_mode), USB_TIMEOUT);
 165         if (ret < 0) {
 166                 sr_err("Failed to send stop command: %s.", libusb_error_name(ret));
 167                 return SR_ERR;
 168         }
 169
 170         return SR_OK;
 171 }
 172
 173 /*
 174  * Get the session trigger and configure the FPGA structure
 175  * accordingly.
 176  */
 177 static int dslogic_set_trigger(const struct sr_dev_inst *sdi,
 178         struct dslogic_fpga_config *cfg)
 179 {
 180         struct sr_trigger *trigger;
 181         struct sr_trigger_stage *stage;
 182         struct sr_trigger_match *match;
 183         struct dev_context *devc;
 184         const GSList *l, *m;
 185         int channelbit, i = 0;
 186         uint16_t v16;
 187
 188         devc = sdi->priv;
 189
 190         cfg->ch_en = 0;
 191         for (l = sdi->channels; l; l = l->next) {
 192                 const struct sr_channel *const probe = (struct sr_channel *)l->data;
 193                 cfg->ch_en |= probe->enabled << probe->index;
 194         }
 195
 196         cfg->trig_mask0[0] = 0xffff;
 197         cfg->trig_mask1[0] = 0xffff;
 198
 199         cfg->trig_value0[0] = 0;
 200         cfg->trig_value1[0] = 0;
 201
 202         cfg->trig_edge0[0] = 0;
 203         cfg->trig_edge1[0] = 0;
 204
 205         cfg->trig_logic0[0] = 0;
 206         cfg->trig_logic1[0] = 0;
 207
 208         cfg->trig_count[0] = 0;
 209
 210         cfg->trig_glb = 0;
 211
 212         for (i = 1; i < NUM_TRIGGER_STAGES; i++) {
 213                 cfg->trig_mask0[i] = 0xff;
 214                 cfg->trig_mask1[i] = 0xff;
 215                 cfg->trig_value0[i] = 0;
 216                 cfg->trig_value1[i] = 0;
 217                 cfg->trig_edge0[i] = 0;
 218                 cfg->trig_edge1[i] = 0;
 219                 cfg->trig_logic0[i] = 2;
 220                 cfg->trig_logic1[i] = 2;
 221                 cfg->trig_count[i] = 0;
 222         }
 223
 224         cfg->trig_pos = (uint32_t)(devc->capture_ratio / 100.0 * devc->limit_samples);
 225         sr_dbg("pos: %d", cfg->trig_pos);
 226
 227         sr_dbg("configuring trigger");
 228
 229         if (!(trigger = sr_session_trigger_get(sdi->session))) {
 230                 sr_dbg("No session trigger found");
 231                 return SR_OK;
 232         }
 233
 234         for (l = trigger->stages; l; l = l->next) {
 235                 stage = l->data;
 236                 for (m = stage->matches; m; m = m->next) {
 237                         match = m->data;
 238                         if (!match->channel->enabled)
 239                                 /* Ignore disabled channels with a trigger. */
 240                                 continue;
 241                         channelbit = 1 << (match->channel->index);
 242                         /* Simple trigger support (event). */
 243                         if (match->match == SR_TRIGGER_ONE) {
 244                                 cfg->trig_mask0[0] &= ~channelbit;
 245                                 cfg->trig_mask1[0] &= ~channelbit;
 246                                 cfg->trig_value0[0] |= channelbit;
 247                                 cfg->trig_value1[0] |= channelbit;
 248                         } else if (match->match == SR_TRIGGER_ZERO) {
 249                                 cfg->trig_mask0[0] &= ~channelbit;
 250                                 cfg->trig_mask1[0] &= ~channelbit;
 251                         } else if (match->match == SR_TRIGGER_FALLING) {
 252                                 cfg->trig_mask0[0] &= ~channelbit;
 253                                 cfg->trig_mask1[0] &= ~channelbit;
 254                                 cfg->trig_edge0[0] |= channelbit;
 255                                 cfg->trig_edge1[0] |= channelbit;
 256                         } else if (match->match == SR_TRIGGER_RISING) {
 257                                 cfg->trig_mask0[0] &= ~channelbit;
 258                                 cfg->trig_mask1[0] &= ~channelbit;
 259                                 cfg->trig_value0[0] |= channelbit;
 260                                 cfg->trig_value1[0] |= channelbit;
 261                                 cfg->trig_edge0[0] |= channelbit;
 262                                 cfg->trig_edge1[0] |= channelbit;
 263                         } else if (match->match == SR_TRIGGER_EDGE) {
 264                                 cfg->trig_edge0[0] |= channelbit;
 265                                 cfg->trig_edge1[0] |= channelbit;
 266                         }
 267                 }
 268         }
 269
 270         v16 = RL16(&cfg->mode);
 271         v16 |= 1 << 0;
 272         WL16(&cfg->mode, v16);
 273
 274         return SR_OK;
 275 }
 276
 277 SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
 278 {
 279         struct dev_context *devc;
 280         struct sr_usb_dev_inst *usb;
 281         uint8_t c[3];
 282         struct dslogic_fpga_config cfg;
 283         uint16_t v16;
 284         uint32_t v32;
 285         int transferred, len, ret;
 286
 287         sr_dbg("Configuring FPGA.");
 288
 289         usb = sdi->conn;
 290         devc = sdi->priv;
 291
 292         WL32(&cfg.sync, DS_CFG_START);
 293         WL16(&cfg.mode_header, DS_CFG_MODE);
 294         WL16(&cfg.divider_header, DS_CFG_DIVIDER);
 295         WL16(&cfg.count_header, DS_CFG_COUNT);
 296         WL16(&cfg.trig_pos_header, DS_CFG_TRIG_POS);
 297         WL16(&cfg.trig_glb_header, DS_CFG_TRIG_GLB);
 298         WL16(&cfg.ch_en_header, DS_CFG_CH_EN);
 299         WL16(&cfg.trig_header, DS_CFG_TRIG);
 300         WL32(&cfg.end_sync, DS_CFG_END);
 301
 302         /* Pass in the length of a fixed-size struct. Really. */
 303         len = sizeof(struct dslogic_fpga_config) / 2;
 304         c[0] = len & 0xff;
 305         c[1] = (len >> 8) & 0xff;
 306         c[2] = (len >> 16) & 0xff;
 307
 308         ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
 309                         LIBUSB_ENDPOINT_OUT, DS_CMD_SETTING, 0x0000, 0x0000,
 310                         c, sizeof(c), USB_TIMEOUT);
 311         if (ret < 0) {
 312                 sr_err("Failed to send FPGA configure command: %s.",
 313                         libusb_error_name(ret));
 314                 return SR_ERR;
 315         }
 316
 317         v16 = 0x0000;
 318
 319         if (devc->mode == DS_OP_INTERNAL_TEST)
 320                 v16 = DS_MODE_INT_TEST;
 321         else if (devc->mode == DS_OP_EXTERNAL_TEST)
 322                 v16 = DS_MODE_EXT_TEST;
 323         else if (devc->mode == DS_OP_LOOPBACK_TEST)
 324                 v16 = DS_MODE_LPB_TEST;
 325
 326         if (devc->cur_samplerate == DS_MAX_LOGIC_SAMPLERATE * 2)
 327                 v16 |= DS_MODE_HALF_MODE;
 328         else if (devc->cur_samplerate == DS_MAX_LOGIC_SAMPLERATE * 4)
 329                 v16 |= DS_MODE_QUAR_MODE;
 330
 331         if (devc->continuous_mode)
 332                 v16 |= DS_MODE_STREAM_MODE;
 333         if (devc->external_clock) {
 334                 v16 |= DS_MODE_CLK_TYPE;
 335                 if (devc->clock_edge == DS_EDGE_FALLING)
 336                         v16 |= DS_MODE_CLK_EDGE;
 337         }
 338         if (devc->limit_samples > DS_MAX_LOGIC_DEPTH *
 339                 ceil(devc->cur_samplerate * 1.0 / DS_MAX_LOGIC_SAMPLERATE)
 340                 && !devc->continuous_mode) {
 341                 /* Enable RLE for long captures.
 342                  * Without this, captured data present errors.
 343                  */
 344                 v16 |= DS_MODE_RLE_MODE;
 345         }
 346
 347         WL16(&cfg.mode, v16);
 348         v32 = ceil(DS_MAX_LOGIC_SAMPLERATE * 1.0 / devc->cur_samplerate);
 349         WL32(&cfg.divider, v32);
 350         WL32(&cfg.count, devc->limit_samples);
 351
 352         dslogic_set_trigger(sdi, &cfg);
 353
 354         len = sizeof(struct dslogic_fpga_config);
 355         ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
 356                         (unsigned char *)&cfg, len, &transferred, USB_TIMEOUT);
 357         if (ret < 0 || transferred != len) {
 358                 sr_err("Failed to send FPGA configuration: %s.", libusb_error_name(ret));
 359                 return SR_ERR;
 360         }
 361
 362         return SR_OK;
 363 }
 364
 365 static int to_bytes_per_ms(struct dev_context *devc)
 366 {
 367         if (devc->cur_samplerate > SR_MHZ(100))
 368                 return SR_MHZ(100) / 1000 * 2;
 369         return devc->cur_samplerate / 1000 * 2;
 370 }
 371
 372 static size_t get_buffer_size(struct dev_context *devc)
 373 {
 374         size_t s;
 375
 376         /*
 377          * The buffer should be large enough to hold 10ms of data and
 378          * a multiple of 512.
 379          */
 380         s = 10 * to_bytes_per_ms(devc);
 381         // s = to_bytes_per_ms(devc->cur_samplerate);
 382         return (s + 511) & ~511;
 383 }
 384
 385 SR_PRIV int dslogic_get_number_of_transfers(struct dev_context *devc)
 386 {
 387         unsigned int n;
 388
 389         /* Total buffer size should be able to hold about 100ms of data. */
 390         n = (100 * to_bytes_per_ms(devc) / get_buffer_size(devc));
 391         sr_info("New calculation: %d", n);
 392
 393         if (n > NUM_SIMUL_TRANSFERS)
 394                 return NUM_SIMUL_TRANSFERS;
 395
 396         return n;
 397 }