2 * This file is part of the libsigrok project.
4 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
5 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation, either version 3 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 #include <glib/gstdio.h>
29 * This should be larger than the FPGA bitstream image so that it'll get
30 * uploaded in one big operation. There seem to be issues when uploading
33 #define FW_BUFSIZE (1024 * 1024)
35 #define FPGA_UPLOAD_DELAY (10 * 1000)
37 #define USB_TIMEOUT (3 * 1000)
39 SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi)
41 const char *name = NULL;
43 struct sr_resource bitstream;
44 struct drv_context *drvc;
45 struct dev_context *devc;
46 struct sr_usb_dev_inst *usb;
51 const uint8_t cmd[3] = {0, 0, 0};
53 drvc = sdi->driver->context;
57 if (!strcmp(devc->profile->model, "DSLogic")) {
58 if (devc->cur_threshold < 1.40)
59 name = DSLOGIC_FPGA_FIRMWARE_3V3;
61 name = DSLOGIC_FPGA_FIRMWARE_5V;
62 } else if (!strcmp(devc->profile->model, "DSLogic Pro")){
63 name = DSLOGIC_PRO_FPGA_FIRMWARE;
64 } else if (!strcmp(devc->profile->model, "DSLogic Plus")){
65 name = DSLOGIC_PLUS_FPGA_FIRMWARE;
66 } else if (!strcmp(devc->profile->model, "DSLogic Basic")){
67 name = DSLOGIC_BASIC_FPGA_FIRMWARE;
68 } else if (!strcmp(devc->profile->model, "DSCope")) {
69 name = DSCOPE_FPGA_FIRMWARE;
71 sr_err("Failed to select FPGA firmware.");
75 sr_dbg("Uploading FPGA firmware '%s'.", name);
77 result = sr_resource_open(drvc->sr_ctx, &bitstream,
78 SR_RESOURCE_FIRMWARE, name);
82 /* Tell the device firmware is coming. */
83 if ((ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
84 LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000,
85 (unsigned char *)&cmd, sizeof(cmd), USB_TIMEOUT)) < 0) {
86 sr_err("Failed to upload FPGA firmware: %s.", libusb_error_name(ret));
87 sr_resource_close(drvc->sr_ctx, &bitstream);
91 /* Give the FX2 time to get ready for FPGA firmware upload. */
92 g_usleep(FPGA_UPLOAD_DELAY);
94 buf = g_malloc(FW_BUFSIZE);
98 chunksize = sr_resource_read(drvc->sr_ctx, &bitstream,
105 if ((ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
106 buf, chunksize, &transferred, USB_TIMEOUT)) < 0) {
107 sr_err("Unable to configure FPGA firmware: %s.",
108 libusb_error_name(ret));
113 sr_spew("Uploaded %" PRIu64 "/%" PRIu64 " bytes.",
114 sum, bitstream.size);
116 if (transferred != chunksize) {
117 sr_err("Short transfer while uploading FPGA firmware.");
123 sr_resource_close(drvc->sr_ctx, &bitstream);
126 sr_dbg("FPGA firmware upload done.");
131 SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi)
133 struct sr_usb_dev_inst *usb;
134 struct dslogic_mode mode;
137 mode.flags = DS_START_FLAGS_MODE_LA | DS_START_FLAGS_SAMPLE_WIDE;
138 mode.sample_delay_h = mode.sample_delay_l = 0;
141 ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
142 LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
143 (unsigned char *)&mode, sizeof(mode), USB_TIMEOUT);
145 sr_err("Failed to send start command: %s.", libusb_error_name(ret));
152 SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi)
154 struct sr_usb_dev_inst *usb;
155 struct dslogic_mode mode;
158 mode.flags = DS_START_FLAGS_STOP;
159 mode.sample_delay_h = mode.sample_delay_l = 0;
162 ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
163 LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
164 (unsigned char *)&mode, sizeof(struct dslogic_mode), USB_TIMEOUT);
166 sr_err("Failed to send stop command: %s.", libusb_error_name(ret));
174 * Get the session trigger and configure the FPGA structure
177 static void dslogic_set_trigger(const struct sr_dev_inst *sdi,
178 struct dslogic_fpga_config *cfg)
180 struct sr_trigger *trigger;
181 struct sr_trigger_stage *stage;
182 struct sr_trigger_match *match;
183 struct dev_context *devc;
185 int num_enabled_channels = 0, num_trigger_stages = 0;
186 int channelbit, i = 0;
187 uint32_t trigger_point;
192 for (l = sdi->channels; l; l = l->next) {
193 const struct sr_channel *const probe = (struct sr_channel *)l->data;
194 if (probe->enabled) {
195 num_enabled_channels++;
196 cfg->ch_en |= 1 << probe->index;
200 cfg->trig_mask0[0] = 0xffff;
201 cfg->trig_mask1[0] = 0xffff;
203 cfg->trig_value0[0] = 0;
204 cfg->trig_value1[0] = 0;
206 cfg->trig_edge0[0] = 0;
207 cfg->trig_edge1[0] = 0;
209 cfg->trig_logic0[0] = 2;
210 cfg->trig_logic1[0] = 2;
212 cfg->trig_count[0] = 0;
214 cfg->trig_glb = num_enabled_channels << 4;
216 for (i = 1; i < NUM_TRIGGER_STAGES; i++) {
217 cfg->trig_mask0[i] = 0xffff;
218 cfg->trig_mask1[i] = 0xffff;
219 cfg->trig_value0[i] = 0;
220 cfg->trig_value1[i] = 0;
221 cfg->trig_edge0[i] = 0;
222 cfg->trig_edge1[i] = 0;
223 cfg->trig_logic0[i] = 2;
224 cfg->trig_logic1[i] = 2;
225 cfg->trig_count[i] = 0;
228 trigger_point = (devc->capture_ratio * devc->limit_samples) / 100;
229 if (trigger_point < DSLOGIC_ATOMIC_SAMPLES)
230 trigger_point = DSLOGIC_ATOMIC_SAMPLES;
231 const uint32_t mem_depth = devc->profile->mem_depth;
232 const uint32_t max_trigger_point = devc->continuous_mode ? ((mem_depth * 10) / 100) :
233 ((mem_depth * DS_MAX_TRIG_PERCENT) / 100);
234 if (trigger_point > max_trigger_point)
235 trigger_point = max_trigger_point;
236 cfg->trig_pos = trigger_point & ~(DSLOGIC_ATOMIC_SAMPLES - 1);
238 if (!(trigger = sr_session_trigger_get(sdi->session))) {
239 sr_dbg("No session trigger found");
243 for (l = trigger->stages; l; l = l->next) {
245 num_trigger_stages++;
246 for (m = stage->matches; m; m = m->next) {
248 if (!match->channel->enabled)
249 /* Ignore disabled channels with a trigger. */
251 channelbit = 1 << (match->channel->index);
252 /* Simple trigger support (event). */
253 if (match->match == SR_TRIGGER_ONE) {
254 cfg->trig_mask0[0] &= ~channelbit;
255 cfg->trig_mask1[0] &= ~channelbit;
256 cfg->trig_value0[0] |= channelbit;
257 cfg->trig_value1[0] |= channelbit;
258 } else if (match->match == SR_TRIGGER_ZERO) {
259 cfg->trig_mask0[0] &= ~channelbit;
260 cfg->trig_mask1[0] &= ~channelbit;
261 } else if (match->match == SR_TRIGGER_FALLING) {
262 cfg->trig_mask0[0] &= ~channelbit;
263 cfg->trig_mask1[0] &= ~channelbit;
264 cfg->trig_edge0[0] |= channelbit;
265 cfg->trig_edge1[0] |= channelbit;
266 } else if (match->match == SR_TRIGGER_RISING) {
267 cfg->trig_mask0[0] &= ~channelbit;
268 cfg->trig_mask1[0] &= ~channelbit;
269 cfg->trig_value0[0] |= channelbit;
270 cfg->trig_value1[0] |= channelbit;
271 cfg->trig_edge0[0] |= channelbit;
272 cfg->trig_edge1[0] |= channelbit;
273 } else if (match->match == SR_TRIGGER_EDGE) {
274 cfg->trig_edge0[0] |= channelbit;
275 cfg->trig_edge1[0] |= channelbit;
280 cfg->trig_glb |= num_trigger_stages;
285 SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
287 struct dev_context *devc;
288 struct sr_usb_dev_inst *usb;
290 struct dslogic_fpga_config cfg;
293 int transferred, len, ret;
295 sr_dbg("Configuring FPGA.");
300 WL32(&cfg.sync, DS_CFG_START);
301 WL16(&cfg.mode_header, DS_CFG_MODE);
302 WL16(&cfg.divider_header, DS_CFG_DIVIDER);
303 WL16(&cfg.count_header, DS_CFG_COUNT);
304 WL16(&cfg.trig_pos_header, DS_CFG_TRIG_POS);
305 WL16(&cfg.trig_glb_header, DS_CFG_TRIG_GLB);
306 WL16(&cfg.ch_en_header, DS_CFG_CH_EN);
307 WL16(&cfg.trig_header, DS_CFG_TRIG);
308 WL32(&cfg.end_sync, DS_CFG_END);
310 /* Pass in the length of a fixed-size struct. Really. */
311 len = sizeof(struct dslogic_fpga_config) / 2;
313 c[1] = (len >> 8) & 0xff;
314 c[2] = (len >> 16) & 0xff;
316 ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
317 LIBUSB_ENDPOINT_OUT, DS_CMD_SETTING, 0x0000, 0x0000,
318 c, sizeof(c), USB_TIMEOUT);
320 sr_err("Failed to send FPGA configure command: %s.",
321 libusb_error_name(ret));
327 if (devc->mode == DS_OP_INTERNAL_TEST)
328 v16 = DS_MODE_INT_TEST;
329 else if (devc->mode == DS_OP_EXTERNAL_TEST)
330 v16 = DS_MODE_EXT_TEST;
331 else if (devc->mode == DS_OP_LOOPBACK_TEST)
332 v16 = DS_MODE_LPB_TEST;
334 if (devc->cur_samplerate == DS_MAX_LOGIC_SAMPLERATE * 2)
335 v16 |= DS_MODE_HALF_MODE;
336 else if (devc->cur_samplerate == DS_MAX_LOGIC_SAMPLERATE * 4)
337 v16 |= DS_MODE_QUAR_MODE;
339 if (devc->continuous_mode)
340 v16 |= DS_MODE_STREAM_MODE;
341 if (devc->external_clock) {
342 v16 |= DS_MODE_CLK_TYPE;
343 if (devc->clock_edge == DS_EDGE_FALLING)
344 v16 |= DS_MODE_CLK_EDGE;
346 if (devc->limit_samples > DS_MAX_LOGIC_DEPTH *
347 ceil(devc->cur_samplerate * 1.0 / DS_MAX_LOGIC_SAMPLERATE)
348 && !devc->continuous_mode) {
349 /* Enable RLE for long captures.
350 * Without this, captured data present errors.
352 v16 |= DS_MODE_RLE_MODE;
355 WL16(&cfg.mode, v16);
356 v32 = ceil(DS_MAX_LOGIC_SAMPLERATE * 1.0 / devc->cur_samplerate);
357 WL32(&cfg.divider, v32);
359 /* Number of 16-sample units. */
360 WL32(&cfg.count, devc->limit_samples / 16);
362 dslogic_set_trigger(sdi, &cfg);
364 len = sizeof(struct dslogic_fpga_config);
365 ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
366 (unsigned char *)&cfg, len, &transferred, USB_TIMEOUT);
367 if (ret < 0 || transferred != len) {
368 sr_err("Failed to send FPGA configuration: %s.", libusb_error_name(ret));
375 static int to_bytes_per_ms(struct dev_context *devc)
377 if (devc->cur_samplerate > SR_MHZ(100))
378 return SR_MHZ(100) / 1000 * 2;
379 return devc->cur_samplerate / 1000 * 2;
382 static size_t get_buffer_size(struct dev_context *devc)
387 * The buffer should be large enough to hold 10ms of data and
390 s = 10 * to_bytes_per_ms(devc);
391 // s = to_bytes_per_ms(devc->cur_samplerate);
392 return (s + 511) & ~511;
395 SR_PRIV int dslogic_get_number_of_transfers(struct dev_context *devc)
399 /* Total buffer size should be able to hold about 100ms of data. */
400 n = (100 * to_bytes_per_ms(devc) / get_buffer_size(devc));
401 sr_info("New calculation: %d", n);
403 if (n > NUM_SIMUL_TRANSFERS)
404 return NUM_SIMUL_TRANSFERS;