src/hardware/dslogic/dslogic.c

   1 /*
   2  * This file is part of the libsigrok project.
   3  *
   4  * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
   5  * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
   6  *
   7  * This program is free software: you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation, either version 3 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include <config.h>
  22 #include <math.h>
  23 #include <glib.h>
  24 #include <glib/gstdio.h>
  25 #include "protocol.h"
  26 #include "dslogic.h"
  27
  28 /*
  29  * This should be larger than the FPGA bitstream image so that it'll get
  30  * uploaded in one big operation. There seem to be issues when uploading
  31  * it in chunks.
  32  */
  33 #define FW_BUFSIZE (1024 * 1024)
  34
  35 #define FPGA_UPLOAD_DELAY (10 * 1000)
  36
  37 #define USB_TIMEOUT (3 * 1000)
  38
  39 SR_PRIV int dslogic_set_vth(const struct sr_dev_inst *sdi, double vth)
  40 {
  41         struct sr_usb_dev_inst *usb;
  42         int ret;
  43         const uint8_t value = (vth / 5.0) * 255;
  44         const uint16_t cmd = value | (DS_ADDR_VTH << 8);
  45
  46         usb = sdi->conn;
  47
  48         /* Send the control command. */
  49         ret = libusb_control_transfer(usb->devhdl,
  50                         LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT,
  51                         DS_CMD_WR_REG, 0x0000, 0x0000,
  52                         (unsigned char *)&cmd, sizeof(cmd), 3000);
  53         if (ret < 0) {
  54                 sr_err("Unable to send VTH command: %s.",
  55                 libusb_error_name(ret));
  56                 return SR_ERR;
  57         }
  58
  59         return SR_OK;
  60 }
  61
  62 SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi)
  63 {
  64         const char *name = NULL;
  65         uint64_t sum;
  66         struct sr_resource bitstream;
  67         struct drv_context *drvc;
  68         struct dev_context *devc;
  69         struct sr_usb_dev_inst *usb;
  70         unsigned char *buf;
  71         ssize_t chunksize;
  72         int transferred;
  73         int result, ret;
  74         const uint8_t cmd[3] = {0, 0, 0};
  75
  76         drvc = sdi->driver->context;
  77         devc = sdi->priv;
  78         usb = sdi->conn;
  79
  80         if (!strcmp(devc->profile->model, "DSLogic")) {
  81                 if (devc->voltage_threshold == DS_VOLTAGE_RANGE_18_33_V)
  82                         name = DSLOGIC_FPGA_FIRMWARE_3V3;
  83                 else
  84                         name = DSLOGIC_FPGA_FIRMWARE_5V;
  85         } else if (!strcmp(devc->profile->model, "DSLogic Pro")){
  86                 name = DSLOGIC_PRO_FPGA_FIRMWARE;
  87         } else if (!strcmp(devc->profile->model, "DSLogic Plus")){
  88                 name = DSLOGIC_PLUS_FPGA_FIRMWARE;
  89         } else if (!strcmp(devc->profile->model, "DSLogic Basic")){
  90                 name = DSLOGIC_BASIC_FPGA_FIRMWARE;
  91         } else if (!strcmp(devc->profile->model, "DSCope")) {
  92                 name = DSCOPE_FPGA_FIRMWARE;
  93         } else {
  94                 sr_err("Failed to select FPGA firmware.");
  95                 return SR_ERR;
  96         }
  97
  98         sr_dbg("Uploading FPGA firmware '%s'.", name);
  99
 100         result = sr_resource_open(drvc->sr_ctx, &bitstream,
 101                         SR_RESOURCE_FIRMWARE, name);
 102         if (result != SR_OK)
 103                 return result;
 104
 105         /* Tell the device firmware is coming. */
 106         if ((ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
 107                         LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000,
 108                         (unsigned char *)&cmd, sizeof(cmd), USB_TIMEOUT)) < 0) {
 109                 sr_err("Failed to upload FPGA firmware: %s.", libusb_error_name(ret));
 110                 sr_resource_close(drvc->sr_ctx, &bitstream);
 111                 return SR_ERR;
 112         }
 113
 114         /* Give the FX2 time to get ready for FPGA firmware upload. */
 115         g_usleep(FPGA_UPLOAD_DELAY);
 116
 117         buf = g_malloc(FW_BUFSIZE);
 118         sum = 0;
 119         result = SR_OK;
 120         while (1) {
 121                 chunksize = sr_resource_read(drvc->sr_ctx, &bitstream,
 122                                 buf, FW_BUFSIZE);
 123                 if (chunksize < 0)
 124                         result = SR_ERR;
 125                 if (chunksize <= 0)
 126                         break;
 127
 128                 if ((ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
 129                                 buf, chunksize, &transferred, USB_TIMEOUT)) < 0) {
 130                         sr_err("Unable to configure FPGA firmware: %s.",
 131                                         libusb_error_name(ret));
 132                         result = SR_ERR;
 133                         break;
 134                 }
 135                 sum += transferred;
 136                 sr_spew("Uploaded %" PRIu64 "/%" PRIu64 " bytes.",
 137                         sum, bitstream.size);
 138
 139                 if (transferred != chunksize) {
 140                         sr_err("Short transfer while uploading FPGA firmware.");
 141                         result = SR_ERR;
 142                         break;
 143                 }
 144         }
 145         g_free(buf);
 146         sr_resource_close(drvc->sr_ctx, &bitstream);
 147
 148         if (result == SR_OK)
 149                 sr_dbg("FPGA firmware upload done.");
 150
 151         return result;
 152 }
 153
 154 SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi)
 155 {
 156         struct sr_usb_dev_inst *usb;
 157         struct dslogic_mode mode;
 158         int ret;
 159
 160         mode.flags = DS_START_FLAGS_MODE_LA | DS_START_FLAGS_SAMPLE_WIDE;
 161         mode.sample_delay_h = mode.sample_delay_l = 0;
 162
 163         usb = sdi->conn;
 164         ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
 165                         LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
 166                         (unsigned char *)&mode, sizeof(mode), USB_TIMEOUT);
 167         if (ret < 0) {
 168                 sr_err("Failed to send start command: %s.", libusb_error_name(ret));
 169                 return SR_ERR;
 170         }
 171
 172         return SR_OK;
 173 }
 174
 175 SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi)
 176 {
 177         struct sr_usb_dev_inst *usb;
 178         struct dslogic_mode mode;
 179         int ret;
 180
 181         mode.flags = DS_START_FLAGS_STOP;
 182         mode.sample_delay_h = mode.sample_delay_l = 0;
 183
 184         usb = sdi->conn;
 185         ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
 186                         LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
 187                         (unsigned char *)&mode, sizeof(struct dslogic_mode), USB_TIMEOUT);
 188         if (ret < 0) {
 189                 sr_err("Failed to send stop command: %s.", libusb_error_name(ret));
 190                 return SR_ERR;
 191         }
 192
 193         return SR_OK;
 194 }
 195
 196 /*
 197  * Get the session trigger and configure the FPGA structure
 198  * accordingly.
 199  */
 200 static int dslogic_set_trigger(const struct sr_dev_inst *sdi,
 201         struct dslogic_fpga_config *cfg)
 202 {
 203         struct sr_trigger *trigger;
 204         struct sr_trigger_stage *stage;
 205         struct sr_trigger_match *match;
 206         struct dev_context *devc;
 207         const GSList *l, *m;
 208         int channelbit, i = 0;
 209         uint16_t v16;
 210
 211         devc = sdi->priv;
 212
 213         cfg->ch_en = 0;
 214         for (l = sdi->channels; l; l = l->next) {
 215                 const struct sr_channel *const probe = (struct sr_channel *)l->data;
 216                 cfg->ch_en |= probe->enabled << probe->index;
 217         }
 218
 219         cfg->trig_mask0[0] = 0xffff;
 220         cfg->trig_mask1[0] = 0xffff;
 221
 222         cfg->trig_value0[0] = 0;
 223         cfg->trig_value1[0] = 0;
 224
 225         cfg->trig_edge0[0] = 0;
 226         cfg->trig_edge1[0] = 0;
 227
 228         cfg->trig_logic0[0] = 0;
 229         cfg->trig_logic1[0] = 0;
 230
 231         cfg->trig_count[0] = 0;
 232
 233         cfg->trig_glb = 0;
 234
 235         for (i = 1; i < NUM_TRIGGER_STAGES; i++) {
 236                 cfg->trig_mask0[i] = 0xff;
 237                 cfg->trig_mask1[i] = 0xff;
 238                 cfg->trig_value0[i] = 0;
 239                 cfg->trig_value1[i] = 0;
 240                 cfg->trig_edge0[i] = 0;
 241                 cfg->trig_edge1[i] = 0;
 242                 cfg->trig_logic0[i] = 2;
 243                 cfg->trig_logic1[i] = 2;
 244                 cfg->trig_count[i] = 0;
 245         }
 246
 247         cfg->trig_pos = (uint32_t)(devc->capture_ratio / 100.0 * devc->limit_samples);
 248         sr_dbg("pos: %d", cfg->trig_pos);
 249
 250         sr_dbg("configuring trigger");
 251
 252         if (!(trigger = sr_session_trigger_get(sdi->session))) {
 253                 sr_dbg("No session trigger found");
 254                 return SR_OK;
 255         }
 256
 257         for (l = trigger->stages; l; l = l->next) {
 258                 stage = l->data;
 259                 for (m = stage->matches; m; m = m->next) {
 260                         match = m->data;
 261                         if (!match->channel->enabled)
 262                                 /* Ignore disabled channels with a trigger. */
 263                                 continue;
 264                         channelbit = 1 << (match->channel->index);
 265                         /* Simple trigger support (event). */
 266                         if (match->match == SR_TRIGGER_ONE) {
 267                                 cfg->trig_mask0[0] &= ~channelbit;
 268                                 cfg->trig_mask1[0] &= ~channelbit;
 269                                 cfg->trig_value0[0] |= channelbit;
 270                                 cfg->trig_value1[0] |= channelbit;
 271                         } else if (match->match == SR_TRIGGER_ZERO) {
 272                                 cfg->trig_mask0[0] &= ~channelbit;
 273                                 cfg->trig_mask1[0] &= ~channelbit;
 274                         } else if (match->match == SR_TRIGGER_FALLING) {
 275                                 cfg->trig_mask0[0] &= ~channelbit;
 276                                 cfg->trig_mask1[0] &= ~channelbit;
 277                                 cfg->trig_edge0[0] |= channelbit;
 278                                 cfg->trig_edge1[0] |= channelbit;
 279                         } else if (match->match == SR_TRIGGER_RISING) {
 280                                 cfg->trig_mask0[0] &= ~channelbit;
 281                                 cfg->trig_mask1[0] &= ~channelbit;
 282                                 cfg->trig_value0[0] |= channelbit;
 283                                 cfg->trig_value1[0] |= channelbit;
 284                                 cfg->trig_edge0[0] |= channelbit;
 285                                 cfg->trig_edge1[0] |= channelbit;
 286                         } else if (match->match == SR_TRIGGER_EDGE) {
 287                                 cfg->trig_edge0[0] |= channelbit;
 288                                 cfg->trig_edge1[0] |= channelbit;
 289                         }
 290                 }
 291         }
 292
 293         v16 = RL16(&cfg->mode);
 294         v16 |= 1 << 0;
 295         WL16(&cfg->mode, v16);
 296
 297         return SR_OK;
 298 }
 299
 300 SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
 301 {
 302         struct dev_context *devc;
 303         struct sr_usb_dev_inst *usb;
 304         uint8_t c[3];
 305         struct dslogic_fpga_config cfg;
 306         uint16_t v16;
 307         uint32_t v32;
 308         int transferred, len, ret;
 309
 310         sr_dbg("Configuring FPGA.");
 311
 312         usb = sdi->conn;
 313         devc = sdi->priv;
 314
 315         WL32(&cfg.sync, DS_CFG_START);
 316         WL16(&cfg.mode_header, DS_CFG_MODE);
 317         WL16(&cfg.divider_header, DS_CFG_DIVIDER);
 318         WL16(&cfg.count_header, DS_CFG_COUNT);
 319         WL16(&cfg.trig_pos_header, DS_CFG_TRIG_POS);
 320         WL16(&cfg.trig_glb_header, DS_CFG_TRIG_GLB);
 321         WL16(&cfg.ch_en_header, DS_CFG_CH_EN);
 322         WL16(&cfg.trig_header, DS_CFG_TRIG);
 323         WL32(&cfg.end_sync, DS_CFG_END);
 324
 325         /* Pass in the length of a fixed-size struct. Really. */
 326         len = sizeof(struct dslogic_fpga_config) / 2;
 327         c[0] = len & 0xff;
 328         c[1] = (len >> 8) & 0xff;
 329         c[2] = (len >> 16) & 0xff;
 330
 331         ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
 332                         LIBUSB_ENDPOINT_OUT, DS_CMD_SETTING, 0x0000, 0x0000,
 333                         c, sizeof(c), USB_TIMEOUT);
 334         if (ret < 0) {
 335                 sr_err("Failed to send FPGA configure command: %s.",
 336                         libusb_error_name(ret));
 337                 return SR_ERR;
 338         }
 339
 340         v16 = 0x0000;
 341
 342         if (devc->mode == DS_OP_INTERNAL_TEST)
 343                 v16 = DS_MODE_INT_TEST;
 344         else if (devc->mode == DS_OP_EXTERNAL_TEST)
 345                 v16 = DS_MODE_EXT_TEST;
 346         else if (devc->mode == DS_OP_LOOPBACK_TEST)
 347                 v16 = DS_MODE_LPB_TEST;
 348
 349         if (devc->cur_samplerate == DS_MAX_LOGIC_SAMPLERATE * 2)
 350                 v16 |= DS_MODE_HALF_MODE;
 351         else if (devc->cur_samplerate == DS_MAX_LOGIC_SAMPLERATE * 4)
 352                 v16 |= DS_MODE_QUAR_MODE;
 353
 354         if (devc->continuous_mode)
 355                 v16 |= DS_MODE_STREAM_MODE;
 356         if (devc->external_clock) {
 357                 v16 |= DS_MODE_CLK_TYPE;
 358                 if (devc->clock_edge == DS_EDGE_FALLING)
 359                         v16 |= DS_MODE_CLK_EDGE;
 360         }
 361         if (devc->limit_samples > DS_MAX_LOGIC_DEPTH *
 362                 ceil(devc->cur_samplerate * 1.0 / DS_MAX_LOGIC_SAMPLERATE)
 363                 && !devc->continuous_mode) {
 364                 /* Enable RLE for long captures.
 365                  * Without this, captured data present errors.
 366                  */
 367                 v16 |= DS_MODE_RLE_MODE;
 368         }
 369
 370         WL16(&cfg.mode, v16);
 371         v32 = ceil(DS_MAX_LOGIC_SAMPLERATE * 1.0 / devc->cur_samplerate);
 372         WL32(&cfg.divider, v32);
 373         WL32(&cfg.count, devc->limit_samples);
 374
 375         dslogic_set_trigger(sdi, &cfg);
 376
 377         len = sizeof(struct dslogic_fpga_config);
 378         ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
 379                         (unsigned char *)&cfg, len, &transferred, USB_TIMEOUT);
 380         if (ret < 0 || transferred != len) {
 381                 sr_err("Failed to send FPGA configuration: %s.", libusb_error_name(ret));
 382                 return SR_ERR;
 383         }
 384
 385         return SR_OK;
 386 }
 387
 388 static int to_bytes_per_ms(struct dev_context *devc)
 389 {
 390         if (devc->cur_samplerate > SR_MHZ(100))
 391                 return SR_MHZ(100) / 1000 * 2;
 392         return devc->cur_samplerate / 1000 * 2;
 393 }
 394
 395 static size_t get_buffer_size(struct dev_context *devc)
 396 {
 397         size_t s;
 398
 399         /*
 400          * The buffer should be large enough to hold 10ms of data and
 401          * a multiple of 512.
 402          */
 403         s = 10 * to_bytes_per_ms(devc);
 404         // s = to_bytes_per_ms(devc->cur_samplerate);
 405         return (s + 511) & ~511;
 406 }
 407
 408 SR_PRIV int dslogic_get_number_of_transfers(struct dev_context *devc)
 409 {
 410         unsigned int n;
 411
 412         /* Total buffer size should be able to hold about 100ms of data. */
 413         n = (100 * to_bytes_per_ms(devc) / get_buffer_size(devc));
 414         sr_info("New calculation: %d", n);
 415
 416         if (n > NUM_SIMUL_TRANSFERS)
 417                 return NUM_SIMUL_TRANSFERS;
 418
 419         return n;
 420 }