2 * This file is part of the libsigrok project.
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #ifndef LIBSIGROK_HARDWARE_ASIX_SIGMA_PROTOCOL_H
23 #define LIBSIGROK_HARDWARE_ASIX_SIGMA_PROTOCOL_H
30 #include <libsigrok/libsigrok.h>
31 #include "libsigrok-internal.h"
34 * Triggers are not working in this implementation. Stop claiming
35 * support for the feature which effectively is not available, until
36 * the implementation got fixed. Yet keep the code in place and allow
37 * developers to turn on this switch during development.
39 #define ASIX_SIGMA_WITH_TRIGGER 0
41 #define LOG_PREFIX "asix-sigma"
43 #define USB_VENDOR 0xa600
44 #define USB_PRODUCT 0xa000
45 #define USB_DESCRIPTION "ASIX SIGMA"
46 #define USB_VENDOR_NAME "ASIX"
47 #define USB_MODEL_NAME "SIGMA"
49 enum sigma_write_register {
50 WRITE_CLOCK_SELECT = 0,
51 WRITE_TRIGGER_SELECT0 = 1,
52 WRITE_TRIGGER_SELECT1 = 2,
55 WRITE_POST_TRIGGER = 5,
56 WRITE_TRIGGER_OPTION = 6,
62 enum sigma_read_register {
64 READ_TRIGGER_POS_LOW = 1,
65 READ_TRIGGER_POS_HIGH = 2,
66 READ_TRIGGER_POS_UP = 3,
67 READ_STOP_POS_LOW = 4,
68 READ_STOP_POS_HIGH = 5,
71 READ_PIN_CHANGE_LOW = 8,
72 READ_PIN_CHANGE_HIGH = 9,
73 READ_BLOCK_LAST_TS_LOW = 10,
74 READ_BLOCK_LAST_TS_HIGH = 11,
80 #define REG_ADDR_LOW (0x0 << 4)
81 #define REG_ADDR_HIGH (0x1 << 4)
82 #define REG_DATA_LOW (0x2 << 4)
83 #define REG_DATA_HIGH_WRITE (0x3 << 4)
84 #define REG_READ_ADDR (0x4 << 4)
85 #define REG_DRAM_WAIT_ACK (0x5 << 4)
87 /* Bit (1 << 4) can be low or high (double buffer / cache) */
88 #define REG_DRAM_BLOCK (0x6 << 4)
89 #define REG_DRAM_BLOCK_BEGIN (0x8 << 4)
90 #define REG_DRAM_BLOCK_DATA (0xa << 4)
97 #define EVENTS_PER_CLUSTER 7
99 #define CHUNK_SIZE 1024
101 /* WRITE_MODE register fields. */
102 #define WMR_SDRAMWRITEEN (1 << 0)
103 #define WMR_SDRAMREADEN (1 << 1)
104 #define WMR_TRGRES (1 << 2)
105 #define WMR_TRGEN (1 << 3)
106 #define WMR_FORCESTOP (1 << 4)
107 #define WMR_TRGSW (1 << 5)
108 /* not used: bit position 6 */
109 #define WMR_SDRAMINIT (1 << 7)
111 /* READ_MODE register fields. */
112 #define RMR_SDRAMWRITEEN (1 << 0)
113 #define RMR_SDRAMREADEN (1 << 1)
114 /* not used: bit position 2 */
115 #define RMR_TRGEN (1 << 3)
116 #define RMR_ROUND (1 << 4)
117 #define RMR_TRIGGERED (1 << 5)
118 #define RMR_POSTTRIGGERED (1 << 6)
119 /* not used: bit position 7 */
122 * The entire ASIX Sigma DRAM is an array of struct sigma_dram_line[1024];
125 /* One "DRAM cluster" contains a timestamp and 7 samples, 16b total. */
126 struct sigma_dram_cluster {
127 uint8_t timestamp_lo;
128 uint8_t timestamp_hi;
135 /* One "DRAM line" contains 64 "DRAM clusters", 1024b total. */
136 struct sigma_dram_line {
137 struct sigma_dram_cluster cluster[64];
140 struct clockselect_50 {
143 uint16_t disabled_channels;
146 /* The effect of all these are still a bit unclear. */
147 struct triggerinout {
148 uint8_t trgout_resistor_enable : 1;
149 uint8_t trgout_resistor_pullup : 1;
150 uint8_t reserved1 : 1;
151 uint8_t trgout_bytrigger : 1;
152 uint8_t trgout_byevent : 1;
153 uint8_t trgout_bytriggerin : 1;
154 uint8_t reserved2 : 2;
156 /* Should be set same as the first two */
157 uint8_t trgout_resistor_enable2 : 1;
158 uint8_t trgout_resistor_pullup2 : 1;
160 uint8_t reserved3 : 1;
161 uint8_t trgout_long : 1;
162 uint8_t trgout_pin : 1; /* Use 1k resistor. Pullup? */
163 uint8_t trgin_negate : 1;
164 uint8_t trgout_enable : 1;
165 uint8_t trgin_enable : 1;
169 /* The actual LUTs. */
170 uint16_t m0d[4], m1d[4], m2d[4];
171 uint16_t m3, m3s, m4;
173 /* Parameters should be sent as a single register write. */
176 uint8_t selpresc : 6;
188 /* Trigger configuration */
189 struct sigma_trigger {
190 /* Only two channels can be used in mask. */
192 uint16_t fallingmask;
194 /* Simple trigger support (<= 50 MHz). */
196 uint16_t simplevalue;
198 /* TODO: Advanced trigger support (boolean expressions). */
201 /* Events for trigger operation. */
213 /* Logical functions for trigger operation. */
225 SIGMA_UNINITIALIZED = 0,
235 /* Private, per-device-instance driver context. */
237 struct ftdi_context ftdic;
238 uint64_t cur_samplerate;
241 uint64_t limit_samples;
242 struct timeval start_tv;
246 int samples_per_event;
248 struct sigma_trigger trigger;
250 struct sigma_state state;
253 extern SR_PRIV const uint64_t samplerates[];
254 extern SR_PRIV const size_t samplerates_count;
256 SR_PRIV int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
257 struct dev_context *devc);
258 SR_PRIV int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc);
259 SR_PRIV int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc);
260 SR_PRIV void sigma_clear_helper(void *priv);
261 SR_PRIV uint64_t sigma_limit_samples_to_msec(const struct dev_context *devc,
262 uint64_t limit_samples);
263 SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate);
264 SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi);
265 SR_PRIV int sigma_receive_data(int fd, int revents, void *cb_data);
266 SR_PRIV int sigma_build_basic_trigger(struct triggerlut *lut, struct dev_context *devc);