2 * This file is part of the libsigrok project.
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
29 #define USB_VENDOR 0xa600
30 #define USB_PRODUCT 0xa000
31 #define USB_DESCRIPTION "ASIX SIGMA"
32 #define USB_VENDOR_NAME "ASIX"
33 #define USB_MODEL_NAME "SIGMA"
36 * The ASIX Sigma supports arbitrary integer frequency divider in
37 * the 50MHz mode. The divider is in range 1...256 , allowing for
38 * very precise sampling rate selection. This driver supports only
39 * a subset of the sampling rates.
41 SR_PRIV const uint64_t samplerates[] = {
42 SR_KHZ(200), /* div=250 */
43 SR_KHZ(250), /* div=200 */
44 SR_KHZ(500), /* div=100 */
45 SR_MHZ(1), /* div=50 */
46 SR_MHZ(5), /* div=10 */
47 SR_MHZ(10), /* div=5 */
48 SR_MHZ(25), /* div=2 */
49 SR_MHZ(50), /* div=1 */
50 SR_MHZ(100), /* Special FW needed */
51 SR_MHZ(200), /* Special FW needed */
54 SR_PRIV const size_t samplerates_count = ARRAY_SIZE(samplerates);
56 static const char sigma_firmware_files[][24] = {
57 /* 50 MHz, supports 8 bit fractions */
63 /* Synchronous clock from pin */
64 "asix-sigma-50sync.fw",
65 /* Frequency counter */
66 "asix-sigma-phasor.fw",
69 static int sigma_read(void *buf, size_t size, struct dev_context *devc)
73 ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size);
75 sr_err("ftdi_read_data failed: %s",
76 ftdi_get_error_string(&devc->ftdic));
82 static int sigma_write(void *buf, size_t size, struct dev_context *devc)
86 ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size);
88 sr_err("ftdi_write_data failed: %s",
89 ftdi_get_error_string(&devc->ftdic));
90 } else if ((size_t) ret != size) {
91 sr_err("ftdi_write_data did not complete write.");
98 * NOTE: We chose the buffer size to be large enough to hold any write to the
99 * device. We still print a message just in case.
101 SR_PRIV int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
102 struct dev_context *devc)
108 if ((2 * len + 2) > sizeof(buf)) {
109 sr_err("Attempted to write %zu bytes, but buffer is too small.",
114 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
115 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
117 for (i = 0; i < len; i++) {
118 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
119 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
122 return sigma_write(buf, idx, devc);
125 SR_PRIV int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc)
127 return sigma_write_register(reg, &value, 1, devc);
130 static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
131 struct dev_context *devc)
135 buf[0] = REG_ADDR_LOW | (reg & 0xf);
136 buf[1] = REG_ADDR_HIGH | (reg >> 4);
137 buf[2] = REG_READ_ADDR;
139 sigma_write(buf, sizeof(buf), devc);
141 return sigma_read(data, len, devc);
144 static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc)
148 if (1 != sigma_read_register(reg, &value, 1, devc)) {
149 sr_err("sigma_get_register: 1 byte expected");
156 static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
157 struct dev_context *devc)
160 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
162 REG_READ_ADDR | NEXT_REG,
163 REG_READ_ADDR | NEXT_REG,
164 REG_READ_ADDR | NEXT_REG,
165 REG_READ_ADDR | NEXT_REG,
166 REG_READ_ADDR | NEXT_REG,
167 REG_READ_ADDR | NEXT_REG,
171 sigma_write(buf, sizeof(buf), devc);
173 sigma_read(result, sizeof(result), devc);
175 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
176 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
178 /* Not really sure why this must be done, but according to spec. */
179 if ((--*stoppos & 0x1ff) == 0x1ff)
182 if ((*--triggerpos & 0x1ff) == 0x1ff)
188 static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
189 uint8_t *data, struct dev_context *devc)
195 /* Send the startchunk. Index start with 1. */
196 buf[0] = startchunk >> 8;
197 buf[1] = startchunk & 0xff;
198 sigma_write_register(WRITE_MEMROW, buf, 2, devc);
201 buf[idx++] = REG_DRAM_BLOCK;
202 buf[idx++] = REG_DRAM_WAIT_ACK;
204 for (i = 0; i < numchunks; i++) {
205 /* Alternate bit to copy from DRAM to cache. */
206 if (i != (numchunks - 1))
207 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
209 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
211 if (i != (numchunks - 1))
212 buf[idx++] = REG_DRAM_WAIT_ACK;
215 sigma_write(buf, idx, devc);
217 return sigma_read(data, numchunks * CHUNK_SIZE, devc);
220 /* Upload trigger look-up tables to Sigma. */
221 SR_PRIV int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc)
227 /* Transpose the table and send to Sigma. */
228 for (i = 0; i < 16; i++) {
233 if (lut->m2d[0] & bit)
235 if (lut->m2d[1] & bit)
237 if (lut->m2d[2] & bit)
239 if (lut->m2d[3] & bit)
249 if (lut->m0d[0] & bit)
251 if (lut->m0d[1] & bit)
253 if (lut->m0d[2] & bit)
255 if (lut->m0d[3] & bit)
258 if (lut->m1d[0] & bit)
260 if (lut->m1d[1] & bit)
262 if (lut->m1d[2] & bit)
264 if (lut->m1d[3] & bit)
267 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
269 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
272 /* Send the parameters */
273 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
274 sizeof(lut->params), devc);
279 SR_PRIV void sigma_clear_helper(void *priv)
281 struct dev_context *devc;
285 ftdi_deinit(&devc->ftdic);
289 * Configure the FPGA for bitbang mode.
290 * This sequence is documented in section 2. of the ASIX Sigma programming
291 * manual. This sequence is necessary to configure the FPGA in the Sigma
292 * into Bitbang mode, in which it can be programmed with the firmware.
294 static int sigma_fpga_init_bitbang(struct dev_context *devc)
296 uint8_t suicide[] = {
297 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
299 uint8_t init_array[] = {
300 0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01,
303 int i, ret, timeout = (10 * 1000);
306 /* Section 2. part 1), do the FPGA suicide. */
307 sigma_write(suicide, sizeof(suicide), devc);
308 sigma_write(suicide, sizeof(suicide), devc);
309 sigma_write(suicide, sizeof(suicide), devc);
310 sigma_write(suicide, sizeof(suicide), devc);
312 /* Section 2. part 2), do pulse on D1. */
313 sigma_write(init_array, sizeof(init_array), devc);
314 ftdi_usb_purge_buffers(&devc->ftdic);
316 /* Wait until the FPGA asserts D6/INIT_B. */
317 for (i = 0; i < timeout; i++) {
318 ret = sigma_read(&data, 1, devc);
321 /* Test if pin D6 got asserted. */
324 /* The D6 was not asserted yet, wait a bit. */
328 return SR_ERR_TIMEOUT;
332 * Configure the FPGA for logic-analyzer mode.
334 static int sigma_fpga_init_la(struct dev_context *devc)
336 /* Initialize the logic analyzer mode. */
337 uint8_t logic_mode_start[] = {
338 REG_ADDR_LOW | (READ_ID & 0xf),
339 REG_ADDR_HIGH | (READ_ID >> 8),
340 REG_READ_ADDR, /* Read ID register. */
342 REG_ADDR_LOW | (WRITE_TEST & 0xf),
344 REG_DATA_HIGH_WRITE | 0x5,
345 REG_READ_ADDR, /* Read scratch register. */
348 REG_DATA_HIGH_WRITE | 0xa,
349 REG_READ_ADDR, /* Read scratch register. */
351 REG_ADDR_LOW | (WRITE_MODE & 0xf),
353 REG_DATA_HIGH_WRITE | 0x8,
359 /* Initialize the logic analyzer mode. */
360 sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
362 /* Expect a 3 byte reply since we issued three READ requests. */
363 ret = sigma_read(result, 3, devc);
367 if (result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa)
372 sr_err("Configuration failed. Invalid reply received.");
377 * Read the firmware from a file and transform it into a series of bitbang
378 * pulses used to program the FPGA. Note that the *bb_cmd must be free()'d
379 * by the caller of this function.
381 static int sigma_fw_2_bitbang(struct sr_context *ctx, const char *name,
382 uint8_t **bb_cmd, gsize *bb_cmd_size)
384 size_t i, file_size, bb_size;
386 uint8_t *bb_stream, *bbs;
391 /* Retrieve the on-disk firmware file content. */
392 firmware = sr_resource_load(ctx, SR_RESOURCE_FIRMWARE,
393 name, &file_size, 256 * 1024);
397 /* Unscramble the file content (XOR with "random" sequence). */
399 for (i = 0; i < file_size; i++) {
400 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
401 firmware[i] ^= imm & 0xff;
405 * Generate a sequence of bitbang samples. With two samples per
406 * FPGA configuration bit, providing the level for the DIN signal
407 * as well as two edges for CCLK. See Xilinx UG332 for details
408 * ("slave serial" mode).
410 * Note that CCLK is inverted in hardware. That's why the
411 * respective bit is first set and then cleared in the bitbang
412 * sample sets. So that the DIN level will be stable when the
413 * data gets sampled at the rising CCLK edge, and the signals'
414 * setup time constraint will be met.
416 * The caller will put the FPGA into download mode, will send
417 * the bitbang samples, and release the allocated memory.
419 bb_size = file_size * 8 * 2;
420 bb_stream = (uint8_t *)g_try_malloc(bb_size);
422 sr_err("%s: Failed to allocate bitbang stream", __func__);
427 for (i = 0; i < file_size; i++) {
428 for (bit = 7; bit >= 0; bit--) {
429 v = (firmware[i] & (1 << bit)) ? 0x40 : 0x00;
435 /* The transformation completed successfully, return the result. */
437 *bb_cmd_size = bb_size;
444 static int upload_firmware(struct sr_context *ctx,
445 int firmware_idx, struct dev_context *devc)
451 const char *firmware = sigma_firmware_files[firmware_idx];
452 struct ftdi_context *ftdic = &devc->ftdic;
454 /* Make sure it's an ASIX SIGMA. */
455 ret = ftdi_usb_open_desc(ftdic, USB_VENDOR, USB_PRODUCT,
456 USB_DESCRIPTION, NULL);
458 sr_err("ftdi_usb_open failed: %s",
459 ftdi_get_error_string(ftdic));
463 ret = ftdi_set_bitmode(ftdic, 0xdf, BITMODE_BITBANG);
465 sr_err("ftdi_set_bitmode failed: %s",
466 ftdi_get_error_string(ftdic));
470 /* Four times the speed of sigmalogan - Works well. */
471 ret = ftdi_set_baudrate(ftdic, 750 * 1000);
473 sr_err("ftdi_set_baudrate failed: %s",
474 ftdi_get_error_string(ftdic));
478 /* Initialize the FPGA for firmware upload. */
479 ret = sigma_fpga_init_bitbang(devc);
483 /* Prepare firmware. */
484 ret = sigma_fw_2_bitbang(ctx, firmware, &buf, &buf_size);
486 sr_err("An error occurred while reading the firmware: %s",
491 /* Upload firmware. */
492 sr_info("Uploading firmware file '%s'.", firmware);
493 sigma_write(buf, buf_size, devc);
497 ret = ftdi_set_bitmode(ftdic, 0x00, BITMODE_RESET);
499 sr_err("ftdi_set_bitmode failed: %s",
500 ftdi_get_error_string(ftdic));
504 ftdi_usb_purge_buffers(ftdic);
506 /* Discard garbage. */
507 while (sigma_read(&pins, 1, devc) == 1)
510 /* Initialize the FPGA for logic-analyzer mode. */
511 ret = sigma_fpga_init_la(devc);
515 devc->cur_firmware = firmware_idx;
517 sr_info("Firmware uploaded.");
523 * Sigma doesn't support limiting the number of samples, so we have to
524 * translate the number and the samplerate to an elapsed time.
526 * In addition we need to ensure that the last data cluster has passed
527 * the hardware pipeline, and became available to the PC side. With RLE
528 * compression up to 327ms could pass before another cluster accumulates
529 * at 200kHz samplerate when input pins don't change.
531 SR_PRIV uint64_t sigma_limit_samples_to_msec(const struct dev_context *devc,
532 uint64_t limit_samples)
535 uint64_t worst_cluster_time_ms;
537 limit_msec = limit_samples * 1000 / devc->cur_samplerate;
538 worst_cluster_time_ms = 65536 * 1000 / devc->cur_samplerate;
540 * One cluster time is not enough to flush pipeline when sampling
541 * grounded pins with 1 sample limit at 200kHz. Hence the 2* fix.
543 return limit_msec + 2 * worst_cluster_time_ms;
546 SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
548 struct dev_context *devc;
549 struct drv_context *drvc;
554 drvc = sdi->driver->context;
557 /* Reject rates that are not in the list of supported rates. */
558 for (i = 0; i < samplerates_count; i++) {
559 if (samplerates[i] == samplerate)
562 if (i >= samplerates_count || samplerates[i] == 0)
563 return SR_ERR_SAMPLERATE;
566 * Depending on the samplerates of 200/100/50- MHz, specific
567 * firmware is required and higher rates might limit the set
568 * of available channels.
570 if (samplerate <= SR_MHZ(50)) {
571 ret = upload_firmware(drvc->sr_ctx, 0, devc);
572 devc->num_channels = 16;
573 } else if (samplerate == SR_MHZ(100)) {
574 ret = upload_firmware(drvc->sr_ctx, 1, devc);
575 devc->num_channels = 8;
576 } else if (samplerate == SR_MHZ(200)) {
577 ret = upload_firmware(drvc->sr_ctx, 2, devc);
578 devc->num_channels = 4;
582 * Derive the sample period from the sample rate as well as the
583 * number of samples that the device will communicate within
584 * an "event" (memory organization internal to the device).
587 devc->cur_samplerate = samplerate;
588 devc->period_ps = 1000000000000ULL / samplerate;
589 devc->samples_per_event = 16 / devc->num_channels;
590 devc->state.state = SIGMA_IDLE;
594 * Support for "limit_samples" is implemented by stopping
595 * acquisition after a corresponding period of time.
596 * Re-calculate that period of time, in case the limit is
597 * set first and the samplerate gets (re-)configured later.
599 if (ret == SR_OK && devc->limit_samples) {
601 msecs = sigma_limit_samples_to_msec(devc, devc->limit_samples);
602 devc->limit_msec = msecs;
609 * In 100 and 200 MHz mode, only a single pin rising/falling can be
610 * set as trigger. In other modes, two rising/falling triggers can be set,
611 * in addition to value/mask trigger for any number of channels.
613 * The Sigma supports complex triggers using boolean expressions, but this
614 * has not been implemented yet.
616 SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi)
618 struct dev_context *devc;
619 struct sr_trigger *trigger;
620 struct sr_trigger_stage *stage;
621 struct sr_trigger_match *match;
623 int channelbit, trigger_set;
626 memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
627 if (!(trigger = sr_session_trigger_get(sdi->session)))
631 for (l = trigger->stages; l; l = l->next) {
633 for (m = stage->matches; m; m = m->next) {
635 if (!match->channel->enabled)
636 /* Ignore disabled channels with a trigger. */
638 channelbit = 1 << (match->channel->index);
639 if (devc->cur_samplerate >= SR_MHZ(100)) {
640 /* Fast trigger support. */
642 sr_err("Only a single pin trigger is "
643 "supported in 100 and 200MHz mode.");
646 if (match->match == SR_TRIGGER_FALLING)
647 devc->trigger.fallingmask |= channelbit;
648 else if (match->match == SR_TRIGGER_RISING)
649 devc->trigger.risingmask |= channelbit;
651 sr_err("Only rising/falling trigger is "
652 "supported in 100 and 200MHz mode.");
658 /* Simple trigger support (event). */
659 if (match->match == SR_TRIGGER_ONE) {
660 devc->trigger.simplevalue |= channelbit;
661 devc->trigger.simplemask |= channelbit;
663 else if (match->match == SR_TRIGGER_ZERO) {
664 devc->trigger.simplevalue &= ~channelbit;
665 devc->trigger.simplemask |= channelbit;
667 else if (match->match == SR_TRIGGER_FALLING) {
668 devc->trigger.fallingmask |= channelbit;
671 else if (match->match == SR_TRIGGER_RISING) {
672 devc->trigger.risingmask |= channelbit;
677 * Actually, Sigma supports 2 rising/falling triggers,
678 * but they are ORed and the current trigger syntax
679 * does not permit ORed triggers.
681 if (trigger_set > 1) {
682 sr_err("Only 1 rising/falling trigger "
694 /* Software trigger to determine exact trigger position. */
695 static int get_trigger_offset(uint8_t *samples, uint16_t last_sample,
696 struct sigma_trigger *t)
701 for (i = 0; i < 8; i++) {
703 last_sample = sample;
704 sample = samples[2 * i] | (samples[2 * i + 1] << 8);
706 /* Simple triggers. */
707 if ((sample & t->simplemask) != t->simplevalue)
711 if (((last_sample & t->risingmask) != 0) ||
712 ((sample & t->risingmask) != t->risingmask))
716 if ((last_sample & t->fallingmask) != t->fallingmask ||
717 (sample & t->fallingmask) != 0)
723 /* If we did not match, return original trigger pos. */
728 * Return the timestamp of "DRAM cluster".
730 static uint16_t sigma_dram_cluster_ts(struct sigma_dram_cluster *cluster)
732 return (cluster->timestamp_hi << 8) | cluster->timestamp_lo;
735 static void sigma_decode_dram_cluster(struct sigma_dram_cluster *dram_cluster,
736 unsigned int events_in_cluster,
737 unsigned int triggered,
738 struct sr_dev_inst *sdi)
740 struct dev_context *devc = sdi->priv;
741 struct sigma_state *ss = &devc->state;
742 struct sr_datafeed_packet packet;
743 struct sr_datafeed_logic logic;
745 uint8_t samples[2048];
748 ts = sigma_dram_cluster_ts(dram_cluster);
749 tsdiff = ts - ss->lastts;
750 ss->lastts = ts + EVENTS_PER_CLUSTER;
752 packet.type = SR_DF_LOGIC;
753 packet.payload = &logic;
755 logic.data = samples;
758 * First of all, send Sigrok a copy of the last sample from
759 * previous cluster as many times as needed to make up for
760 * the differential characteristics of data we get from the
761 * Sigma. Sigrok needs one sample of data per period.
763 * One DRAM cluster contains a timestamp and seven samples,
764 * the units of timestamp are "devc->period_ps" , the first
765 * sample in the cluster happens at the time of the timestamp
766 * and the remaining samples happen at timestamp +1...+6 .
768 for (ts = 0; ts < tsdiff; ts++) {
770 samples[2 * i + 0] = ss->lastsample & 0xff;
771 samples[2 * i + 1] = ss->lastsample >> 8;
774 * If we have 1024 samples ready or we're at the
775 * end of submitting the padding samples, submit
776 * the packet to Sigrok.
778 if ((i == 1023) || (ts == tsdiff - 1)) {
779 logic.length = (i + 1) * logic.unitsize;
780 sr_session_send(sdi, &packet);
785 * Parse the samples in current cluster and prepare them
786 * to be submitted to Sigrok.
788 for (i = 0; i < events_in_cluster; i++) {
789 samples[2 * i + 1] = dram_cluster->samples[i].sample_lo;
790 samples[2 * i + 0] = dram_cluster->samples[i].sample_hi;
793 /* Send data up to trigger point (if triggered). */
794 int trigger_offset = 0;
797 * Trigger is not always accurate to sample because of
798 * pipeline delay. However, it always triggers before
799 * the actual event. We therefore look at the next
800 * samples to pinpoint the exact position of the trigger.
802 trigger_offset = get_trigger_offset(samples,
803 ss->lastsample, &devc->trigger);
805 if (trigger_offset > 0) {
806 packet.type = SR_DF_LOGIC;
807 logic.length = trigger_offset * logic.unitsize;
808 sr_session_send(sdi, &packet);
809 events_in_cluster -= trigger_offset;
812 /* Only send trigger if explicitly enabled. */
813 if (devc->use_triggers) {
814 packet.type = SR_DF_TRIGGER;
815 sr_session_send(sdi, &packet);
819 if (events_in_cluster > 0) {
820 packet.type = SR_DF_LOGIC;
821 logic.length = events_in_cluster * logic.unitsize;
822 logic.data = samples + (trigger_offset * logic.unitsize);
823 sr_session_send(sdi, &packet);
827 samples[2 * (events_in_cluster - 1) + 0] |
828 (samples[2 * (events_in_cluster - 1) + 1] << 8);
833 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
834 * Each event is 20ns apart, and can contain multiple samples.
836 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
837 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
838 * For 50 MHz and below, events contain one sample for each channel,
839 * spread 20 ns apart.
841 static int decode_chunk_ts(struct sigma_dram_line *dram_line,
842 uint16_t events_in_line,
843 uint32_t trigger_event,
844 struct sr_dev_inst *sdi)
846 struct sigma_dram_cluster *dram_cluster;
847 struct dev_context *devc = sdi->priv;
848 unsigned int clusters_in_line =
849 (events_in_line + (EVENTS_PER_CLUSTER - 1)) / EVENTS_PER_CLUSTER;
850 unsigned int events_in_cluster;
852 uint32_t trigger_cluster = ~0, triggered = 0;
854 /* Check if trigger is in this chunk. */
855 if (trigger_event < (64 * 7)) {
856 if (devc->cur_samplerate <= SR_MHZ(50)) {
857 trigger_event -= MIN(EVENTS_PER_CLUSTER - 1,
861 /* Find in which cluster the trigger occurred. */
862 trigger_cluster = trigger_event / EVENTS_PER_CLUSTER;
865 /* For each full DRAM cluster. */
866 for (i = 0; i < clusters_in_line; i++) {
867 dram_cluster = &dram_line->cluster[i];
869 /* The last cluster might not be full. */
870 if ((i == clusters_in_line - 1) &&
871 (events_in_line % EVENTS_PER_CLUSTER)) {
872 events_in_cluster = events_in_line % EVENTS_PER_CLUSTER;
874 events_in_cluster = EVENTS_PER_CLUSTER;
877 triggered = (i == trigger_cluster);
878 sigma_decode_dram_cluster(dram_cluster, events_in_cluster,
885 static int download_capture(struct sr_dev_inst *sdi)
887 struct dev_context *devc = sdi->priv;
888 const uint32_t chunks_per_read = 32;
889 struct sigma_dram_line *dram_line;
891 uint32_t stoppos, triggerpos;
895 uint32_t dl_lines_total, dl_lines_curr, dl_lines_done;
896 uint32_t dl_events_in_line = 64 * 7;
897 uint32_t trg_line = ~0, trg_event = ~0;
899 dram_line = g_try_malloc0(chunks_per_read * sizeof(*dram_line));
903 sr_info("Downloading sample data.");
905 /* Stop acquisition. */
906 sigma_set_register(WRITE_MODE, 0x11, devc);
908 /* Set SDRAM Read Enable. */
909 sigma_set_register(WRITE_MODE, 0x02, devc);
911 /* Get the current position. */
912 sigma_read_pos(&stoppos, &triggerpos, devc);
914 /* Check if trigger has fired. */
915 modestatus = sigma_get_register(READ_MODE, devc);
916 if (modestatus & 0x20) {
917 trg_line = triggerpos >> 9;
918 trg_event = triggerpos & 0x1ff;
922 * Determine how many 1024b "DRAM lines" do we need to read from the
923 * Sigma so we have a complete set of samples. Note that the last
924 * line can be only partial, containing less than 64 clusters.
926 dl_lines_total = (stoppos >> 9) + 1;
930 while (dl_lines_total > dl_lines_done) {
931 /* We can download only up-to 32 DRAM lines in one go! */
932 dl_lines_curr = MIN(chunks_per_read, dl_lines_total);
934 bufsz = sigma_read_dram(dl_lines_done, dl_lines_curr,
935 (uint8_t *)dram_line, devc);
936 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
939 /* This is the first DRAM line, so find the initial timestamp. */
940 if (dl_lines_done == 0) {
942 sigma_dram_cluster_ts(&dram_line[0].cluster[0]);
943 devc->state.lastsample = 0;
946 for (i = 0; i < dl_lines_curr; i++) {
947 uint32_t trigger_event = ~0;
948 /* The last "DRAM line" can be only partially full. */
949 if (dl_lines_done + i == dl_lines_total - 1)
950 dl_events_in_line = stoppos & 0x1ff;
952 /* Test if the trigger happened on this line. */
953 if (dl_lines_done + i == trg_line)
954 trigger_event = trg_event;
956 decode_chunk_ts(dram_line + i, dl_events_in_line,
960 dl_lines_done += dl_lines_curr;
963 std_session_send_df_end(sdi);
965 sdi->driver->dev_acquisition_stop(sdi);
973 * Handle the Sigma when in CAPTURE mode. This function checks:
974 * - Sampling time ended
975 * - DRAM capacity overflow
976 * This function triggers download of the samples from Sigma
977 * in case either of the above conditions is true.
979 static int sigma_capture_mode(struct sr_dev_inst *sdi)
981 struct dev_context *devc = sdi->priv;
983 uint64_t running_msec;
986 uint32_t stoppos, triggerpos;
988 /* Check if the selected sampling duration passed. */
989 gettimeofday(&tv, 0);
990 running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 +
991 (tv.tv_usec - devc->start_tv.tv_usec) / 1000;
992 if (running_msec >= devc->limit_msec)
993 return download_capture(sdi);
995 /* Get the position in DRAM to which the FPGA is writing now. */
996 sigma_read_pos(&stoppos, &triggerpos, devc);
997 /* Test if DRAM is full and if so, download the data. */
998 if ((stoppos >> 9) == 32767)
999 return download_capture(sdi);
1004 SR_PRIV int sigma_receive_data(int fd, int revents, void *cb_data)
1006 struct sr_dev_inst *sdi;
1007 struct dev_context *devc;
1015 if (devc->state.state == SIGMA_IDLE)
1018 if (devc->state.state == SIGMA_CAPTURE)
1019 return sigma_capture_mode(sdi);
1024 /* Build a LUT entry used by the trigger functions. */
1025 static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1029 /* For each quad channel. */
1030 for (i = 0; i < 4; i++) {
1033 /* For each bit in LUT. */
1034 for (j = 0; j < 16; j++)
1036 /* For each channel in quad. */
1037 for (k = 0; k < 4; k++) {
1038 bit = 1 << (i * 4 + k);
1040 /* Set bit in entry */
1041 if ((mask & bit) && ((!(value & bit)) !=
1043 entry[i] &= ~(1 << j);
1048 /* Add a logical function to LUT mask. */
1049 static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1050 int index, int neg, uint16_t *mask)
1053 int x[2][2], tmp, a, b, aset, bset, rset;
1055 memset(x, 0, 4 * sizeof(int));
1057 /* Trigger detect condition. */
1087 case OP_NOTRISEFALL:
1093 /* Transpose if neg is set. */
1095 for (i = 0; i < 2; i++) {
1096 for (j = 0; j < 2; j++) {
1098 x[i][j] = x[1 - i][1 - j];
1099 x[1 - i][1 - j] = tmp;
1104 /* Update mask with function. */
1105 for (i = 0; i < 16; i++) {
1106 a = (i >> (2 * index + 0)) & 1;
1107 b = (i >> (2 * index + 1)) & 1;
1109 aset = (*mask >> i) & 1;
1113 if (func == FUNC_AND || func == FUNC_NAND)
1115 else if (func == FUNC_OR || func == FUNC_NOR)
1117 else if (func == FUNC_XOR || func == FUNC_NXOR)
1120 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1131 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1132 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1133 * set at any time, but a full mask and value can be set (0/1).
1135 SR_PRIV int sigma_build_basic_trigger(struct triggerlut *lut, struct dev_context *devc)
1138 uint16_t masks[2] = { 0, 0 };
1140 memset(lut, 0, sizeof(struct triggerlut));
1142 /* Constant for simple triggers. */
1145 /* Value/mask trigger support. */
1146 build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask,
1149 /* Rise/fall trigger support. */
1150 for (i = 0, j = 0; i < 16; i++) {
1151 if (devc->trigger.risingmask & (1 << i) ||
1152 devc->trigger.fallingmask & (1 << i))
1153 masks[j++] = 1 << i;
1156 build_lut_entry(masks[0], masks[0], lut->m0d);
1157 build_lut_entry(masks[1], masks[1], lut->m1d);
1159 /* Add glue logic */
1160 if (masks[0] || masks[1]) {
1161 /* Transition trigger. */
1162 if (masks[0] & devc->trigger.risingmask)
1163 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1164 if (masks[0] & devc->trigger.fallingmask)
1165 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1166 if (masks[1] & devc->trigger.risingmask)
1167 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1168 if (masks[1] & devc->trigger.fallingmask)
1169 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1171 /* Only value/mask trigger. */
1175 /* Triggertype: event. */
1176 lut->params.selres = 3;