2 * This file is part of the libsigrok project.
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
30 * The ASIX Sigma supports arbitrary integer frequency divider in
31 * the 50MHz mode. The divider is in range 1...256 , allowing for
32 * very precise sampling rate selection. This driver supports only
33 * a subset of the sampling rates.
35 SR_PRIV const uint64_t samplerates[] = {
36 SR_KHZ(200), /* div=250 */
37 SR_KHZ(250), /* div=200 */
38 SR_KHZ(500), /* div=100 */
39 SR_MHZ(1), /* div=50 */
40 SR_MHZ(5), /* div=10 */
41 SR_MHZ(10), /* div=5 */
42 SR_MHZ(25), /* div=2 */
43 SR_MHZ(50), /* div=1 */
44 SR_MHZ(100), /* Special FW needed */
45 SR_MHZ(200), /* Special FW needed */
48 SR_PRIV const size_t samplerates_count = ARRAY_SIZE(samplerates);
50 static const char firmware_files[][24] = {
51 /* 50 MHz, supports 8 bit fractions */
57 /* Synchronous clock from pin */
58 "asix-sigma-50sync.fw",
59 /* Frequency counter */
60 "asix-sigma-phasor.fw",
63 static int sigma_read(void *buf, size_t size, struct dev_context *devc)
67 ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size);
69 sr_err("ftdi_read_data failed: %s",
70 ftdi_get_error_string(&devc->ftdic));
76 static int sigma_write(void *buf, size_t size, struct dev_context *devc)
80 ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size);
82 sr_err("ftdi_write_data failed: %s",
83 ftdi_get_error_string(&devc->ftdic));
84 else if ((size_t) ret != size)
85 sr_err("ftdi_write_data did not complete write.");
91 * NOTE: We chose the buffer size to be large enough to hold any write to the
92 * device. We still print a message just in case.
94 SR_PRIV int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
95 struct dev_context *devc)
101 if ((2 * len + 2) > sizeof(buf)) {
102 sr_err("Attempted to write %zu bytes, but buffer is too small.",
107 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
108 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
110 for (i = 0; i < len; i++) {
111 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
112 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
115 return sigma_write(buf, idx, devc);
118 SR_PRIV int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc)
120 return sigma_write_register(reg, &value, 1, devc);
123 static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
124 struct dev_context *devc)
128 buf[0] = REG_ADDR_LOW | (reg & 0xf);
129 buf[1] = REG_ADDR_HIGH | (reg >> 4);
130 buf[2] = REG_READ_ADDR;
132 sigma_write(buf, sizeof(buf), devc);
134 return sigma_read(data, len, devc);
137 static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc)
141 if (1 != sigma_read_register(reg, &value, 1, devc)) {
142 sr_err("sigma_get_register: 1 byte expected");
149 static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
150 struct dev_context *devc)
153 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
155 REG_READ_ADDR | NEXT_REG,
156 REG_READ_ADDR | NEXT_REG,
157 REG_READ_ADDR | NEXT_REG,
158 REG_READ_ADDR | NEXT_REG,
159 REG_READ_ADDR | NEXT_REG,
160 REG_READ_ADDR | NEXT_REG,
164 sigma_write(buf, sizeof(buf), devc);
166 sigma_read(result, sizeof(result), devc);
168 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
169 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
172 * These "position" values point to after the event (end of
173 * capture data, trigger condition matched). This is why they
174 * get decremented here. Sample memory consists of 512-byte
175 * chunks with meta data in the upper 64 bytes. Thus when the
176 * decrements takes us into this upper part of the chunk, then
177 * further move backwards to the end of the chunk's data part.
179 if ((--*stoppos & 0x1ff) == 0x1ff)
181 if ((--*triggerpos & 0x1ff) == 0x1ff)
187 static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
188 uint8_t *data, struct dev_context *devc)
194 /* Send the startchunk. Index start with 1. */
196 buf[idx++] = startchunk >> 8;
197 buf[idx++] = startchunk & 0xff;
198 sigma_write_register(WRITE_MEMROW, buf, idx, devc);
202 buf[idx++] = REG_DRAM_BLOCK;
203 buf[idx++] = REG_DRAM_WAIT_ACK;
205 for (i = 0; i < numchunks; i++) {
206 /* Alternate bit to copy from DRAM to cache. */
207 if (i != (numchunks - 1))
208 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
210 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
212 if (i != (numchunks - 1))
213 buf[idx++] = REG_DRAM_WAIT_ACK;
216 sigma_write(buf, idx, devc);
218 return sigma_read(data, numchunks * CHUNK_SIZE, devc);
221 /* Upload trigger look-up tables to Sigma. */
222 SR_PRIV int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc)
228 /* Transpose the table and send to Sigma. */
229 for (i = 0; i < 16; i++) {
234 if (lut->m2d[0] & bit)
236 if (lut->m2d[1] & bit)
238 if (lut->m2d[2] & bit)
240 if (lut->m2d[3] & bit)
250 if (lut->m0d[0] & bit)
252 if (lut->m0d[1] & bit)
254 if (lut->m0d[2] & bit)
256 if (lut->m0d[3] & bit)
259 if (lut->m1d[0] & bit)
261 if (lut->m1d[1] & bit)
263 if (lut->m1d[2] & bit)
265 if (lut->m1d[3] & bit)
268 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
270 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
273 /* Send the parameters */
274 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
275 sizeof(lut->params), devc);
281 * Configure the FPGA for bitbang mode.
282 * This sequence is documented in section 2. of the ASIX Sigma programming
283 * manual. This sequence is necessary to configure the FPGA in the Sigma
284 * into Bitbang mode, in which it can be programmed with the firmware.
286 static int sigma_fpga_init_bitbang(struct dev_context *devc)
288 uint8_t suicide[] = {
289 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
291 uint8_t init_array[] = {
292 0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01,
295 int i, ret, timeout = (10 * 1000);
298 /* Section 2. part 1), do the FPGA suicide. */
299 sigma_write(suicide, sizeof(suicide), devc);
300 sigma_write(suicide, sizeof(suicide), devc);
301 sigma_write(suicide, sizeof(suicide), devc);
302 sigma_write(suicide, sizeof(suicide), devc);
304 /* Section 2. part 2), do pulse on D1. */
305 sigma_write(init_array, sizeof(init_array), devc);
306 ftdi_usb_purge_buffers(&devc->ftdic);
308 /* Wait until the FPGA asserts D6/INIT_B. */
309 for (i = 0; i < timeout; i++) {
310 ret = sigma_read(&data, 1, devc);
313 /* Test if pin D6 got asserted. */
316 /* The D6 was not asserted yet, wait a bit. */
320 return SR_ERR_TIMEOUT;
324 * Configure the FPGA for logic-analyzer mode.
326 static int sigma_fpga_init_la(struct dev_context *devc)
328 /* Initialize the logic analyzer mode. */
329 uint8_t mode_regval = WMR_SDRAMINIT;
330 uint8_t logic_mode_start[] = {
331 REG_ADDR_LOW | (READ_ID & 0xf),
332 REG_ADDR_HIGH | (READ_ID >> 4),
333 REG_READ_ADDR, /* Read ID register. */
335 REG_ADDR_LOW | (WRITE_TEST & 0xf),
337 REG_DATA_HIGH_WRITE | 0x5,
338 REG_READ_ADDR, /* Read scratch register. */
341 REG_DATA_HIGH_WRITE | 0xa,
342 REG_READ_ADDR, /* Read scratch register. */
344 REG_ADDR_LOW | (WRITE_MODE & 0xf),
345 REG_DATA_LOW | (mode_regval & 0xf),
346 REG_DATA_HIGH_WRITE | (mode_regval >> 4),
352 /* Initialize the logic analyzer mode. */
353 sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
355 /* Expect a 3 byte reply since we issued three READ requests. */
356 ret = sigma_read(result, 3, devc);
360 if (result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa)
365 sr_err("Configuration failed. Invalid reply received.");
370 * Read the firmware from a file and transform it into a series of bitbang
371 * pulses used to program the FPGA. Note that the *bb_cmd must be free()'d
372 * by the caller of this function.
374 static int sigma_fw_2_bitbang(struct sr_context *ctx, const char *name,
375 uint8_t **bb_cmd, gsize *bb_cmd_size)
377 size_t i, file_size, bb_size;
379 uint8_t *bb_stream, *bbs;
384 /* Retrieve the on-disk firmware file content. */
385 firmware = sr_resource_load(ctx, SR_RESOURCE_FIRMWARE,
386 name, &file_size, 256 * 1024);
390 /* Unscramble the file content (XOR with "random" sequence). */
392 for (i = 0; i < file_size; i++) {
393 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
394 firmware[i] ^= imm & 0xff;
398 * Generate a sequence of bitbang samples. With two samples per
399 * FPGA configuration bit, providing the level for the DIN signal
400 * as well as two edges for CCLK. See Xilinx UG332 for details
401 * ("slave serial" mode).
403 * Note that CCLK is inverted in hardware. That's why the
404 * respective bit is first set and then cleared in the bitbang
405 * sample sets. So that the DIN level will be stable when the
406 * data gets sampled at the rising CCLK edge, and the signals'
407 * setup time constraint will be met.
409 * The caller will put the FPGA into download mode, will send
410 * the bitbang samples, and release the allocated memory.
412 bb_size = file_size * 8 * 2;
413 bb_stream = (uint8_t *)g_try_malloc(bb_size);
415 sr_err("%s: Failed to allocate bitbang stream", __func__);
420 for (i = 0; i < file_size; i++) {
421 for (bit = 7; bit >= 0; bit--) {
422 v = (firmware[i] & (1 << bit)) ? 0x40 : 0x00;
428 /* The transformation completed successfully, return the result. */
430 *bb_cmd_size = bb_size;
437 static int upload_firmware(struct sr_context *ctx,
438 int firmware_idx, struct dev_context *devc)
444 const char *firmware;
446 /* Avoid downloading the same firmware multiple times. */
447 firmware = firmware_files[firmware_idx];
448 if (devc->cur_firmware == firmware_idx) {
449 sr_info("Not uploading firmware file '%s' again.", firmware);
453 ret = ftdi_set_bitmode(&devc->ftdic, 0xdf, BITMODE_BITBANG);
455 sr_err("ftdi_set_bitmode failed: %s",
456 ftdi_get_error_string(&devc->ftdic));
460 /* Four times the speed of sigmalogan - Works well. */
461 ret = ftdi_set_baudrate(&devc->ftdic, 750 * 1000);
463 sr_err("ftdi_set_baudrate failed: %s",
464 ftdi_get_error_string(&devc->ftdic));
468 /* Initialize the FPGA for firmware upload. */
469 ret = sigma_fpga_init_bitbang(devc);
473 /* Prepare firmware. */
474 ret = sigma_fw_2_bitbang(ctx, firmware, &buf, &buf_size);
476 sr_err("An error occurred while reading the firmware: %s",
481 /* Upload firmware. */
482 sr_info("Uploading firmware file '%s'.", firmware);
483 sigma_write(buf, buf_size, devc);
487 ret = ftdi_set_bitmode(&devc->ftdic, 0x00, BITMODE_RESET);
489 sr_err("ftdi_set_bitmode failed: %s",
490 ftdi_get_error_string(&devc->ftdic));
494 ftdi_usb_purge_buffers(&devc->ftdic);
496 /* Discard garbage. */
497 while (sigma_read(&pins, 1, devc) == 1)
500 /* Initialize the FPGA for logic-analyzer mode. */
501 ret = sigma_fpga_init_la(devc);
505 devc->cur_firmware = firmware_idx;
507 sr_info("Firmware uploaded.");
513 * Sigma doesn't support limiting the number of samples, so we have to
514 * translate the number and the samplerate to an elapsed time.
516 * In addition we need to ensure that the last data cluster has passed
517 * the hardware pipeline, and became available to the PC side. With RLE
518 * compression up to 327ms could pass before another cluster accumulates
519 * at 200kHz samplerate when input pins don't change.
521 SR_PRIV uint64_t sigma_limit_samples_to_msec(const struct dev_context *devc,
522 uint64_t limit_samples)
525 uint64_t worst_cluster_time_ms;
527 limit_msec = limit_samples * 1000 / devc->cur_samplerate;
528 worst_cluster_time_ms = 65536 * 1000 / devc->cur_samplerate;
530 * One cluster time is not enough to flush pipeline when sampling
531 * grounded pins with 1 sample limit at 200kHz. Hence the 2* fix.
533 return limit_msec + 2 * worst_cluster_time_ms;
536 SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
538 struct dev_context *devc;
539 struct drv_context *drvc;
545 drvc = sdi->driver->context;
548 /* Reject rates that are not in the list of supported rates. */
549 for (i = 0; i < samplerates_count; i++) {
550 if (samplerates[i] == samplerate)
553 if (i >= samplerates_count || samplerates[i] == 0)
554 return SR_ERR_SAMPLERATE;
557 * Depending on the samplerates of 200/100/50- MHz, specific
558 * firmware is required and higher rates might limit the set
559 * of available channels.
561 num_channels = devc->num_channels;
562 if (samplerate <= SR_MHZ(50)) {
563 ret = upload_firmware(drvc->sr_ctx, 0, devc);
565 } else if (samplerate == SR_MHZ(100)) {
566 ret = upload_firmware(drvc->sr_ctx, 1, devc);
568 } else if (samplerate == SR_MHZ(200)) {
569 ret = upload_firmware(drvc->sr_ctx, 2, devc);
574 * Derive the sample period from the sample rate as well as the
575 * number of samples that the device will communicate within
576 * an "event" (memory organization internal to the device).
579 devc->num_channels = num_channels;
580 devc->cur_samplerate = samplerate;
581 devc->samples_per_event = 16 / devc->num_channels;
582 devc->state.state = SIGMA_IDLE;
586 * Support for "limit_samples" is implemented by stopping
587 * acquisition after a corresponding period of time.
588 * Re-calculate that period of time, in case the limit is
589 * set first and the samplerate gets (re-)configured later.
591 if (ret == SR_OK && devc->limit_samples) {
593 msecs = sigma_limit_samples_to_msec(devc, devc->limit_samples);
594 devc->limit_msec = msecs;
601 * In 100 and 200 MHz mode, only a single pin rising/falling can be
602 * set as trigger. In other modes, two rising/falling triggers can be set,
603 * in addition to value/mask trigger for any number of channels.
605 * The Sigma supports complex triggers using boolean expressions, but this
606 * has not been implemented yet.
608 SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi)
610 struct dev_context *devc;
611 struct sr_trigger *trigger;
612 struct sr_trigger_stage *stage;
613 struct sr_trigger_match *match;
615 int channelbit, trigger_set;
618 memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
619 if (!(trigger = sr_session_trigger_get(sdi->session)))
623 for (l = trigger->stages; l; l = l->next) {
625 for (m = stage->matches; m; m = m->next) {
627 if (!match->channel->enabled)
628 /* Ignore disabled channels with a trigger. */
630 channelbit = 1 << (match->channel->index);
631 if (devc->cur_samplerate >= SR_MHZ(100)) {
632 /* Fast trigger support. */
634 sr_err("Only a single pin trigger is "
635 "supported in 100 and 200MHz mode.");
638 if (match->match == SR_TRIGGER_FALLING)
639 devc->trigger.fallingmask |= channelbit;
640 else if (match->match == SR_TRIGGER_RISING)
641 devc->trigger.risingmask |= channelbit;
643 sr_err("Only rising/falling trigger is "
644 "supported in 100 and 200MHz mode.");
650 /* Simple trigger support (event). */
651 if (match->match == SR_TRIGGER_ONE) {
652 devc->trigger.simplevalue |= channelbit;
653 devc->trigger.simplemask |= channelbit;
654 } else if (match->match == SR_TRIGGER_ZERO) {
655 devc->trigger.simplevalue &= ~channelbit;
656 devc->trigger.simplemask |= channelbit;
657 } else if (match->match == SR_TRIGGER_FALLING) {
658 devc->trigger.fallingmask |= channelbit;
660 } else if (match->match == SR_TRIGGER_RISING) {
661 devc->trigger.risingmask |= channelbit;
666 * Actually, Sigma supports 2 rising/falling triggers,
667 * but they are ORed and the current trigger syntax
668 * does not permit ORed triggers.
670 if (trigger_set > 1) {
671 sr_err("Only 1 rising/falling trigger "
682 /* Software trigger to determine exact trigger position. */
683 static int get_trigger_offset(uint8_t *samples, uint16_t last_sample,
684 struct sigma_trigger *t)
689 for (i = 0; i < 8; i++) {
691 last_sample = sample;
692 sample = samples[2 * i] | (samples[2 * i + 1] << 8);
694 /* Simple triggers. */
695 if ((sample & t->simplemask) != t->simplevalue)
699 if (((last_sample & t->risingmask) != 0) ||
700 ((sample & t->risingmask) != t->risingmask))
704 if ((last_sample & t->fallingmask) != t->fallingmask ||
705 (sample & t->fallingmask) != 0)
711 /* If we did not match, return original trigger pos. */
716 * Return the timestamp of "DRAM cluster".
718 static uint16_t sigma_dram_cluster_ts(struct sigma_dram_cluster *cluster)
720 return (cluster->timestamp_hi << 8) | cluster->timestamp_lo;
724 * Return one 16bit data entity of a DRAM cluster at the specified index.
726 static uint16_t sigma_dram_cluster_data(struct sigma_dram_cluster *cl, int idx)
731 sample |= cl->samples[idx].sample_lo << 0;
732 sample |= cl->samples[idx].sample_hi << 8;
733 sample = (sample >> 8) | (sample << 8);
738 * Deinterlace sample data that was retrieved at 100MHz samplerate.
739 * One 16bit item contains two samples of 8bits each. The bits of
740 * multiple samples are interleaved.
742 static uint16_t sigma_deinterlace_100mhz_data(uint16_t indata, int idx)
748 outdata |= (indata >> (0 * 2 - 0)) & (1 << 0);
749 outdata |= (indata >> (1 * 2 - 1)) & (1 << 1);
750 outdata |= (indata >> (2 * 2 - 2)) & (1 << 2);
751 outdata |= (indata >> (3 * 2 - 3)) & (1 << 3);
752 outdata |= (indata >> (4 * 2 - 4)) & (1 << 4);
753 outdata |= (indata >> (5 * 2 - 5)) & (1 << 5);
754 outdata |= (indata >> (6 * 2 - 6)) & (1 << 6);
755 outdata |= (indata >> (7 * 2 - 7)) & (1 << 7);
760 * Deinterlace sample data that was retrieved at 200MHz samplerate.
761 * One 16bit item contains four samples of 4bits each. The bits of
762 * multiple samples are interleaved.
764 static uint16_t sigma_deinterlace_200mhz_data(uint16_t indata, int idx)
770 outdata |= (indata >> (0 * 4 - 0)) & (1 << 0);
771 outdata |= (indata >> (1 * 4 - 1)) & (1 << 1);
772 outdata |= (indata >> (2 * 4 - 2)) & (1 << 2);
773 outdata |= (indata >> (3 * 4 - 3)) & (1 << 3);
777 static void store_sr_sample(uint8_t *samples, int idx, uint16_t data)
779 samples[2 * idx + 0] = (data >> 0) & 0xff;
780 samples[2 * idx + 1] = (data >> 8) & 0xff;
784 * Local wrapper around sr_session_send() calls. Make sure to not send
785 * more samples to the session's datafeed than what was requested by a
786 * previously configured (optional) sample count.
788 static void sigma_session_send(struct sr_dev_inst *sdi,
789 struct sr_datafeed_packet *packet)
791 struct dev_context *devc;
792 struct sr_datafeed_logic *logic;
796 if (devc->limit_samples) {
797 logic = (void *)packet->payload;
798 send_now = logic->length / logic->unitsize;
799 if (devc->sent_samples + send_now > devc->limit_samples) {
800 send_now = devc->limit_samples - devc->sent_samples;
801 logic->length = send_now * logic->unitsize;
805 devc->sent_samples += send_now;
808 sr_session_send(sdi, packet);
812 * This size translates to: event count (1K events per cluster), times
813 * the sample width (unitsize, 16bits per event), times the maximum
814 * number of samples per event.
816 #define SAMPLES_BUFFER_SIZE (1024 * 2 * 4)
818 static void sigma_decode_dram_cluster(struct sigma_dram_cluster *dram_cluster,
819 unsigned int events_in_cluster,
820 unsigned int triggered,
821 struct sr_dev_inst *sdi)
823 struct dev_context *devc = sdi->priv;
824 struct sigma_state *ss = &devc->state;
825 struct sr_datafeed_packet packet;
826 struct sr_datafeed_logic logic;
827 uint16_t tsdiff, ts, sample, item16;
828 uint8_t samples[SAMPLES_BUFFER_SIZE];
830 size_t send_count, trig_count;
834 ts = sigma_dram_cluster_ts(dram_cluster);
835 tsdiff = ts - ss->lastts;
836 ss->lastts = ts + EVENTS_PER_CLUSTER;
838 packet.type = SR_DF_LOGIC;
839 packet.payload = &logic;
841 logic.data = samples;
844 * If this cluster is not adjacent to the previously received
845 * cluster, then send the appropriate number of samples with the
846 * previous values to the sigrok session. This "decodes RLE".
848 for (ts = 0; ts < tsdiff; ts++) {
850 store_sr_sample(samples, i, ss->lastsample);
853 * If we have 1024 samples ready or we're at the
854 * end of submitting the padding samples, submit
855 * the packet to Sigrok. Since constant data is
856 * sent, duplication of data for rates above 50MHz
859 if ((i == 1023) || (ts == tsdiff - 1)) {
860 logic.length = (i + 1) * logic.unitsize;
861 for (j = 0; j < devc->samples_per_event; j++)
862 sigma_session_send(sdi, &packet);
867 * Parse the samples in current cluster and prepare them
868 * to be submitted to Sigrok. Cope with memory layouts that
869 * vary with the samplerate.
871 send_ptr = &samples[0];
874 for (i = 0; i < events_in_cluster; i++) {
875 item16 = sigma_dram_cluster_data(dram_cluster, i);
876 if (devc->cur_samplerate == SR_MHZ(200)) {
877 sample = sigma_deinterlace_200mhz_data(item16, 0);
878 store_sr_sample(samples, send_count++, sample);
879 sample = sigma_deinterlace_200mhz_data(item16, 1);
880 store_sr_sample(samples, send_count++, sample);
881 sample = sigma_deinterlace_200mhz_data(item16, 2);
882 store_sr_sample(samples, send_count++, sample);
883 sample = sigma_deinterlace_200mhz_data(item16, 3);
884 store_sr_sample(samples, send_count++, sample);
885 } else if (devc->cur_samplerate == SR_MHZ(100)) {
886 sample = sigma_deinterlace_100mhz_data(item16, 0);
887 store_sr_sample(samples, send_count++, sample);
888 sample = sigma_deinterlace_100mhz_data(item16, 1);
889 store_sr_sample(samples, send_count++, sample);
892 store_sr_sample(samples, send_count++, sample);
897 * If a trigger position applies, then provide the datafeed with
898 * the first part of data up to that position, then send the
901 int trigger_offset = 0;
904 * Trigger is not always accurate to sample because of
905 * pipeline delay. However, it always triggers before
906 * the actual event. We therefore look at the next
907 * samples to pinpoint the exact position of the trigger.
909 trigger_offset = get_trigger_offset(samples,
910 ss->lastsample, &devc->trigger);
912 if (trigger_offset > 0) {
913 trig_count = trigger_offset * devc->samples_per_event;
914 packet.type = SR_DF_LOGIC;
915 logic.length = trig_count * logic.unitsize;
916 sigma_session_send(sdi, &packet);
917 send_ptr += trig_count * logic.unitsize;
918 send_count -= trig_count;
921 /* Only send trigger if explicitly enabled. */
922 if (devc->use_triggers) {
923 packet.type = SR_DF_TRIGGER;
924 sr_session_send(sdi, &packet);
929 * Send the data after the trigger, or all of the received data
930 * if no trigger position applies.
933 packet.type = SR_DF_LOGIC;
934 logic.length = send_count * logic.unitsize;
935 logic.data = send_ptr;
936 sigma_session_send(sdi, &packet);
939 ss->lastsample = sample;
943 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
944 * Each event is 20ns apart, and can contain multiple samples.
946 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
947 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
948 * For 50 MHz and below, events contain one sample for each channel,
949 * spread 20 ns apart.
951 static int decode_chunk_ts(struct sigma_dram_line *dram_line,
952 uint16_t events_in_line,
953 uint32_t trigger_event,
954 struct sr_dev_inst *sdi)
956 struct sigma_dram_cluster *dram_cluster;
957 struct dev_context *devc;
958 unsigned int clusters_in_line;
959 unsigned int events_in_cluster;
961 uint32_t trigger_cluster, triggered;
964 clusters_in_line = events_in_line;
965 clusters_in_line += EVENTS_PER_CLUSTER - 1;
966 clusters_in_line /= EVENTS_PER_CLUSTER;
967 trigger_cluster = ~0;
970 /* Check if trigger is in this chunk. */
971 if (trigger_event < (64 * 7)) {
972 if (devc->cur_samplerate <= SR_MHZ(50)) {
973 trigger_event -= MIN(EVENTS_PER_CLUSTER - 1,
977 /* Find in which cluster the trigger occurred. */
978 trigger_cluster = trigger_event / EVENTS_PER_CLUSTER;
981 /* For each full DRAM cluster. */
982 for (i = 0; i < clusters_in_line; i++) {
983 dram_cluster = &dram_line->cluster[i];
985 /* The last cluster might not be full. */
986 if ((i == clusters_in_line - 1) &&
987 (events_in_line % EVENTS_PER_CLUSTER)) {
988 events_in_cluster = events_in_line % EVENTS_PER_CLUSTER;
990 events_in_cluster = EVENTS_PER_CLUSTER;
993 triggered = (i == trigger_cluster);
994 sigma_decode_dram_cluster(dram_cluster, events_in_cluster,
1001 static int download_capture(struct sr_dev_inst *sdi)
1003 const uint32_t chunks_per_read = 32;
1005 struct dev_context *devc;
1006 struct sigma_dram_line *dram_line;
1008 uint32_t stoppos, triggerpos;
1011 uint32_t dl_lines_total, dl_lines_curr, dl_lines_done;
1012 uint32_t dl_first_line, dl_line;
1013 uint32_t dl_events_in_line;
1014 uint32_t trg_line, trg_event;
1017 dl_events_in_line = 64 * 7;
1019 dram_line = g_try_malloc0(chunks_per_read * sizeof(*dram_line));
1023 sr_info("Downloading sample data.");
1024 devc->state.state = SIGMA_DOWNLOAD;
1027 * Ask the hardware to stop data acquisition. Reception of the
1028 * FORCESTOP request makes the hardware "disable RLE" (store
1029 * clusters to DRAM regardless of whether pin state changes) and
1030 * raise the POSTTRIGGERED flag.
1032 sigma_set_register(WRITE_MODE, WMR_FORCESTOP | WMR_SDRAMWRITEEN, devc);
1034 modestatus = sigma_get_register(READ_MODE, devc);
1035 } while (!(modestatus & RMR_POSTTRIGGERED));
1037 /* Set SDRAM Read Enable. */
1038 sigma_set_register(WRITE_MODE, WMR_SDRAMREADEN, devc);
1040 /* Get the current position. */
1041 sigma_read_pos(&stoppos, &triggerpos, devc);
1043 /* Check if trigger has fired. */
1044 modestatus = sigma_get_register(READ_MODE, devc);
1047 if (modestatus & RMR_TRIGGERED) {
1048 trg_line = triggerpos >> 9;
1049 trg_event = triggerpos & 0x1ff;
1052 devc->sent_samples = 0;
1055 * Determine how many "DRAM lines" of 1024 bytes each we need to
1056 * retrieve from the Sigma hardware, so that we have a complete
1057 * set of samples. Note that the last line need not contain 64
1058 * clusters, it might be partially filled only.
1060 * When RMR_ROUND is set, the circular buffer in DRAM has wrapped
1061 * around. Since the status of the very next line is uncertain in
1062 * that case, we skip it and start reading from the next line. The
1063 * circular buffer has 32K lines (0x8000).
1065 dl_lines_total = (stoppos >> 9) + 1;
1066 if (modestatus & RMR_ROUND) {
1067 dl_first_line = dl_lines_total + 1;
1068 dl_lines_total = 0x8000 - 2;
1073 while (dl_lines_total > dl_lines_done) {
1074 /* We can download only up-to 32 DRAM lines in one go! */
1075 dl_lines_curr = MIN(chunks_per_read, dl_lines_total - dl_lines_done);
1077 dl_line = dl_first_line + dl_lines_done;
1079 bufsz = sigma_read_dram(dl_line, dl_lines_curr,
1080 (uint8_t *)dram_line, devc);
1081 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1084 /* This is the first DRAM line, so find the initial timestamp. */
1085 if (dl_lines_done == 0) {
1086 devc->state.lastts =
1087 sigma_dram_cluster_ts(&dram_line[0].cluster[0]);
1088 devc->state.lastsample = 0;
1091 for (i = 0; i < dl_lines_curr; i++) {
1092 uint32_t trigger_event = ~0;
1093 /* The last "DRAM line" can be only partially full. */
1094 if (dl_lines_done + i == dl_lines_total - 1)
1095 dl_events_in_line = stoppos & 0x1ff;
1097 /* Test if the trigger happened on this line. */
1098 if (dl_lines_done + i == trg_line)
1099 trigger_event = trg_event;
1101 decode_chunk_ts(dram_line + i, dl_events_in_line,
1102 trigger_event, sdi);
1105 dl_lines_done += dl_lines_curr;
1109 std_session_send_df_end(sdi);
1111 devc->state.state = SIGMA_IDLE;
1112 sr_dev_acquisition_stop(sdi);
1118 * Periodically check the Sigma status when in CAPTURE mode. This routine
1119 * checks whether the configured sample count or sample time have passed,
1120 * and will stop acquisition and download the acquired samples.
1122 static int sigma_capture_mode(struct sr_dev_inst *sdi)
1124 struct dev_context *devc;
1125 uint64_t running_msec;
1126 uint64_t current_time;
1131 * Check if the selected sampling duration passed. Sample count
1132 * limits are covered by this enforced timeout as well.
1134 current_time = g_get_monotonic_time();
1135 running_msec = (current_time - devc->start_time) / 1000;
1136 if (running_msec >= devc->limit_msec)
1137 return download_capture(sdi);
1142 SR_PRIV int sigma_receive_data(int fd, int revents, void *cb_data)
1144 struct sr_dev_inst *sdi;
1145 struct dev_context *devc;
1153 if (devc->state.state == SIGMA_IDLE)
1157 * When the application has requested to stop the acquisition,
1158 * then immediately start downloading sample data. Otherwise
1159 * keep checking configured limits which will terminate the
1160 * acquisition and initiate download.
1162 if (devc->state.state == SIGMA_STOPPING)
1163 return download_capture(sdi);
1164 if (devc->state.state == SIGMA_CAPTURE)
1165 return sigma_capture_mode(sdi);
1170 /* Build a LUT entry used by the trigger functions. */
1171 static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1175 /* For each quad channel. */
1176 for (i = 0; i < 4; i++) {
1179 /* For each bit in LUT. */
1180 for (j = 0; j < 16; j++)
1182 /* For each channel in quad. */
1183 for (k = 0; k < 4; k++) {
1184 bit = 1 << (i * 4 + k);
1186 /* Set bit in entry */
1187 if ((mask & bit) && ((!(value & bit)) !=
1189 entry[i] &= ~(1 << j);
1194 /* Add a logical function to LUT mask. */
1195 static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1196 int index, int neg, uint16_t *mask)
1199 int x[2][2], tmp, a, b, aset, bset, rset;
1201 memset(x, 0, 4 * sizeof(int));
1203 /* Trigger detect condition. */
1233 case OP_NOTRISEFALL:
1239 /* Transpose if neg is set. */
1241 for (i = 0; i < 2; i++) {
1242 for (j = 0; j < 2; j++) {
1244 x[i][j] = x[1 - i][1 - j];
1245 x[1 - i][1 - j] = tmp;
1250 /* Update mask with function. */
1251 for (i = 0; i < 16; i++) {
1252 a = (i >> (2 * index + 0)) & 1;
1253 b = (i >> (2 * index + 1)) & 1;
1255 aset = (*mask >> i) & 1;
1259 if (func == FUNC_AND || func == FUNC_NAND)
1261 else if (func == FUNC_OR || func == FUNC_NOR)
1263 else if (func == FUNC_XOR || func == FUNC_NXOR)
1266 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1277 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1278 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1279 * set at any time, but a full mask and value can be set (0/1).
1281 SR_PRIV int sigma_build_basic_trigger(struct triggerlut *lut, struct dev_context *devc)
1284 uint16_t masks[2] = { 0, 0 };
1286 memset(lut, 0, sizeof(struct triggerlut));
1288 /* Constant for simple triggers. */
1291 /* Value/mask trigger support. */
1292 build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask,
1295 /* Rise/fall trigger support. */
1296 for (i = 0, j = 0; i < 16; i++) {
1297 if (devc->trigger.risingmask & (1 << i) ||
1298 devc->trigger.fallingmask & (1 << i))
1299 masks[j++] = 1 << i;
1302 build_lut_entry(masks[0], masks[0], lut->m0d);
1303 build_lut_entry(masks[1], masks[1], lut->m1d);
1305 /* Add glue logic */
1306 if (masks[0] || masks[1]) {
1307 /* Transition trigger. */
1308 if (masks[0] & devc->trigger.risingmask)
1309 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1310 if (masks[0] & devc->trigger.fallingmask)
1311 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1312 if (masks[1] & devc->trigger.risingmask)
1313 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1314 if (masks[1] & devc->trigger.fallingmask)
1315 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1317 /* Only value/mask trigger. */
1321 /* Triggertype: event. */
1322 lut->params.selres = 3;