2 * This file is part of the libsigrok project.
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
27 #include <glib/gstdio.h>
31 #include "libsigrok.h"
32 #include "libsigrok-internal.h"
33 #include "asix-sigma.h"
35 #define USB_VENDOR 0xa600
36 #define USB_PRODUCT 0xa000
37 #define USB_DESCRIPTION "ASIX SIGMA"
38 #define USB_VENDOR_NAME "ASIX"
39 #define USB_MODEL_NAME "SIGMA"
41 SR_PRIV struct sr_dev_driver asix_sigma_driver_info;
42 static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data);
45 * The ASIX Sigma supports arbitrary integer frequency divider in
46 * the 50MHz mode. The divider is in range 1...256 , allowing for
47 * very precise sampling rate selection. This driver supports only
48 * a subset of the sampling rates.
50 static const uint64_t samplerates[] = {
51 SR_KHZ(200), /* div=250 */
52 SR_KHZ(250), /* div=200 */
53 SR_KHZ(500), /* div=100 */
54 SR_MHZ(1), /* div=50 */
55 SR_MHZ(5), /* div=10 */
56 SR_MHZ(10), /* div=5 */
57 SR_MHZ(25), /* div=2 */
58 SR_MHZ(50), /* div=1 */
59 SR_MHZ(100), /* Special FW needed */
60 SR_MHZ(200), /* Special FW needed */
64 * Channel numbers seem to go from 1-16, according to this image:
65 * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
66 * (the cable has two additional GND pins, and a TI and TO pin)
68 static const char *channel_names[] = {
69 "1", "2", "3", "4", "5", "6", "7", "8",
70 "9", "10", "11", "12", "13", "14", "15", "16",
73 static const uint32_t drvopts[] = {
74 SR_CONF_LOGIC_ANALYZER,
77 static const uint32_t devopts[] = {
78 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
79 SR_CONF_LIMIT_SAMPLES | SR_CONF_SET,
80 SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
81 SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
82 SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET,
85 static const int32_t trigger_matches[] = {
92 static const char *sigma_firmware_files[] = {
93 /* 50 MHz, supports 8 bit fractions */
94 FIRMWARE_DIR "/asix-sigma-50.fw",
96 FIRMWARE_DIR "/asix-sigma-100.fw",
98 FIRMWARE_DIR "/asix-sigma-200.fw",
99 /* Synchronous clock from pin */
100 FIRMWARE_DIR "/asix-sigma-50sync.fw",
101 /* Frequency counter */
102 FIRMWARE_DIR "/asix-sigma-phasor.fw",
105 static int sigma_read(void *buf, size_t size, struct dev_context *devc)
109 ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size);
111 sr_err("ftdi_read_data failed: %s",
112 ftdi_get_error_string(&devc->ftdic));
118 static int sigma_write(void *buf, size_t size, struct dev_context *devc)
122 ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size);
124 sr_err("ftdi_write_data failed: %s",
125 ftdi_get_error_string(&devc->ftdic));
126 } else if ((size_t) ret != size) {
127 sr_err("ftdi_write_data did not complete write.");
133 static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
134 struct dev_context *devc)
137 uint8_t buf[len + 2];
140 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
141 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
143 for (i = 0; i < len; ++i) {
144 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
145 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
148 return sigma_write(buf, idx, devc);
151 static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc)
153 return sigma_write_register(reg, &value, 1, devc);
156 static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
157 struct dev_context *devc)
161 buf[0] = REG_ADDR_LOW | (reg & 0xf);
162 buf[1] = REG_ADDR_HIGH | (reg >> 4);
163 buf[2] = REG_READ_ADDR;
165 sigma_write(buf, sizeof(buf), devc);
167 return sigma_read(data, len, devc);
170 static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc)
174 if (1 != sigma_read_register(reg, &value, 1, devc)) {
175 sr_err("sigma_get_register: 1 byte expected");
182 static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
183 struct dev_context *devc)
186 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
188 REG_READ_ADDR | NEXT_REG,
189 REG_READ_ADDR | NEXT_REG,
190 REG_READ_ADDR | NEXT_REG,
191 REG_READ_ADDR | NEXT_REG,
192 REG_READ_ADDR | NEXT_REG,
193 REG_READ_ADDR | NEXT_REG,
197 sigma_write(buf, sizeof(buf), devc);
199 sigma_read(result, sizeof(result), devc);
201 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
202 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
204 /* Not really sure why this must be done, but according to spec. */
205 if ((--*stoppos & 0x1ff) == 0x1ff)
208 if ((*--triggerpos & 0x1ff) == 0x1ff)
214 static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
215 uint8_t *data, struct dev_context *devc)
221 /* Send the startchunk. Index start with 1. */
222 buf[0] = startchunk >> 8;
223 buf[1] = startchunk & 0xff;
224 sigma_write_register(WRITE_MEMROW, buf, 2, devc);
227 buf[idx++] = REG_DRAM_BLOCK;
228 buf[idx++] = REG_DRAM_WAIT_ACK;
230 for (i = 0; i < numchunks; ++i) {
231 /* Alternate bit to copy from DRAM to cache. */
232 if (i != (numchunks - 1))
233 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
235 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
237 if (i != (numchunks - 1))
238 buf[idx++] = REG_DRAM_WAIT_ACK;
241 sigma_write(buf, idx, devc);
243 return sigma_read(data, numchunks * CHUNK_SIZE, devc);
246 /* Upload trigger look-up tables to Sigma. */
247 static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc)
253 /* Transpose the table and send to Sigma. */
254 for (i = 0; i < 16; ++i) {
259 if (lut->m2d[0] & bit)
261 if (lut->m2d[1] & bit)
263 if (lut->m2d[2] & bit)
265 if (lut->m2d[3] & bit)
275 if (lut->m0d[0] & bit)
277 if (lut->m0d[1] & bit)
279 if (lut->m0d[2] & bit)
281 if (lut->m0d[3] & bit)
284 if (lut->m1d[0] & bit)
286 if (lut->m1d[1] & bit)
288 if (lut->m1d[2] & bit)
290 if (lut->m1d[3] & bit)
293 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
295 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
298 /* Send the parameters */
299 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
300 sizeof(lut->params), devc);
305 static void clear_helper(void *priv)
307 struct dev_context *devc;
311 ftdi_deinit(&devc->ftdic);
314 static int dev_clear(const struct sr_dev_driver *di)
316 return std_dev_clear(di, clear_helper);
319 static int init(struct sr_dev_driver *di, struct sr_context *sr_ctx)
321 return std_init(sr_ctx, di, LOG_PREFIX);
324 static GSList *scan(struct sr_dev_driver *di, GSList *options)
326 struct sr_dev_inst *sdi;
327 struct drv_context *drvc;
328 struct dev_context *devc;
330 struct ftdi_device_list *devlist;
342 devc = g_malloc0(sizeof(struct dev_context));
344 ftdi_init(&devc->ftdic);
346 /* Look for SIGMAs. */
348 if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist,
349 USB_VENDOR, USB_PRODUCT)) <= 0) {
351 sr_err("ftdi_usb_find_all(): %d", ret);
355 /* Make sure it's a version 1 or 2 SIGMA. */
356 ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0,
357 serial_txt, sizeof(serial_txt));
358 sscanf(serial_txt, "%x", &serial);
360 if (serial < 0xa6010000 || serial > 0xa602ffff) {
361 sr_err("Only SIGMA and SIGMA2 are supported "
362 "in this version of libsigrok.");
366 sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
368 devc->cur_samplerate = samplerates[0];
370 devc->limit_msec = 0;
371 devc->cur_firmware = -1;
372 devc->num_channels = 0;
373 devc->samples_per_event = 0;
374 devc->capture_ratio = 50;
375 devc->use_triggers = 0;
377 /* Register SIGMA device. */
378 sdi = g_malloc0(sizeof(struct sr_dev_inst));
379 sdi->status = SR_ST_INITIALIZING;
380 sdi->vendor = g_strdup(USB_VENDOR_NAME);
381 sdi->model = g_strdup(USB_MODEL_NAME);
384 for (i = 0; i < ARRAY_SIZE(channel_names); i++)
385 sr_channel_new(sdi, i, SR_CHANNEL_LOGIC, TRUE,
388 devices = g_slist_append(devices, sdi);
389 drvc->instances = g_slist_append(drvc->instances, sdi);
392 /* We will open the device again when we need it. */
393 ftdi_list_free(&devlist);
398 ftdi_deinit(&devc->ftdic);
403 static GSList *dev_list(const struct sr_dev_driver *di)
405 return ((struct drv_context *)(di->priv))->instances;
409 * Configure the FPGA for bitbang mode.
410 * This sequence is documented in section 2. of the ASIX Sigma programming
411 * manual. This sequence is necessary to configure the FPGA in the Sigma
412 * into Bitbang mode, in which it can be programmed with the firmware.
414 static int sigma_fpga_init_bitbang(struct dev_context *devc)
416 uint8_t suicide[] = {
417 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
419 uint8_t init_array[] = {
420 0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01,
423 int i, ret, timeout = 10000;
426 /* Section 2. part 1), do the FPGA suicide. */
427 sigma_write(suicide, sizeof(suicide), devc);
428 sigma_write(suicide, sizeof(suicide), devc);
429 sigma_write(suicide, sizeof(suicide), devc);
430 sigma_write(suicide, sizeof(suicide), devc);
432 /* Section 2. part 2), do pulse on D1. */
433 sigma_write(init_array, sizeof(init_array), devc);
434 ftdi_usb_purge_buffers(&devc->ftdic);
436 /* Wait until the FPGA asserts D6/INIT_B. */
437 for (i = 0; i < timeout; i++) {
438 ret = sigma_read(&data, 1, devc);
441 /* Test if pin D6 got asserted. */
444 /* The D6 was not asserted yet, wait a bit. */
448 return SR_ERR_TIMEOUT;
452 * Configure the FPGA for logic-analyzer mode.
454 static int sigma_fpga_init_la(struct dev_context *devc)
456 /* Initialize the logic analyzer mode. */
457 uint8_t logic_mode_start[] = {
458 REG_ADDR_LOW | (READ_ID & 0xf),
459 REG_ADDR_HIGH | (READ_ID >> 8),
460 REG_READ_ADDR, /* Read ID register. */
462 REG_ADDR_LOW | (WRITE_TEST & 0xf),
464 REG_DATA_HIGH_WRITE | 0x5,
465 REG_READ_ADDR, /* Read scratch register. */
468 REG_DATA_HIGH_WRITE | 0xa,
469 REG_READ_ADDR, /* Read scratch register. */
471 REG_ADDR_LOW | (WRITE_MODE & 0xf),
473 REG_DATA_HIGH_WRITE | 0x8,
479 /* Initialize the logic analyzer mode. */
480 sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
482 /* Expect a 3 byte reply since we issued three READ requests. */
483 ret = sigma_read(result, 3, devc);
487 if (result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa)
492 sr_err("Configuration failed. Invalid reply received.");
497 * Read the firmware from a file and transform it into a series of bitbang
498 * pulses used to program the FPGA. Note that the *bb_cmd must be free()'d
499 * by the caller of this function.
501 static int sigma_fw_2_bitbang(const char *filename,
502 uint8_t **bb_cmd, gsize *bb_cmd_size)
506 gsize i, file_size, bb_size;
508 uint8_t *bb_stream, *bbs;
514 * Map the file and make the mapped buffer writable.
515 * NOTE: Using writable=TRUE does _NOT_ mean that file that is mapped
516 * will be modified. It will not be modified until someone uses
517 * g_file_set_contents() on it.
520 file = g_mapped_file_new(filename, TRUE, &error);
521 g_assert_no_error(error);
523 file_size = g_mapped_file_get_length(file);
524 firmware = g_mapped_file_get_contents(file);
527 /* Weird magic transformation below, I have no idea what it does. */
529 for (i = 0; i < file_size; i++) {
530 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
531 firmware[i] ^= imm & 0xff;
535 * Now that the firmware is "transformed", we will transcribe the
536 * firmware blob into a sequence of toggles of the Dx wires. This
537 * sequence will be fed directly into the Sigma, which must be in
538 * the FPGA bitbang programming mode.
541 /* Each bit of firmware is transcribed as two toggles of Dx wires. */
542 bb_size = file_size * 8 * 2;
543 bb_stream = (uint8_t *)g_try_malloc(bb_size);
545 sr_err("%s: Failed to allocate bitbang stream", __func__);
551 for (i = 0; i < file_size; i++) {
552 for (bit = 7; bit >= 0; bit--) {
553 v = (firmware[i] & (1 << bit)) ? 0x40 : 0x00;
559 /* The transformation completed successfully, return the result. */
561 *bb_cmd_size = bb_size;
564 g_mapped_file_unref(file);
568 static int upload_firmware(int firmware_idx, struct dev_context *devc)
574 const char *firmware = sigma_firmware_files[firmware_idx];
575 struct ftdi_context *ftdic = &devc->ftdic;
577 /* Make sure it's an ASIX SIGMA. */
578 ret = ftdi_usb_open_desc(ftdic, USB_VENDOR, USB_PRODUCT,
579 USB_DESCRIPTION, NULL);
581 sr_err("ftdi_usb_open failed: %s",
582 ftdi_get_error_string(ftdic));
586 ret = ftdi_set_bitmode(ftdic, 0xdf, BITMODE_BITBANG);
588 sr_err("ftdi_set_bitmode failed: %s",
589 ftdi_get_error_string(ftdic));
593 /* Four times the speed of sigmalogan - Works well. */
594 ret = ftdi_set_baudrate(ftdic, 750000);
596 sr_err("ftdi_set_baudrate failed: %s",
597 ftdi_get_error_string(ftdic));
601 /* Initialize the FPGA for firmware upload. */
602 ret = sigma_fpga_init_bitbang(devc);
606 /* Prepare firmware. */
607 ret = sigma_fw_2_bitbang(firmware, &buf, &buf_size);
609 sr_err("An error occured while reading the firmware: %s",
614 /* Upload firmare. */
615 sr_info("Uploading firmware file '%s'.", firmware);
616 sigma_write(buf, buf_size, devc);
620 ret = ftdi_set_bitmode(ftdic, 0x00, BITMODE_RESET);
622 sr_err("ftdi_set_bitmode failed: %s",
623 ftdi_get_error_string(ftdic));
627 ftdi_usb_purge_buffers(ftdic);
629 /* Discard garbage. */
630 while (sigma_read(&pins, 1, devc) == 1)
633 /* Initialize the FPGA for logic-analyzer mode. */
634 ret = sigma_fpga_init_la(devc);
638 devc->cur_firmware = firmware_idx;
640 sr_info("Firmware uploaded.");
645 static int dev_open(struct sr_dev_inst *sdi)
647 struct dev_context *devc;
652 /* Make sure it's an ASIX SIGMA. */
653 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
654 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
656 sr_err("ftdi_usb_open failed: %s",
657 ftdi_get_error_string(&devc->ftdic));
662 sdi->status = SR_ST_ACTIVE;
667 static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
669 struct dev_context *devc;
676 for (i = 0; i < ARRAY_SIZE(samplerates); i++) {
677 if (samplerates[i] == samplerate)
680 if (samplerates[i] == 0)
681 return SR_ERR_SAMPLERATE;
683 if (samplerate <= SR_MHZ(50)) {
684 ret = upload_firmware(0, devc);
685 devc->num_channels = 16;
686 } else if (samplerate == SR_MHZ(100)) {
687 ret = upload_firmware(1, devc);
688 devc->num_channels = 8;
689 } else if (samplerate == SR_MHZ(200)) {
690 ret = upload_firmware(2, devc);
691 devc->num_channels = 4;
695 devc->cur_samplerate = samplerate;
696 devc->period_ps = 1000000000000ULL / samplerate;
697 devc->samples_per_event = 16 / devc->num_channels;
698 devc->state.state = SIGMA_IDLE;
705 * In 100 and 200 MHz mode, only a single pin rising/falling can be
706 * set as trigger. In other modes, two rising/falling triggers can be set,
707 * in addition to value/mask trigger for any number of channels.
709 * The Sigma supports complex triggers using boolean expressions, but this
710 * has not been implemented yet.
712 static int convert_trigger(const struct sr_dev_inst *sdi)
714 struct dev_context *devc;
715 struct sr_trigger *trigger;
716 struct sr_trigger_stage *stage;
717 struct sr_trigger_match *match;
719 int channelbit, trigger_set;
722 memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
723 if (!(trigger = sr_session_trigger_get(sdi->session)))
727 for (l = trigger->stages; l; l = l->next) {
729 for (m = stage->matches; m; m = m->next) {
731 if (!match->channel->enabled)
732 /* Ignore disabled channels with a trigger. */
734 channelbit = 1 << (match->channel->index);
735 if (devc->cur_samplerate >= SR_MHZ(100)) {
736 /* Fast trigger support. */
738 sr_err("Only a single pin trigger is "
739 "supported in 100 and 200MHz mode.");
742 if (match->match == SR_TRIGGER_FALLING)
743 devc->trigger.fallingmask |= channelbit;
744 else if (match->match == SR_TRIGGER_RISING)
745 devc->trigger.risingmask |= channelbit;
747 sr_err("Only rising/falling trigger is "
748 "supported in 100 and 200MHz mode.");
754 /* Simple trigger support (event). */
755 if (match->match == SR_TRIGGER_ONE) {
756 devc->trigger.simplevalue |= channelbit;
757 devc->trigger.simplemask |= channelbit;
759 else if (match->match == SR_TRIGGER_ZERO) {
760 devc->trigger.simplevalue &= ~channelbit;
761 devc->trigger.simplemask |= channelbit;
763 else if (match->match == SR_TRIGGER_FALLING) {
764 devc->trigger.fallingmask |= channelbit;
767 else if (match->match == SR_TRIGGER_RISING) {
768 devc->trigger.risingmask |= channelbit;
773 * Actually, Sigma supports 2 rising/falling triggers,
774 * but they are ORed and the current trigger syntax
775 * does not permit ORed triggers.
777 if (trigger_set > 1) {
778 sr_err("Only 1 rising/falling trigger "
789 static int dev_close(struct sr_dev_inst *sdi)
791 struct dev_context *devc;
796 if (sdi->status == SR_ST_ACTIVE)
797 ftdi_usb_close(&devc->ftdic);
799 sdi->status = SR_ST_INACTIVE;
804 static int cleanup(const struct sr_dev_driver *di)
806 return dev_clear(di);
809 static int config_get(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
810 const struct sr_channel_group *cg)
812 struct dev_context *devc;
821 case SR_CONF_SAMPLERATE:
822 *data = g_variant_new_uint64(devc->cur_samplerate);
824 case SR_CONF_LIMIT_MSEC:
825 *data = g_variant_new_uint64(devc->limit_msec);
827 case SR_CONF_CAPTURE_RATIO:
828 *data = g_variant_new_uint64(devc->capture_ratio);
837 static int config_set(uint32_t key, GVariant *data, const struct sr_dev_inst *sdi,
838 const struct sr_channel_group *cg)
840 struct dev_context *devc;
846 if (sdi->status != SR_ST_ACTIVE)
847 return SR_ERR_DEV_CLOSED;
853 case SR_CONF_SAMPLERATE:
854 ret = set_samplerate(sdi, g_variant_get_uint64(data));
856 case SR_CONF_LIMIT_MSEC:
857 tmp = g_variant_get_uint64(data);
859 devc->limit_msec = g_variant_get_uint64(data);
863 case SR_CONF_LIMIT_SAMPLES:
864 tmp = g_variant_get_uint64(data);
865 devc->limit_msec = tmp * 1000 / devc->cur_samplerate;
867 case SR_CONF_CAPTURE_RATIO:
868 tmp = g_variant_get_uint64(data);
870 devc->capture_ratio = tmp;
881 static int config_list(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
882 const struct sr_channel_group *cg)
891 case SR_CONF_DEVICE_OPTIONS:
893 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
894 drvopts, ARRAY_SIZE(drvopts), sizeof(uint32_t));
896 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
897 devopts, ARRAY_SIZE(devopts), sizeof(uint32_t));
899 case SR_CONF_SAMPLERATE:
900 g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}"));
901 gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates,
902 ARRAY_SIZE(samplerates), sizeof(uint64_t));
903 g_variant_builder_add(&gvb, "{sv}", "samplerates", gvar);
904 *data = g_variant_builder_end(&gvb);
906 case SR_CONF_TRIGGER_MATCH:
907 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
908 trigger_matches, ARRAY_SIZE(trigger_matches),
918 /* Software trigger to determine exact trigger position. */
919 static int get_trigger_offset(uint8_t *samples, uint16_t last_sample,
920 struct sigma_trigger *t)
925 for (i = 0; i < 8; ++i) {
927 last_sample = sample;
928 sample = samples[2 * i] | (samples[2 * i + 1] << 8);
930 /* Simple triggers. */
931 if ((sample & t->simplemask) != t->simplevalue)
935 if (((last_sample & t->risingmask) != 0) ||
936 ((sample & t->risingmask) != t->risingmask))
940 if ((last_sample & t->fallingmask) != t->fallingmask ||
941 (sample & t->fallingmask) != 0)
947 /* If we did not match, return original trigger pos. */
952 * Return the timestamp of "DRAM cluster".
954 static uint16_t sigma_dram_cluster_ts(struct sigma_dram_cluster *cluster)
956 return (cluster->timestamp_hi << 8) | cluster->timestamp_lo;
959 static void sigma_decode_dram_cluster(struct sigma_dram_cluster *dram_cluster,
960 unsigned int events_in_cluster,
961 unsigned int triggered,
962 struct sr_dev_inst *sdi)
964 struct dev_context *devc = sdi->priv;
965 struct sigma_state *ss = &devc->state;
966 struct sr_datafeed_packet packet;
967 struct sr_datafeed_logic logic;
969 uint8_t samples[2048];
972 ts = sigma_dram_cluster_ts(dram_cluster);
973 tsdiff = ts - ss->lastts;
976 packet.type = SR_DF_LOGIC;
977 packet.payload = &logic;
979 logic.data = samples;
982 * First of all, send Sigrok a copy of the last sample from
983 * previous cluster as many times as needed to make up for
984 * the differential characteristics of data we get from the
985 * Sigma. Sigrok needs one sample of data per period.
987 * One DRAM cluster contains a timestamp and seven samples,
988 * the units of timestamp are "devc->period_ps" , the first
989 * sample in the cluster happens at the time of the timestamp
990 * and the remaining samples happen at timestamp +1...+6 .
992 for (ts = 0; ts < tsdiff - (EVENTS_PER_CLUSTER - 1); ts++) {
994 samples[2 * i + 0] = ss->lastsample & 0xff;
995 samples[2 * i + 1] = ss->lastsample >> 8;
998 * If we have 1024 samples ready or we're at the
999 * end of submitting the padding samples, submit
1000 * the packet to Sigrok.
1002 if ((i == 1023) || (ts == (tsdiff - EVENTS_PER_CLUSTER))) {
1003 logic.length = (i + 1) * logic.unitsize;
1004 sr_session_send(sdi, &packet);
1009 * Parse the samples in current cluster and prepare them
1010 * to be submitted to Sigrok.
1012 for (i = 0; i < events_in_cluster; i++) {
1013 samples[2 * i + 1] = dram_cluster->samples[i].sample_lo;
1014 samples[2 * i + 0] = dram_cluster->samples[i].sample_hi;
1017 /* Send data up to trigger point (if triggered). */
1018 int trigger_offset = 0;
1021 * Trigger is not always accurate to sample because of
1022 * pipeline delay. However, it always triggers before
1023 * the actual event. We therefore look at the next
1024 * samples to pinpoint the exact position of the trigger.
1026 trigger_offset = get_trigger_offset(samples,
1027 ss->lastsample, &devc->trigger);
1029 if (trigger_offset > 0) {
1030 packet.type = SR_DF_LOGIC;
1031 logic.length = trigger_offset * logic.unitsize;
1032 sr_session_send(sdi, &packet);
1033 events_in_cluster -= trigger_offset;
1036 /* Only send trigger if explicitly enabled. */
1037 if (devc->use_triggers) {
1038 packet.type = SR_DF_TRIGGER;
1039 sr_session_send(sdi, &packet);
1043 if (events_in_cluster > 0) {
1044 packet.type = SR_DF_LOGIC;
1045 logic.length = events_in_cluster * logic.unitsize;
1046 logic.data = samples + (trigger_offset * logic.unitsize);
1047 sr_session_send(sdi, &packet);
1051 samples[2 * (events_in_cluster - 1) + 0] |
1052 (samples[2 * (events_in_cluster - 1) + 1] << 8);
1057 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
1058 * Each event is 20ns apart, and can contain multiple samples.
1060 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
1061 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
1062 * For 50 MHz and below, events contain one sample for each channel,
1063 * spread 20 ns apart.
1065 static int decode_chunk_ts(struct sigma_dram_line *dram_line,
1066 uint16_t events_in_line,
1067 uint32_t trigger_event,
1068 struct sr_dev_inst *sdi)
1070 struct sigma_dram_cluster *dram_cluster;
1071 struct dev_context *devc = sdi->priv;
1072 unsigned int clusters_in_line =
1073 (events_in_line + (EVENTS_PER_CLUSTER - 1)) / EVENTS_PER_CLUSTER;
1074 unsigned int events_in_cluster;
1076 uint32_t trigger_cluster = ~0, triggered = 0;
1078 /* Check if trigger is in this chunk. */
1079 if (trigger_event < (64 * 7)) {
1080 if (devc->cur_samplerate <= SR_MHZ(50)) {
1081 trigger_event -= MIN(EVENTS_PER_CLUSTER - 1,
1085 /* Find in which cluster the trigger occured. */
1086 trigger_cluster = trigger_event / EVENTS_PER_CLUSTER;
1089 /* For each full DRAM cluster. */
1090 for (i = 0; i < clusters_in_line; i++) {
1091 dram_cluster = &dram_line->cluster[i];
1093 /* The last cluster might not be full. */
1094 if ((i == clusters_in_line - 1) &&
1095 (events_in_line % EVENTS_PER_CLUSTER)) {
1096 events_in_cluster = events_in_line % EVENTS_PER_CLUSTER;
1098 events_in_cluster = EVENTS_PER_CLUSTER;
1101 triggered = (i == trigger_cluster);
1102 sigma_decode_dram_cluster(dram_cluster, events_in_cluster,
1109 static int download_capture(struct sr_dev_inst *sdi)
1111 struct dev_context *devc = sdi->priv;
1112 const uint32_t chunks_per_read = 32;
1113 struct sigma_dram_line *dram_line;
1115 uint32_t stoppos, triggerpos;
1116 struct sr_datafeed_packet packet;
1120 uint32_t dl_lines_total, dl_lines_curr, dl_lines_done;
1121 uint32_t dl_events_in_line = 64 * 7;
1122 uint32_t trg_line = ~0, trg_event = ~0;
1124 dram_line = g_try_malloc0(chunks_per_read * sizeof(*dram_line));
1128 sr_info("Downloading sample data.");
1130 /* Stop acquisition. */
1131 sigma_set_register(WRITE_MODE, 0x11, devc);
1133 /* Set SDRAM Read Enable. */
1134 sigma_set_register(WRITE_MODE, 0x02, devc);
1136 /* Get the current position. */
1137 sigma_read_pos(&stoppos, &triggerpos, devc);
1139 /* Check if trigger has fired. */
1140 modestatus = sigma_get_register(READ_MODE, devc);
1141 if (modestatus & 0x20) {
1142 trg_line = triggerpos >> 9;
1143 trg_event = triggerpos & 0x1ff;
1147 * Determine how many 1024b "DRAM lines" do we need to read from the
1148 * Sigma so we have a complete set of samples. Note that the last
1149 * line can be only partial, containing less than 64 clusters.
1151 dl_lines_total = (stoppos >> 9) + 1;
1155 while (dl_lines_total > dl_lines_done) {
1156 /* We can download only up-to 32 DRAM lines in one go! */
1157 dl_lines_curr = MIN(chunks_per_read, dl_lines_total);
1159 bufsz = sigma_read_dram(dl_lines_done, dl_lines_curr,
1160 (uint8_t *)dram_line, devc);
1161 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1164 /* This is the first DRAM line, so find the initial timestamp. */
1165 if (dl_lines_done == 0) {
1166 devc->state.lastts =
1167 sigma_dram_cluster_ts(&dram_line[0].cluster[0]);
1168 devc->state.lastsample = 0;
1171 for (i = 0; i < dl_lines_curr; i++) {
1172 uint32_t trigger_event = ~0;
1173 /* The last "DRAM line" can be only partially full. */
1174 if (dl_lines_done + i == dl_lines_total - 1)
1175 dl_events_in_line = stoppos & 0x1ff;
1177 /* Test if the trigger happened on this line. */
1178 if (dl_lines_done + i == trg_line)
1179 trigger_event = trg_event;
1181 decode_chunk_ts(dram_line + i, dl_events_in_line,
1182 trigger_event, sdi);
1185 dl_lines_done += dl_lines_curr;
1189 packet.type = SR_DF_END;
1190 sr_session_send(sdi, &packet);
1192 dev_acquisition_stop(sdi, sdi);
1200 * Handle the Sigma when in CAPTURE mode. This function checks:
1201 * - Sampling time ended
1202 * - DRAM capacity overflow
1203 * This function triggers download of the samples from Sigma
1204 * in case either of the above conditions is true.
1206 static int sigma_capture_mode(struct sr_dev_inst *sdi)
1208 struct dev_context *devc = sdi->priv;
1210 uint64_t running_msec;
1213 uint32_t stoppos, triggerpos;
1215 /* Check if the selected sampling duration passed. */
1216 gettimeofday(&tv, 0);
1217 running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 +
1218 (tv.tv_usec - devc->start_tv.tv_usec) / 1000;
1219 if (running_msec >= devc->limit_msec)
1220 return download_capture(sdi);
1222 /* Get the position in DRAM to which the FPGA is writing now. */
1223 sigma_read_pos(&stoppos, &triggerpos, devc);
1224 /* Test if DRAM is full and if so, download the data. */
1225 if ((stoppos >> 9) == 32767)
1226 return download_capture(sdi);
1231 static int receive_data(int fd, int revents, void *cb_data)
1233 struct sr_dev_inst *sdi;
1234 struct dev_context *devc;
1242 if (devc->state.state == SIGMA_IDLE)
1245 if (devc->state.state == SIGMA_CAPTURE)
1246 return sigma_capture_mode(sdi);
1251 /* Build a LUT entry used by the trigger functions. */
1252 static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1256 /* For each quad channel. */
1257 for (i = 0; i < 4; ++i) {
1260 /* For each bit in LUT. */
1261 for (j = 0; j < 16; ++j)
1263 /* For each channel in quad. */
1264 for (k = 0; k < 4; ++k) {
1265 bit = 1 << (i * 4 + k);
1267 /* Set bit in entry */
1269 ((!(value & bit)) !=
1271 entry[i] &= ~(1 << j);
1276 /* Add a logical function to LUT mask. */
1277 static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1278 int index, int neg, uint16_t *mask)
1281 int x[2][2], tmp, a, b, aset, bset, rset;
1283 memset(x, 0, 4 * sizeof(int));
1285 /* Trigger detect condition. */
1315 case OP_NOTRISEFALL:
1321 /* Transpose if neg is set. */
1323 for (i = 0; i < 2; ++i) {
1324 for (j = 0; j < 2; ++j) {
1326 x[i][j] = x[1-i][1-j];
1332 /* Update mask with function. */
1333 for (i = 0; i < 16; ++i) {
1334 a = (i >> (2 * index + 0)) & 1;
1335 b = (i >> (2 * index + 1)) & 1;
1337 aset = (*mask >> i) & 1;
1341 if (func == FUNC_AND || func == FUNC_NAND)
1343 else if (func == FUNC_OR || func == FUNC_NOR)
1345 else if (func == FUNC_XOR || func == FUNC_NXOR)
1348 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1359 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1360 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1361 * set at any time, but a full mask and value can be set (0/1).
1363 static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc)
1366 uint16_t masks[2] = { 0, 0 };
1368 memset(lut, 0, sizeof(struct triggerlut));
1370 /* Contant for simple triggers. */
1373 /* Value/mask trigger support. */
1374 build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask,
1377 /* Rise/fall trigger support. */
1378 for (i = 0, j = 0; i < 16; ++i) {
1379 if (devc->trigger.risingmask & (1 << i) ||
1380 devc->trigger.fallingmask & (1 << i))
1381 masks[j++] = 1 << i;
1384 build_lut_entry(masks[0], masks[0], lut->m0d);
1385 build_lut_entry(masks[1], masks[1], lut->m1d);
1387 /* Add glue logic */
1388 if (masks[0] || masks[1]) {
1389 /* Transition trigger. */
1390 if (masks[0] & devc->trigger.risingmask)
1391 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1392 if (masks[0] & devc->trigger.fallingmask)
1393 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1394 if (masks[1] & devc->trigger.risingmask)
1395 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1396 if (masks[1] & devc->trigger.fallingmask)
1397 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1399 /* Only value/mask trigger. */
1403 /* Triggertype: event. */
1404 lut->params.selres = 3;
1409 static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data)
1411 struct dev_context *devc;
1412 struct clockselect_50 clockselect;
1413 int frac, triggerpin, ret;
1414 uint8_t triggerselect = 0;
1415 struct triggerinout triggerinout_conf;
1416 struct triggerlut lut;
1418 if (sdi->status != SR_ST_ACTIVE)
1419 return SR_ERR_DEV_CLOSED;
1423 if (convert_trigger(sdi) != SR_OK) {
1424 sr_err("Failed to configure triggers.");
1428 /* If the samplerate has not been set, default to 200 kHz. */
1429 if (devc->cur_firmware == -1) {
1430 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1434 /* Enter trigger programming mode. */
1435 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc);
1437 /* 100 and 200 MHz mode. */
1438 if (devc->cur_samplerate >= SR_MHZ(100)) {
1439 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc);
1441 /* Find which pin to trigger on from mask. */
1442 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1443 if ((devc->trigger.risingmask | devc->trigger.fallingmask) &
1447 /* Set trigger pin and light LED on trigger. */
1448 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1450 /* Default rising edge. */
1451 if (devc->trigger.fallingmask)
1452 triggerselect |= 1 << 3;
1454 /* All other modes. */
1455 } else if (devc->cur_samplerate <= SR_MHZ(50)) {
1456 build_basic_trigger(&lut, devc);
1458 sigma_write_trigger_lut(&lut, devc);
1460 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1463 /* Setup trigger in and out pins to default values. */
1464 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1465 triggerinout_conf.trgout_bytrigger = 1;
1466 triggerinout_conf.trgout_enable = 1;
1468 sigma_write_register(WRITE_TRIGGER_OPTION,
1469 (uint8_t *) &triggerinout_conf,
1470 sizeof(struct triggerinout), devc);
1472 /* Go back to normal mode. */
1473 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc);
1475 /* Set clock select register. */
1476 if (devc->cur_samplerate == SR_MHZ(200))
1477 /* Enable 4 channels. */
1478 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc);
1479 else if (devc->cur_samplerate == SR_MHZ(100))
1480 /* Enable 8 channels. */
1481 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc);
1484 * 50 MHz mode (or fraction thereof). Any fraction down to
1485 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1487 frac = SR_MHZ(50) / devc->cur_samplerate - 1;
1489 clockselect.async = 0;
1490 clockselect.fraction = frac;
1491 clockselect.disabled_channels = 0;
1493 sigma_write_register(WRITE_CLOCK_SELECT,
1494 (uint8_t *) &clockselect,
1495 sizeof(clockselect), devc);
1498 /* Setup maximum post trigger time. */
1499 sigma_set_register(WRITE_POST_TRIGGER,
1500 (devc->capture_ratio * 255) / 100, devc);
1502 /* Start acqusition. */
1503 gettimeofday(&devc->start_tv, 0);
1504 sigma_set_register(WRITE_MODE, 0x0d, devc);
1506 devc->cb_data = cb_data;
1508 /* Send header packet to the session bus. */
1509 std_session_send_df_header(sdi, LOG_PREFIX);
1511 /* Add capture source. */
1512 sr_session_source_add(sdi->session, 0, G_IO_IN, 10, receive_data, (void *)sdi);
1514 devc->state.state = SIGMA_CAPTURE;
1519 static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
1521 struct dev_context *devc;
1526 devc->state.state = SIGMA_IDLE;
1528 sr_session_source_remove(sdi->session, 0);
1533 SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
1534 .name = "asix-sigma",
1535 .longname = "ASIX SIGMA/SIGMA2",
1540 .dev_list = dev_list,
1541 .dev_clear = dev_clear,
1542 .config_get = config_get,
1543 .config_set = config_set,
1544 .config_list = config_list,
1545 .dev_open = dev_open,
1546 .dev_close = dev_close,
1547 .dev_acquisition_start = dev_acquisition_start,
1548 .dev_acquisition_stop = dev_acquisition_stop,