hardware/zeroplus-logic-cube/analyzer.c

   1 /*
   2  * This file is part of the sigrok project.
   3  *
   4  * Copyright (C) 2010 Sven Peter <sven@fail0verflow.com>
   5  * Copyright (C) 2010 Haxx Enterprises <bushing@gmail.com>
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or
   9  * without modification, are permitted provided that the following
  10  * conditions are met:
  11  *
  12  * * Redistributions of source code must retain the above copyright notice,
  13  *   this list of conditions and the following disclaimer.
  14  *
  15  * * Redistributions in binary form must reproduce the above copyright notice,
  16  *   this list of conditions and the following disclaimer in the documentation
  17  *   and/or other materials provided with the distribution.
  18  *
  19  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  23  *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  29  *  THE POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 #include <assert.h>
  33 #include "analyzer.h"
  34 #include "gl_usb.h"
  35
  36 enum {
  37         HARD_DATA_CHECK_SUM             = 0x00,
  38         PASS_WORD,
  39
  40         DEV_ID0                         = 0x10,
  41         DEV_ID1,
  42
  43         START_STATUS                    = 0x20,
  44         DEV_STATUS                      = 0x21,
  45         FREQUENCY_REG0                  = 0x30,
  46         FREQUENCY_REG1,
  47         FREQUENCY_REG2,
  48         FREQUENCY_REG3,
  49         FREQUENCY_REG4,
  50         MEMORY_LENGTH,
  51         CLOCK_SOURCE,
  52
  53         TRIGGER_STATUS0                 = 0x40,
  54         TRIGGER_STATUS1,
  55         TRIGGER_STATUS2,
  56         TRIGGER_STATUS3,
  57         TRIGGER_STATUS4,
  58         TRIGGER_STATUS5,
  59         TRIGGER_STATUS6,
  60         TRIGGER_STATUS7,
  61         TRIGGER_STATUS8,
  62
  63         TRIGGER_COUNT0                  = 0x50,
  64         TRIGGER_COUNT1,
  65
  66         TRIGGER_LEVEL0                  = 0x55,
  67         TRIGGER_LEVEL1,
  68         TRIGGER_LEVEL2,
  69         TRIGGER_LEVEL3,
  70
  71         RAMSIZE_TRIGGERBAR_ADDRESS0     = 0x60,
  72         RAMSIZE_TRIGGERBAR_ADDRESS1,
  73         RAMSIZE_TRIGGERBAR_ADDRESS2,
  74         TRIGGERBAR_ADDRESS0,
  75         TRIGGERBAR_ADDRESS1,
  76         TRIGGERBAR_ADDRESS2,
  77         DONT_CARE_TRIGGERBAR,
  78
  79         FILTER_ENABLE                   = 0x70,
  80         FILTER_STATUS,
  81
  82         ENABLE_DELAY_TIME0              = 0x7a,
  83         ENABLE_DELAY_TIME1,
  84
  85         ENABLE_INSERT_DATA0             = 0x80,
  86         ENABLE_INSERT_DATA1,
  87         ENABLE_INSERT_DATA2,
  88         ENABLE_INSERT_DATA3,
  89         COMPRESSION_TYPE0,
  90         COMPRESSION_TYPE1,
  91
  92         TRIGGER_ADDRESS0                = 0x90,
  93         TRIGGER_ADDRESS1,
  94         TRIGGER_ADDRESS2,
  95
  96         NOW_ADDRESS0                    = 0x96,
  97         NOW_ADDRESS1,
  98         NOW_ADDRESS2,
  99
 100         STOP_ADDRESS0                   = 0x9b,
 101         STOP_ADDRESS1,
 102         STOP_ADDRESS2,
 103
 104         READ_RAM_STATUS                 = 0xa0,
 105 };
 106
 107 static int g_trigger_status[9] = { 0 };
 108 static int g_trigger_count = 1;
 109 static int g_filter_status[8] = { 0 };
 110 static int g_filter_enable = 0;
 111
 112 static int g_freq_value = 100;
 113 static int g_freq_scale = FREQ_SCALE_MHZ;
 114 static int g_memory_size = MEMORY_SIZE_512K;
 115 static int g_ramsize_triggerbar_addr = 0x80000 >> 2;
 116 static int g_triggerbar_addr = 0x3fe;
 117 static int g_compression = COMPRESSION_NONE;
 118
 119 /* Maybe unk specifies an "endpoint" or "register" of sorts. */
 120 static int analyzer_write_status(libusb_device_handle *devh, unsigned char unk,
 121                                  unsigned char flags)
 122 {
 123         assert(unk <= 3);
 124         return gl_reg_write(devh, START_STATUS, unk << 6 | flags);
 125 }
 126
 127 static int __analyzer_set_freq(libusb_device_handle *devh, int freq, int scale)
 128 {
 129         int reg0 = 0, divisor = 0, reg2 = 0;
 130
 131         switch (scale) {
 132         case FREQ_SCALE_MHZ: /* MHz */
 133                 if (freq >= 100 && freq <= 200) {
 134                         reg0 = freq * 0.1;
 135                         divisor = 1;
 136                         reg2 = 0;
 137                         break;
 138                 }
 139                 if (freq >= 50 && freq < 100) {
 140                         reg0 = freq * 0.2;
 141                         divisor = 2;
 142                         reg2 = 0;
 143                         break;
 144                 }
 145                 if (freq >= 10 && freq < 50) {
 146                         if (freq == 25) {
 147                                 reg0 = 25;
 148                                 divisor = 5;
 149                                 reg2 = 1;
 150                                 break;
 151                         } else {
 152                                 reg0 = freq * 0.5;
 153                                 divisor = 5;
 154                                 reg2 = 1;
 155                                 break;
 156                         }
 157                 }
 158                 if (freq >= 2 && freq < 10) {
 159                         divisor = 5;
 160                         reg0 = freq * 2;
 161                         reg2 = 2;
 162                         break;
 163                 }
 164                 if (freq == 1) {
 165                         divisor = 5;
 166                         reg2 = 16;
 167                         reg0 = 5;
 168                         break;
 169                 }
 170                 divisor = 5;
 171                 reg0 = 5;
 172                 reg2 = 64;
 173                 break;
 174         case FREQ_SCALE_HZ: /* Hz */
 175                 if (freq >= 500 && freq < 1000) {
 176                         reg0 = freq * 0.01;
 177                         divisor = 10;
 178                         reg2 = 64;
 179                         break;
 180                 }
 181                 if (freq >= 300 && freq < 500) {
 182                         reg0 = freq * 0.005 * 8;
 183                         divisor = 5;
 184                         reg2 = 67;
 185                         break;
 186                 }
 187                 if (freq >= 100 && freq < 300) {
 188                         reg0 = freq * 0.005 * 16;
 189                         divisor = 5;
 190                         reg2 = 68;
 191                         break;
 192                 }
 193                 divisor = 5;
 194                 reg0 = 5;
 195                 reg2 = 64;
 196                 break;
 197         case FREQ_SCALE_KHZ: /* kHz */
 198                 if (freq >= 500 && freq < 1000) {
 199                         reg0 = freq * 0.01;
 200                         divisor = 5;
 201                         reg2 = 17;
 202                         break;
 203                 }
 204                 if (freq >= 100 && freq < 500) {
 205                         reg0 = freq * 0.05;
 206                         divisor = 5;
 207                         reg2 = 32;
 208                         break;
 209                 }
 210                 if (freq >= 50 && freq < 100) {
 211                         reg0 = freq * 0.1;
 212                         divisor = 5;
 213                         reg2 = 33;
 214                         break;
 215                 }
 216                 if (freq >= 10 && freq < 50) {
 217                         if (freq == 25) {
 218                                 reg0 = 25;
 219                                 divisor = 5;
 220                                 reg2 = 49;
 221                                 break;
 222                         }
 223                         reg0 = freq * 0.5;
 224                         divisor = 5;
 225                         reg2 = 48;
 226                         break;
 227                 }
 228                 if (freq >= 2 && freq < 10) {
 229                         divisor = 5;
 230                         reg0 = freq * 2;
 231                         reg2 = 50;
 232                         break;
 233                 }
 234                 divisor = 5;
 235                 reg0 = 5;
 236                 reg2 = 64;
 237                 break;
 238         default:
 239                 divisor = 5;
 240                 reg0 = 5;
 241                 reg2 = 64;
 242                 break;
 243         }
 244         if (gl_reg_write(devh, FREQUENCY_REG0, divisor) < 0)
 245                 return -1; /* Divisor maybe? */
 246
 247         if (gl_reg_write(devh, FREQUENCY_REG1, reg0) < 0)
 248                 return -1; /* 10 / 0.2 */
 249
 250         if (gl_reg_write(devh, FREQUENCY_REG2, 0x02) < 0)
 251                 return -1; /* Always 2 */
 252
 253         if (gl_reg_write(devh, FREQUENCY_REG4, reg2) < 0)
 254                 return -1;
 255
 256         return 0;
 257 }
 258
 259 static void __analyzer_set_ramsize_trigger_address(libusb_device_handle *devh,
 260                                                    unsigned int address)
 261 {
 262         gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
 263         gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
 264         gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
 265 }
 266
 267 static void __analyzer_set_triggerbar_address(libusb_device_handle *devh,
 268                                               unsigned int address)
 269 {
 270         gl_reg_write(devh, TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
 271         gl_reg_write(devh, TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
 272         gl_reg_write(devh, TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
 273 }
 274
 275 static void __analyzer_set_compression(libusb_device_handle *devh,
 276                                        unsigned int type)
 277 {
 278         gl_reg_write(devh, COMPRESSION_TYPE0, (type >> 0) & 0xFF);
 279         gl_reg_write(devh, COMPRESSION_TYPE1, (type >> 8) & 0xFF);
 280 }
 281
 282 static void __analyzer_set_trigger_count(libusb_device_handle *devh,
 283                                          unsigned int count)
 284 {
 285         gl_reg_write(devh, TRIGGER_COUNT0, (count >> 0) & 0xFF);
 286         gl_reg_write(devh, TRIGGER_COUNT1, (count >> 8) & 0xFF);
 287 }
 288
 289 static void analyzer_write_enable_insert_data(libusb_device_handle *devh)
 290 {
 291         gl_reg_write(devh, ENABLE_INSERT_DATA0, 0x12);
 292         gl_reg_write(devh, ENABLE_INSERT_DATA1, 0x34);
 293         gl_reg_write(devh, ENABLE_INSERT_DATA2, 0x56);
 294         gl_reg_write(devh, ENABLE_INSERT_DATA3, 0x78);
 295 }
 296
 297 static void analyzer_set_filter(libusb_device_handle *devh)
 298 {
 299         int i;
 300         gl_reg_write(devh, FILTER_ENABLE, g_filter_enable);
 301         for (i = 0; i < 8; i++)
 302                 gl_reg_write(devh, FILTER_STATUS + i, g_filter_status[i]);
 303 }
 304
 305 SR_PRIV void analyzer_reset(libusb_device_handle *devh)
 306 {
 307         analyzer_write_status(devh, 3, STATUS_FLAG_NONE);       // reset device
 308         analyzer_write_status(devh, 3, STATUS_FLAG_RESET);      // reset device
 309 }
 310
 311 SR_PRIV void analyzer_initialize(libusb_device_handle *devh)
 312 {
 313         analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
 314         analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
 315         analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
 316 }
 317
 318 SR_PRIV void analyzer_wait(libusb_device_handle *devh, int set, int unset)
 319 {
 320         int status;
 321         while (1) {
 322                 status = gl_reg_read(devh, DEV_STATUS);
 323                 if ((status & set) && ((status & unset) == 0))
 324                         return;
 325         }
 326 }
 327
 328 SR_PRIV void analyzer_read_start(libusb_device_handle *devh)
 329 {
 330         int i;
 331
 332         analyzer_write_status(devh, 3, STATUS_FLAG_20 | STATUS_FLAG_READ);
 333
 334         for (i = 0; i < 8; i++)
 335                 (void)gl_reg_read(devh, READ_RAM_STATUS);
 336 }
 337
 338 SR_PRIV int analyzer_read_data(libusb_device_handle *devh, void *buffer,
 339                        unsigned int size)
 340 {
 341         return gl_read_bulk(devh, buffer, size);
 342 }
 343
 344 SR_PRIV void analyzer_read_stop(libusb_device_handle *devh)
 345 {
 346         analyzer_write_status(devh, 3, STATUS_FLAG_20);
 347         analyzer_write_status(devh, 3, STATUS_FLAG_NONE);
 348 }
 349
 350 SR_PRIV void analyzer_start(libusb_device_handle *devh)
 351 {
 352         analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
 353         analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
 354         analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
 355         analyzer_write_status(devh, 1, STATUS_FLAG_GO);
 356 }
 357
 358 SR_PRIV void analyzer_configure(libusb_device_handle *devh)
 359 {
 360         int i;
 361
 362         /* Write_Start_Status */
 363         analyzer_write_status(devh, 1, STATUS_FLAG_RESET);
 364         analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
 365
 366         /* Start_Config_Outside_Device ? */
 367         analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
 368         analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
 369
 370         /* SetData_To_Frequence_Reg */
 371         __analyzer_set_freq(devh, g_freq_value, g_freq_scale);
 372
 373         /* SetMemory_Length */
 374         gl_reg_write(devh, MEMORY_LENGTH, g_memory_size);
 375
 376         /* Sele_Inside_Outside_Clock */
 377         gl_reg_write(devh, CLOCK_SOURCE, 0x03);
 378
 379         /* Set_Trigger_Status */
 380         for (i = 0; i < 9; i++)
 381                 gl_reg_write(devh, TRIGGER_STATUS0 + i, g_trigger_status[i]);
 382
 383         __analyzer_set_trigger_count(devh, g_trigger_count);
 384
 385         /* Set_Trigger_Level */
 386         gl_reg_write(devh, TRIGGER_LEVEL0, 0x31);
 387         gl_reg_write(devh, TRIGGER_LEVEL1, 0x31);
 388         gl_reg_write(devh, TRIGGER_LEVEL2, 0x31);
 389         gl_reg_write(devh, TRIGGER_LEVEL3, 0x31);
 390
 391         /* Size of actual memory >> 2 */
 392         __analyzer_set_ramsize_trigger_address(devh, g_ramsize_triggerbar_addr);
 393         __analyzer_set_triggerbar_address(devh, g_triggerbar_addr);
 394
 395         /* Set_Dont_Care_TriggerBar */
 396         gl_reg_write(devh, DONT_CARE_TRIGGERBAR, 0x01);
 397
 398         /* Enable_Status */
 399         analyzer_set_filter(devh);
 400
 401         /* Set_Enable_Delay_Time */
 402         gl_reg_write(devh, 0x7a, 0x00);
 403         gl_reg_write(devh, 0x7b, 0x00);
 404         analyzer_write_enable_insert_data(devh);
 405         __analyzer_set_compression(devh, g_compression);
 406 }
 407
 408 SR_PRIV void analyzer_add_trigger(int channel, int type)
 409 {
 410         int i;
 411
 412         if ((channel & 0xf) >= 8)
 413                 return;
 414
 415         if (type == TRIGGER_HIGH || type == TRIGGER_LOW) {
 416                 if (channel & CHANNEL_A)
 417                         i = 0;
 418                 else if (channel & CHANNEL_B)
 419                         i = 2;
 420                 else if (channel & CHANNEL_C)
 421                         i = 4;
 422                 else if (channel & CHANNEL_D)
 423                         i = 6;
 424                 else
 425                         return;
 426                 if ((channel & 0xf) >= 4) {
 427                         i++;
 428                         channel -= 4;
 429                 }
 430                 g_trigger_status[i] |=
 431                     1 << ((2 * channel) + (type == TRIGGER_LOW ? 1 : 0));
 432         } else {
 433                 if (type == TRIGGER_POSEDGE)
 434                         g_trigger_status[8] = 0x40;
 435                 else if (type == TRIGGER_NEGEDGE)
 436                         g_trigger_status[8] = 0x80;
 437                 else
 438                         g_trigger_status[8] = 0xc0;
 439
 440                 /* FIXME: Just guessed the index; need to verify. */
 441                 if (channel & CHANNEL_B)
 442                         g_trigger_status[8] += 8;
 443                 else if (channel & CHANNEL_C)
 444                         g_trigger_status[8] += 16;
 445                 else if (channel & CHANNEL_D)
 446                         g_trigger_status[8] += 24;
 447                 g_trigger_status[8] += channel % 8;
 448         }
 449 }
 450
 451 SR_PRIV void analyzer_add_filter(int channel, int type)
 452 {
 453         int i;
 454
 455         if (type != FILTER_HIGH && type != FILTER_LOW)
 456                 return;
 457         if ((channel & 0xf) >= 8)
 458                 return;
 459
 460         if (channel & CHANNEL_A)
 461                 i = 0;
 462         else if (channel & CHANNEL_B)
 463                 i = 2;
 464         else if (channel & CHANNEL_C)
 465                 i = 4;
 466         else if (channel & CHANNEL_D)
 467                 i = 6;
 468         else
 469                 return;
 470
 471         if ((channel & 0xf) >= 4) {
 472                 i++;
 473                 channel -= 4;
 474         }
 475
 476         g_filter_status[i] |=
 477             1 << ((2 * channel) + (type == FILTER_LOW ? 1 : 0));
 478
 479         g_filter_enable = 1;
 480 }
 481
 482 SR_PRIV void analyzer_set_trigger_count(int count)
 483 {
 484         g_trigger_count = count;
 485 }
 486
 487 SR_PRIV void analyzer_set_freq(int freq, int scale)
 488 {
 489         g_freq_value = freq;
 490         g_freq_scale = scale;
 491 }
 492
 493 SR_PRIV void analyzer_set_memory_size(unsigned int size)
 494 {
 495         g_memory_size = size;
 496 }
 497
 498 SR_PRIV void analyzer_set_ramsize_trigger_address(unsigned int address)
 499 {
 500         g_ramsize_triggerbar_addr = address;
 501 }
 502
 503 SR_PRIV void analyzer_set_triggerbar_address(unsigned int address)
 504 {
 505         g_triggerbar_addr = address;
 506 }
 507
 508 SR_PRIV unsigned int analyzer_read_id(libusb_device_handle *devh)
 509 {
 510         return gl_reg_read(devh, DEV_ID1) << 8 | gl_reg_read(devh, DEV_ID0);
 511 }
 512
 513 SR_PRIV unsigned int analyzer_get_stop_address(libusb_device_handle *devh)
 514 {
 515         return gl_reg_read(devh, STOP_ADDRESS2) << 16 | gl_reg_read(devh,
 516                         STOP_ADDRESS1) << 8 | gl_reg_read(devh, STOP_ADDRESS0);
 517 }
 518
 519 SR_PRIV unsigned int analyzer_get_now_address(libusb_device_handle *devh)
 520 {
 521         return gl_reg_read(devh, NOW_ADDRESS2) << 16 | gl_reg_read(devh,
 522                         NOW_ADDRESS1) << 8 | gl_reg_read(devh, NOW_ADDRESS0);
 523 }
 524
 525 SR_PRIV unsigned int analyzer_get_trigger_address(libusb_device_handle *devh)
 526 {
 527         return gl_reg_read(devh, TRIGGER_ADDRESS2) << 16 | gl_reg_read(devh,
 528                 TRIGGER_ADDRESS1) << 8 | gl_reg_read(devh, TRIGGER_ADDRESS0);
 529 }
 530
 531 SR_PRIV void analyzer_set_compression(unsigned int type)
 532 {
 533         g_compression = type;
 534 }
 535
 536 SR_PRIV void analyzer_wait_button(libusb_device_handle *devh)
 537 {
 538         analyzer_wait(devh, STATUS_BUTTON_PRESSED, 0);
 539 }
 540
 541 SR_PRIV void analyzer_wait_data(libusb_device_handle *devh)
 542 {
 543         analyzer_wait(devh, STATUS_READY | 8, STATUS_BUSY);
 544 }
 545
 546 SR_PRIV int analyzer_decompress(void *input, unsigned int input_len,
 547                                 void *output, unsigned int output_len)
 548 {
 549         unsigned char *in = input;
 550         unsigned char *out = output;
 551         unsigned int A, B, C, count;
 552         unsigned int written = 0;
 553
 554         while (input_len > 0) {
 555                 A = *in++;
 556                 B = *in++;
 557                 C = *in++;
 558                 count = (*in++) + 1;
 559
 560                 if (count > output_len)
 561                         count = output_len;
 562                 output_len -= count;
 563                 written += count;
 564
 565                 while (count--) {
 566                         *out++ = A;
 567                         *out++ = B;
 568                         *out++ = C;
 569                         *out++ = 0; /* Channel D */
 570                 }
 571
 572                 input_len -= 4;
 573                 if (output_len == 0)
 574                         break;
 575         }
 576
 577         return written;
 578 }