2 * This file is part of the sigrok project.
4 * Copyright (C) 2010 Sven Peter <sven@fail0verflow.com>
5 * Copyright (C) 2010 Haxx Enterprises <bushing@gmail.com>
8 * Redistribution and use in source and binary forms, with or
9 * without modification, are permitted provided that the following
12 * * Redistributions of source code must retain the above copyright notice,
13 * this list of conditions and the following disclaimer.
15 * * Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
29 * THE POSSIBILITY OF SUCH DAMAGE.
37 HARD_DATA_CHECK_SUM = 0x00,
45 FREQUENCY_REG0 = 0x30,
53 TRIGGER_STATUS0 = 0x40,
63 TRIGGER_COUNT0 = 0x50,
66 TRIGGER_LEVEL0 = 0x55,
71 RAMSIZE_TRIGGERBAR_ADDRESS0 = 0x60,
72 RAMSIZE_TRIGGERBAR_ADDRESS1,
73 RAMSIZE_TRIGGERBAR_ADDRESS2,
82 ENABLE_DELAY_TIME0 = 0x7a,
85 ENABLE_INSERT_DATA0 = 0x80,
92 TRIGGER_ADDRESS0 = 0x90,
100 STOP_ADDRESS0 = 0x9b,
104 READ_RAM_STATUS = 0xa0,
107 static int g_trigger_status[9] = { 0 };
108 static int g_trigger_count = 1;
109 static int g_filter_status[8] = { 0 };
110 static int g_filter_enable = 0;
112 static int g_freq_value = 100;
113 static int g_freq_scale = FREQ_SCALE_MHZ;
114 static int g_memory_size = MEMORY_SIZE_512K;
115 static int g_ramsize_triggerbar_addr = 0x80000 >> 2;
116 static int g_triggerbar_addr = 0x3fe;
117 static int g_compression = COMPRESSION_NONE;
119 /* Maybe unk specifies an "endpoint" or "register" of sorts. */
120 static int analyzer_write_status(libusb_device_handle *devh, unsigned char unk,
124 return gl_reg_write(devh, START_STATUS, unk << 6 | flags);
127 static int __analyzer_set_freq(libusb_device_handle *devh, int freq, int scale)
129 int reg0 = 0, divisor = 0, reg2 = 0;
132 case FREQ_SCALE_MHZ: /* MHz */
133 if (freq >= 100 && freq <= 200) {
139 if (freq >= 50 && freq < 100) {
145 if (freq >= 10 && freq < 50) {
158 if (freq >= 2 && freq < 10) {
174 case FREQ_SCALE_HZ: /* Hz */
175 if (freq >= 500 && freq < 1000) {
181 if (freq >= 300 && freq < 500) {
182 reg0 = freq * 0.005 * 8;
187 if (freq >= 100 && freq < 300) {
188 reg0 = freq * 0.005 * 16;
197 case FREQ_SCALE_KHZ: /* kHz */
198 if (freq >= 500 && freq < 1000) {
204 if (freq >= 100 && freq < 500) {
210 if (freq >= 50 && freq < 100) {
216 if (freq >= 10 && freq < 50) {
228 if (freq >= 2 && freq < 10) {
244 if (gl_reg_write(devh, FREQUENCY_REG0, divisor) < 0)
245 return -1; /* Divisor maybe? */
247 if (gl_reg_write(devh, FREQUENCY_REG1, reg0) < 0)
248 return -1; /* 10 / 0.2 */
250 if (gl_reg_write(devh, FREQUENCY_REG2, 0x02) < 0)
251 return -1; /* Always 2 */
253 if (gl_reg_write(devh, FREQUENCY_REG4, reg2) < 0)
259 static void __analyzer_set_ramsize_trigger_address(libusb_device_handle *devh,
260 unsigned int address)
262 gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
263 gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
264 gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
267 static void __analyzer_set_triggerbar_address(libusb_device_handle *devh,
268 unsigned int address)
270 gl_reg_write(devh, TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
271 gl_reg_write(devh, TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
272 gl_reg_write(devh, TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
275 static void __analyzer_set_compression(libusb_device_handle *devh,
278 gl_reg_write(devh, COMPRESSION_TYPE0, (type >> 0) & 0xFF);
279 gl_reg_write(devh, COMPRESSION_TYPE1, (type >> 8) & 0xFF);
282 static void __analyzer_set_trigger_count(libusb_device_handle *devh,
285 gl_reg_write(devh, TRIGGER_COUNT0, (count >> 0) & 0xFF);
286 gl_reg_write(devh, TRIGGER_COUNT1, (count >> 8) & 0xFF);
289 static void analyzer_write_enable_insert_data(libusb_device_handle *devh)
291 gl_reg_write(devh, ENABLE_INSERT_DATA0, 0x12);
292 gl_reg_write(devh, ENABLE_INSERT_DATA1, 0x34);
293 gl_reg_write(devh, ENABLE_INSERT_DATA2, 0x56);
294 gl_reg_write(devh, ENABLE_INSERT_DATA3, 0x78);
297 static void analyzer_set_filter(libusb_device_handle *devh)
300 gl_reg_write(devh, FILTER_ENABLE, g_filter_enable);
301 for (i = 0; i < 8; i++)
302 gl_reg_write(devh, FILTER_STATUS + i, g_filter_status[i]);
305 SR_PRIV void analyzer_reset(libusb_device_handle *devh)
307 analyzer_write_status(devh, 3, STATUS_FLAG_NONE); // reset device
308 analyzer_write_status(devh, 3, STATUS_FLAG_RESET); // reset device
311 SR_PRIV void analyzer_initialize(libusb_device_handle *devh)
313 analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
314 analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
315 analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
318 SR_PRIV void analyzer_wait(libusb_device_handle *devh, int set, int unset)
322 status = gl_reg_read(devh, DEVICE_STATUS);
323 if ((status & set) && ((status & unset) == 0))
328 SR_PRIV void analyzer_read_start(libusb_device_handle *devh)
332 analyzer_write_status(devh, 3, STATUS_FLAG_20 | STATUS_FLAG_READ);
334 for (i = 0; i < 8; i++)
335 (void)gl_reg_read(devh, READ_RAM_STATUS);
338 SR_PRIV int analyzer_read_data(libusb_device_handle *devh, void *buffer,
341 return gl_read_bulk(devh, buffer, size);
344 SR_PRIV void analyzer_read_stop(libusb_device_handle *devh)
346 analyzer_write_status(devh, 3, STATUS_FLAG_20);
347 analyzer_write_status(devh, 3, STATUS_FLAG_NONE);
350 SR_PRIV void analyzer_start(libusb_device_handle *devh)
352 analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
353 analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
354 analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
355 analyzer_write_status(devh, 1, STATUS_FLAG_GO);
358 SR_PRIV void analyzer_configure(libusb_device_handle *devh)
362 /* Write_Start_Status */
363 analyzer_write_status(devh, 1, STATUS_FLAG_RESET);
364 analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
366 /* Start_Config_Outside_Device ? */
367 analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
368 analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
370 /* SetData_To_Frequence_Reg */
371 __analyzer_set_freq(devh, g_freq_value, g_freq_scale);
373 /* SetMemory_Length */
374 gl_reg_write(devh, MEMORY_LENGTH, g_memory_size);
376 /* Sele_Inside_Outside_Clock */
377 gl_reg_write(devh, CLOCK_SOURCE, 0x03);
379 /* Set_Trigger_Status */
380 for (i = 0; i < 9; i++)
381 gl_reg_write(devh, TRIGGER_STATUS0 + i, g_trigger_status[i]);
383 __analyzer_set_trigger_count(devh, g_trigger_count);
385 /* Set_Trigger_Level */
386 gl_reg_write(devh, TRIGGER_LEVEL0, 0x31);
387 gl_reg_write(devh, TRIGGER_LEVEL1, 0x31);
388 gl_reg_write(devh, TRIGGER_LEVEL2, 0x31);
389 gl_reg_write(devh, TRIGGER_LEVEL3, 0x31);
391 /* Size of actual memory >> 2 */
392 __analyzer_set_ramsize_trigger_address(devh, g_ramsize_triggerbar_addr);
393 __analyzer_set_triggerbar_address(devh, g_triggerbar_addr);
395 /* Set_Dont_Care_TriggerBar */
396 gl_reg_write(devh, DONT_CARE_TRIGGERBAR, 0x01);
399 analyzer_set_filter(devh);
401 /* Set_Enable_Delay_Time */
402 gl_reg_write(devh, 0x7a, 0x00);
403 gl_reg_write(devh, 0x7b, 0x00);
404 analyzer_write_enable_insert_data(devh);
405 __analyzer_set_compression(devh, g_compression);
408 SR_PRIV void analyzer_add_trigger(int channel, int type)
412 if ((channel & 0xf) >= 8)
415 if (type == TRIGGER_HIGH || type == TRIGGER_LOW) {
416 if (channel & CHANNEL_A)
418 else if (channel & CHANNEL_B)
420 else if (channel & CHANNEL_C)
422 else if (channel & CHANNEL_D)
426 if ((channel & 0xf) >= 4) {
430 g_trigger_status[i] |=
431 1 << ((2 * channel) + (type == TRIGGER_LOW ? 1 : 0));
433 if (type == TRIGGER_POSEDGE)
434 g_trigger_status[8] = 0x40;
435 else if (type == TRIGGER_NEGEDGE)
436 g_trigger_status[8] = 0x80;
438 g_trigger_status[8] = 0xc0;
440 /* FIXME: Just guessed the index; need to verify. */
441 if (channel & CHANNEL_B)
442 g_trigger_status[8] += 8;
443 else if (channel & CHANNEL_C)
444 g_trigger_status[8] += 16;
445 else if (channel & CHANNEL_D)
446 g_trigger_status[8] += 24;
447 g_trigger_status[8] += channel % 8;
451 SR_PRIV void analyzer_add_filter(int channel, int type)
455 if (type != FILTER_HIGH && type != FILTER_LOW)
457 if ((channel & 0xf) >= 8)
460 if (channel & CHANNEL_A)
462 else if (channel & CHANNEL_B)
464 else if (channel & CHANNEL_C)
466 else if (channel & CHANNEL_D)
471 if ((channel & 0xf) >= 4) {
476 g_filter_status[i] |=
477 1 << ((2 * channel) + (type == FILTER_LOW ? 1 : 0));
482 SR_PRIV void analyzer_set_trigger_count(int count)
484 g_trigger_count = count;
487 SR_PRIV void analyzer_set_freq(int freq, int scale)
490 g_freq_scale = scale;
493 SR_PRIV void analyzer_set_memory_size(unsigned int size)
495 g_memory_size = size;
498 SR_PRIV void analyzer_set_ramsize_trigger_address(unsigned int address)
500 g_ramsize_triggerbar_addr = address;
503 SR_PRIV void analyzer_set_triggerbar_address(unsigned int address)
505 g_triggerbar_addr = address;
508 SR_PRIV unsigned int analyzer_read_id(libusb_device_handle *devh)
510 return gl_reg_read(devh, DEVICE_ID1) << 8 | gl_reg_read(devh,
514 SR_PRIV unsigned int analyzer_get_stop_address(libusb_device_handle *devh)
516 return gl_reg_read(devh, STOP_ADDRESS2) << 16 | gl_reg_read(devh,
517 STOP_ADDRESS1) << 8 | gl_reg_read(devh, STOP_ADDRESS0);
520 SR_PRIV unsigned int analyzer_get_now_address(libusb_device_handle *devh)
522 return gl_reg_read(devh, NOW_ADDRESS2) << 16 | gl_reg_read(devh,
523 NOW_ADDRESS1) << 8 | gl_reg_read(devh, NOW_ADDRESS0);
526 SR_PRIV unsigned int analyzer_get_trigger_address(libusb_device_handle *devh)
528 return gl_reg_read(devh, TRIGGER_ADDRESS2) << 16 | gl_reg_read(devh,
529 TRIGGER_ADDRESS1) << 8 | gl_reg_read(devh, TRIGGER_ADDRESS0);
532 SR_PRIV void analyzer_set_compression(unsigned int type)
534 g_compression = type;
537 SR_PRIV void analyzer_wait_button(libusb_device_handle *devh)
539 analyzer_wait(devh, STATUS_BUTTON_PRESSED, 0);
542 SR_PRIV void analyzer_wait_data(libusb_device_handle *devh)
544 analyzer_wait(devh, STATUS_READY | 8, STATUS_BUSY);
547 SR_PRIV int analyzer_decompress(void *input, unsigned int input_len,
548 void *output, unsigned int output_len)
550 unsigned char *in = input;
551 unsigned char *out = output;
552 unsigned int A, B, C, count;
553 unsigned int written = 0;
555 while (input_len > 0) {
561 if (count > output_len)
570 *out++ = 0; /* Channel D */