2 * This file is part of the libsigrok project.
4 * Copyright (C) 2014 Daniel Elstner <daniel.kitta@gmail.com>
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 /* Bit mask covering all 34 channels. */
24 #define ALL_CHANNELS_MASK (((uint64_t)1 << NUM_PROBES) - 1)
26 /* Bit mask for the RLE repeat-count-follows flag. */
27 #define RLE_FLAG_LEN_FOLLOWS ((uint64_t)1 << 35)
29 /* Start address of capture status memory area to read. */
30 #define CAP_STAT_ADDR 5
32 /* Number of 64-bit words read from the capture status memory. */
33 #define CAP_STAT_LEN 5
35 /* The bitstream filenames are indexed by the clock source enumeration.
37 static const char *const bitstream_map[] = {
38 FIRMWARE_DIR "/sysclk-lwla1034-off.bitstream",
39 FIRMWARE_DIR "/sysclk-lwla1034-int.bitstream",
40 FIRMWARE_DIR "/sysclk-lwla1034-extpos.bitstream",
41 FIRMWARE_DIR "/sysclk-lwla1034-extneg.bitstream",
44 /* Submit an already filled-in USB transfer.
46 static int submit_transfer(struct dev_context *devc,
47 struct libusb_transfer *xfer)
51 ret = libusb_submit_transfer(xfer);
54 sr_err("Submit transfer failed: %s.", libusb_error_name(ret));
55 devc->transfer_error = TRUE;
62 /* Set up the LWLA in preparation for an acquisition session.
64 static int capture_setup(const struct sr_dev_inst *sdi)
66 struct dev_context *devc;
67 struct acquisition_state *acq;
68 uint64_t divider_count;
69 uint64_t memory_limit;
70 uint16_t command[3 + 10*4];
73 acq = devc->acquisition;
75 command[0] = LWLA_WORD(CMD_CAP_SETUP);
76 command[1] = LWLA_WORD(0); /* address */
77 command[2] = LWLA_WORD(10); /* length */
79 command[3] = LWLA_WORD_0(devc->channel_mask);
80 command[4] = LWLA_WORD_1(devc->channel_mask);
81 command[5] = LWLA_WORD_2(devc->channel_mask);
82 command[6] = LWLA_WORD_3(devc->channel_mask);
84 /* Set the clock divide counter maximum for samplerates of up to
85 * 100 MHz. At the highest samplerate of 125 MHz the clock divider
88 if (!acq->bypass_clockdiv && devc->samplerate > 0)
89 divider_count = SR_MHZ(100) / devc->samplerate - 1;
93 command[7] = LWLA_WORD_0(divider_count);
94 command[8] = LWLA_WORD_1(divider_count);
95 command[9] = LWLA_WORD_2(divider_count);
96 command[10] = LWLA_WORD_3(divider_count);
98 command[11] = LWLA_WORD_0(devc->trigger_values);
99 command[12] = LWLA_WORD_1(devc->trigger_values);
100 command[13] = LWLA_WORD_2(devc->trigger_values);
101 command[14] = LWLA_WORD_3(devc->trigger_values);
103 command[15] = LWLA_WORD_0(devc->trigger_edge_mask);
104 command[16] = LWLA_WORD_1(devc->trigger_edge_mask);
105 command[17] = LWLA_WORD_2(devc->trigger_edge_mask);
106 command[18] = LWLA_WORD_3(devc->trigger_edge_mask);
108 command[19] = LWLA_WORD_0(devc->trigger_mask);
109 command[20] = LWLA_WORD_1(devc->trigger_mask);
110 command[21] = LWLA_WORD_2(devc->trigger_mask);
111 command[22] = LWLA_WORD_3(devc->trigger_mask);
113 /* Set the capture memory full threshold. This is slightly less
114 * than the actual maximum, most likely in order to compensate for
117 memory_limit = MEMORY_DEPTH - 16;
119 command[23] = LWLA_WORD_0(memory_limit);
120 command[24] = LWLA_WORD_1(memory_limit);
121 command[25] = LWLA_WORD_2(memory_limit);
122 command[26] = LWLA_WORD_3(memory_limit);
124 /* Fill remaining 64-bit words with zeroes. */
125 memset(&command[27], 0, 16 * sizeof(uint16_t));
127 return lwla_send_command(sdi->conn, command, G_N_ELEMENTS(command));
130 /* Issue a register write command as an asynchronous USB transfer.
132 static int issue_write_reg(const struct sr_dev_inst *sdi,
133 unsigned int reg, unsigned int value)
135 struct dev_context *devc;
136 struct acquisition_state *acq;
139 acq = devc->acquisition;
141 acq->xfer_buf_out[0] = LWLA_WORD(CMD_WRITE_REG);
142 acq->xfer_buf_out[1] = LWLA_WORD(reg);
143 acq->xfer_buf_out[2] = LWLA_WORD_0(value);
144 acq->xfer_buf_out[3] = LWLA_WORD_1(value);
146 acq->xfer_out->length = 4 * sizeof(uint16_t);
148 return submit_transfer(devc, acq->xfer_out);
151 /* Issue a register write command as an asynchronous USB transfer for the
152 * next register/value pair of the currently active register write sequence.
154 static int issue_next_write_reg(const struct sr_dev_inst *sdi)
156 struct dev_context *devc;
157 struct regval_pair *regval;
162 if (devc->reg_write_pos >= devc->reg_write_len) {
163 sr_err("Already written all registers in sequence.");
166 regval = &devc->reg_write_seq[devc->reg_write_pos];
168 ret = issue_write_reg(sdi, regval->reg, regval->val);
172 ++devc->reg_write_pos;
176 /* Issue a capture status request as an asynchronous USB transfer.
178 static void request_capture_status(const struct sr_dev_inst *sdi)
180 struct dev_context *devc;
181 struct acquisition_state *acq;
184 acq = devc->acquisition;
186 acq->xfer_buf_out[0] = LWLA_WORD(CMD_CAP_STATUS);
187 acq->xfer_buf_out[1] = LWLA_WORD(CAP_STAT_ADDR);
188 acq->xfer_buf_out[2] = LWLA_WORD(CAP_STAT_LEN);
190 acq->xfer_out->length = 3 * sizeof(uint16_t);
192 if (submit_transfer(devc, acq->xfer_out) == SR_OK)
193 devc->state = STATE_STATUS_REQUEST;
196 /* Issue a request for the capture buffer fill level as
197 * an asynchronous USB transfer.
199 static void request_capture_length(const struct sr_dev_inst *sdi)
201 struct dev_context *devc;
202 struct acquisition_state *acq;
205 acq = devc->acquisition;
207 acq->xfer_buf_out[0] = LWLA_WORD(CMD_READ_REG);
208 acq->xfer_buf_out[1] = LWLA_WORD(REG_MEM_FILL);
210 acq->xfer_out->length = 2 * sizeof(uint16_t);
212 if (submit_transfer(devc, acq->xfer_out) == SR_OK)
213 devc->state = STATE_LENGTH_REQUEST;
216 /* Initiate the capture memory read operation: Reset the acquisition state
217 * and start a sequence of register writes in order to set up the device for
218 * reading from the capture buffer.
220 static void issue_read_start(const struct sr_dev_inst *sdi)
222 struct dev_context *devc;
223 struct acquisition_state *acq;
224 struct regval_pair *regvals;
227 acq = devc->acquisition;
229 /* Reset RLE state. */
230 acq->rle = RLE_STATE_DATA;
234 acq->samples_done = 0;
236 /* For some reason, the start address is 4 rather than 0. */
237 acq->mem_addr_done = 4;
238 acq->mem_addr_next = 4;
239 acq->mem_addr_stop = acq->mem_addr_fill;
241 /* Sample position in the packet output buffer. */
244 regvals = devc->reg_write_seq;
246 regvals[0].reg = REG_DIV_BYPASS;
249 regvals[1].reg = REG_MEM_CTRL2;
252 regvals[2].reg = REG_MEM_CTRL4;
255 devc->reg_write_pos = 0;
256 devc->reg_write_len = 3;
258 if (issue_next_write_reg(sdi) == SR_OK)
259 devc->state = STATE_READ_PREPARE;
262 /* Issue a command as an asynchronous USB transfer which returns the device
263 * to normal state after a read operation. Sets a new device context state
266 static void issue_read_end(const struct sr_dev_inst *sdi)
268 struct dev_context *devc;
272 if (issue_write_reg(sdi, REG_DIV_BYPASS, 0) == SR_OK)
273 devc->state = STATE_READ_END;
276 /* Decode an incoming reponse to a buffer fill level request and act on it
277 * as appropriate. Note that this function changes the device context state.
279 static void process_capture_length(const struct sr_dev_inst *sdi)
281 struct dev_context *devc;
282 struct acquisition_state *acq;
285 acq = devc->acquisition;
287 if (acq->xfer_in->actual_length != 4) {
288 sr_err("Received size %d doesn't match expected size 4.",
289 acq->xfer_in->actual_length);
290 devc->transfer_error = TRUE;
293 acq->mem_addr_fill = LWLA_READ32(acq->xfer_buf_in);
295 sr_dbg("%lu words in capture buffer.",
296 (unsigned long)acq->mem_addr_fill);
298 if (acq->mem_addr_fill > 0 && sdi->status == SR_ST_ACTIVE)
299 issue_read_start(sdi);
304 /* Initiate a sequence of register write commands with the effect of
305 * cancelling a running capture operation. This sets a new device state
306 * if issuing the first command succeeds.
308 static void issue_stop_capture(const struct sr_dev_inst *sdi)
310 struct dev_context *devc;
311 struct regval_pair *regvals;
315 if (devc->stopping_in_progress)
318 regvals = devc->reg_write_seq;
320 regvals[0].reg = REG_CMD_CTRL2;
323 regvals[1].reg = REG_CMD_CTRL3;
326 regvals[2].reg = REG_CMD_CTRL4;
329 regvals[3].reg = REG_CMD_CTRL1;
332 regvals[4].reg = REG_DIV_BYPASS;
335 devc->reg_write_pos = 0;
336 devc->reg_write_len = 5;
338 if (issue_next_write_reg(sdi) == SR_OK) {
339 devc->stopping_in_progress = TRUE;
340 devc->state = STATE_STOP_CAPTURE;
344 /* Decode an incoming capture status reponse and act on it as appropriate.
345 * Note that this function changes the device state.
347 static void process_capture_status(const struct sr_dev_inst *sdi)
350 struct dev_context *devc;
351 struct acquisition_state *acq;
354 acq = devc->acquisition;
356 if (acq->xfer_in->actual_length != CAP_STAT_LEN * 8) {
357 sr_err("Received size %d doesn't match expected size %d.",
358 acq->xfer_in->actual_length, CAP_STAT_LEN * 8);
359 devc->transfer_error = TRUE;
363 /* TODO: Find out the actual bit width of these fields as stored
364 * in the FPGA. These fields are definitely less than 64 bit wide
365 * internally, and the unused bits occasionally even contain garbage.
367 acq->mem_addr_fill = LWLA_READ32(&acq->xfer_buf_in[0]);
368 duration = LWLA_READ32(&acq->xfer_buf_in[8]);
369 acq->capture_flags = LWLA_READ32(&acq->xfer_buf_in[16])
372 /* The LWLA1034 runs at 125 MHz if the clock divider is bypassed.
373 * However, the time base used for the duration is apparently not
374 * adjusted for this "boost" mode. Whereas normally the duration
375 * unit is 1 ms, it is 0.8 ms when the clock divider is bypassed.
376 * As 0.8 = 100 MHz / 125 MHz, it seems that the internal cycle
377 * counter period is the same as at the 100 MHz setting.
379 if (acq->bypass_clockdiv)
380 acq->duration_now = duration * 4 / 5;
382 acq->duration_now = duration;
384 sr_spew("Captured %zu words, %" PRIu64 " ms, flags 0x%02X",
385 acq->mem_addr_fill, acq->duration_now, acq->capture_flags);
387 if (acq->duration_now >= acq->duration_max) {
388 issue_stop_capture(sdi);
391 devc->state = STATE_STATUS_WAIT;
393 if ((acq->capture_flags & STATUS_TRIGGERED) == 0) {
394 sr_spew("Waiting for trigger.");
395 } else if ((acq->capture_flags & STATUS_MEM_AVAIL) == 0) {
396 sr_dbg("Capture memory filled.");
397 request_capture_length(sdi);
398 } else if ((acq->capture_flags & STATUS_CAPTURING) != 0) {
399 sr_spew("Sampling in progress.");
403 /* Issue a capture buffer read request as an asynchronous USB transfer.
404 * The address and size of the memory area to read are derived from the
405 * current acquisition state.
407 static void request_read_mem(const struct sr_dev_inst *sdi)
409 struct dev_context *devc;
410 struct acquisition_state *acq;
414 acq = devc->acquisition;
416 if (acq->mem_addr_next >= acq->mem_addr_stop)
419 /* Always read a multiple of 8 device words. */
420 count = (acq->mem_addr_stop - acq->mem_addr_next + 7) / 8 * 8;
421 count = MIN(count, READ_CHUNK_LEN);
423 acq->xfer_buf_out[0] = LWLA_WORD(CMD_READ_MEM);
424 acq->xfer_buf_out[1] = LWLA_WORD_0(acq->mem_addr_next);
425 acq->xfer_buf_out[2] = LWLA_WORD_1(acq->mem_addr_next);
426 acq->xfer_buf_out[3] = LWLA_WORD_0(count);
427 acq->xfer_buf_out[4] = LWLA_WORD_1(count);
429 acq->xfer_out->length = 5 * sizeof(uint16_t);
431 if (submit_transfer(devc, acq->xfer_out) == SR_OK) {
432 acq->mem_addr_next += count;
433 devc->state = STATE_READ_REQUEST;
437 /* Demangle and decompress incoming sample data from the capture buffer.
438 * The data chunk is taken from the acquisition state, and is expected to
439 * contain a multiple of 8 device words.
440 * All data currently in the acquisition buffer will be processed. Packets
441 * of decoded samples are sent off to the session bus whenever the output
442 * buffer becomes full while decoding.
444 static int process_sample_data(const struct sr_dev_inst *sdi)
447 uint64_t high_nibbles;
449 struct dev_context *devc;
450 struct acquisition_state *acq;
453 struct sr_datafeed_packet packet;
454 struct sr_datafeed_logic logic;
457 size_t out_max_samples;
458 size_t out_run_samples;
460 size_t in_words_left;
464 acq = devc->acquisition;
466 if (acq->mem_addr_done >= acq->mem_addr_stop
467 || acq->samples_done >= acq->samples_max)
470 in_words_left = MIN(acq->mem_addr_stop - acq->mem_addr_done,
472 expect_len = LWLA1034_MEMBUF_LEN(in_words_left) * sizeof(uint16_t);
473 actual_len = acq->xfer_in->actual_length;
475 if (actual_len != expect_len) {
476 sr_err("Received size %lu does not match expected size %lu.",
477 (unsigned long)actual_len, (unsigned long)expect_len);
478 devc->transfer_error = TRUE;
481 acq->mem_addr_done += in_words_left;
483 /* Prepare session packet. */
484 packet.type = SR_DF_LOGIC;
485 packet.payload = &logic;
486 logic.unitsize = UNIT_SIZE;
487 logic.data = acq->out_packet;
489 slice = acq->xfer_buf_in;
490 si = 0; /* word index within slice */
493 /* Calculate number of samples to write into packet. */
494 out_max_samples = MIN(acq->samples_max - acq->samples_done,
495 PACKET_LENGTH - acq->out_index);
496 out_run_samples = MIN(acq->run_len, out_max_samples);
498 /* Expand run-length samples into session packet. */
499 sample = acq->sample;
500 out_p = &acq->out_packet[acq->out_index * UNIT_SIZE];
502 for (ri = 0; ri < out_run_samples; ++ri) {
503 out_p[0] = sample & 0xFF;
504 out_p[1] = (sample >> 8) & 0xFF;
505 out_p[2] = (sample >> 16) & 0xFF;
506 out_p[3] = (sample >> 24) & 0xFF;
507 out_p[4] = (sample >> 32) & 0xFF;
510 acq->run_len -= out_run_samples;
511 acq->out_index += out_run_samples;
512 acq->samples_done += out_run_samples;
514 /* Packet full or sample count limit reached? */
515 if (out_run_samples == out_max_samples) {
516 logic.length = acq->out_index * UNIT_SIZE;
517 sr_session_send(sdi, &packet);
520 if (acq->samples_done >= acq->samples_max)
521 return SR_OK; /* sample limit reached */
522 if (acq->run_len > 0)
523 continue; /* need another packet */
526 if (in_words_left == 0)
527 break; /* done with current chunk */
529 /* Now work on the current slice. */
530 high_nibbles = LWLA_READ32(&slice[8 * 2]);
531 word = LWLA_READ32(&slice[si * 2]);
532 word |= (high_nibbles << (4 * si + 4)) & ((uint64_t)0xF << 32);
534 if (acq->rle == RLE_STATE_DATA) {
535 acq->sample = word & ALL_CHANNELS_MASK;
536 acq->run_len = ((word >> NUM_PROBES) & 1) + 1;
537 if (word & RLE_FLAG_LEN_FOLLOWS)
538 acq->rle = RLE_STATE_LEN;
540 acq->run_len += word << 1;
541 acq->rle = RLE_STATE_DATA;
544 /* Move to next word. */
552 /* Send out partially filled packet if this was the last chunk. */
553 if (acq->mem_addr_done >= acq->mem_addr_stop && acq->out_index > 0) {
554 logic.length = acq->out_index * UNIT_SIZE;
555 sr_session_send(sdi, &packet);
561 /* Finish an acquisition session. This sends the end packet to the session
562 * bus and removes the listener for asynchronous USB transfers.
564 static void end_acquisition(struct sr_dev_inst *sdi)
566 struct drv_context *drvc;
567 struct dev_context *devc;
568 struct sr_datafeed_packet packet;
570 drvc = sdi->driver->priv;
573 if (devc->state == STATE_IDLE)
576 devc->state = STATE_IDLE;
578 /* Remove USB file descriptors from polling. */
579 usb_source_remove(drvc->sr_ctx);
581 packet.type = SR_DF_END;
582 sr_session_send(sdi, &packet);
584 lwla_free_acquisition_state(devc->acquisition);
585 devc->acquisition = NULL;
587 sdi->status = SR_ST_ACTIVE;
590 /* USB output transfer completion callback.
592 static void receive_transfer_out(struct libusb_transfer *transfer)
594 struct sr_dev_inst *sdi;
595 struct dev_context *devc;
597 sdi = transfer->user_data;
600 if (transfer->status != LIBUSB_TRANSFER_COMPLETED) {
601 sr_err("Transfer to device failed: %d.", transfer->status);
602 devc->transfer_error = TRUE;
606 if (devc->reg_write_pos < devc->reg_write_len) {
607 issue_next_write_reg(sdi);
609 switch (devc->state) {
610 case STATE_START_CAPTURE:
611 devc->state = STATE_STATUS_WAIT;
613 case STATE_STATUS_REQUEST:
614 devc->state = STATE_STATUS_RESPONSE;
615 submit_transfer(devc, devc->acquisition->xfer_in);
617 case STATE_STOP_CAPTURE:
618 if (sdi->status == SR_ST_ACTIVE)
619 request_capture_length(sdi);
621 end_acquisition(sdi);
623 case STATE_LENGTH_REQUEST:
624 devc->state = STATE_LENGTH_RESPONSE;
625 submit_transfer(devc, devc->acquisition->xfer_in);
627 case STATE_READ_PREPARE:
628 request_read_mem(sdi);
630 case STATE_READ_REQUEST:
631 devc->state = STATE_READ_RESPONSE;
632 submit_transfer(devc, devc->acquisition->xfer_in);
635 end_acquisition(sdi);
638 sr_err("Unexpected device state %d.", devc->state);
644 /* USB input transfer completion callback.
646 static void receive_transfer_in(struct libusb_transfer *transfer)
648 struct sr_dev_inst *sdi;
649 struct dev_context *devc;
650 struct acquisition_state *acq;
652 sdi = transfer->user_data;
654 acq = devc->acquisition;
656 if (transfer->status != LIBUSB_TRANSFER_COMPLETED) {
657 sr_err("Transfer from device failed: %d.", transfer->status);
658 devc->transfer_error = TRUE;
662 switch (devc->state) {
663 case STATE_STATUS_RESPONSE:
664 process_capture_status(sdi);
666 case STATE_LENGTH_RESPONSE:
667 process_capture_length(sdi);
669 case STATE_READ_RESPONSE:
670 if (process_sample_data(sdi) == SR_OK
671 && acq->mem_addr_next < acq->mem_addr_stop
672 && acq->samples_done < acq->samples_max)
673 request_read_mem(sdi);
678 sr_err("Unexpected device state %d.", devc->state);
683 /* Initialize the LWLA. This downloads a bitstream into the FPGA
684 * and executes a simple device test sequence.
686 SR_PRIV int lwla_init_device(const struct sr_dev_inst *sdi)
688 struct dev_context *devc;
694 /* Select internal clock if it hasn't been set yet */
695 if (devc->selected_clock_source == CLOCK_SOURCE_NONE)
696 devc->selected_clock_source = CLOCK_SOURCE_INT;
698 /* Force reload of bitstream */
699 devc->cur_clock_source = CLOCK_SOURCE_NONE;
701 ret = lwla_set_clock_source(sdi);
706 ret = lwla_write_reg(sdi->conn, REG_CMD_CTRL2, 100);
710 ret = lwla_read_reg(sdi->conn, REG_CMD_CTRL1, &value);
713 sr_info("Received test word 0x%08X back.", value);
714 if (value != 0x12345678)
717 ret = lwla_read_reg(sdi->conn, REG_CMD_CTRL4, &value);
720 sr_info("Received test word 0x%08X back.", value);
721 if (value != 0x12345678)
724 ret = lwla_read_reg(sdi->conn, REG_CMD_CTRL3, &value);
727 sr_info("Received test word 0x%08X back.", value);
728 if (value != 0x87654321)
734 /* Select the LWLA clock source. If the clock source changed from the
735 * previous setting, this will download a new bitstream to the FPGA.
737 SR_PRIV int lwla_set_clock_source(const struct sr_dev_inst *sdi)
739 struct dev_context *devc;
741 enum clock_source selected;
745 selected = devc->selected_clock_source;
747 if (devc->cur_clock_source != selected) {
748 devc->cur_clock_source = CLOCK_SOURCE_NONE;
750 if (idx >= G_N_ELEMENTS(bitstream_map)) {
751 sr_err("Clock source (%d) out of range", selected);
754 ret = lwla_send_bitstream(sdi->conn, bitstream_map[idx]);
756 devc->cur_clock_source = selected;
762 /* Configure the LWLA in preparation for an acquisition session.
764 SR_PRIV int lwla_setup_acquisition(const struct sr_dev_inst *sdi)
766 struct dev_context *devc;
767 struct sr_usb_dev_inst *usb;
768 struct acquisition_state *acq;
769 struct regval_pair regvals[7];
774 acq = devc->acquisition;
776 /* By default, run virtually unlimited. */
777 acq->duration_max = (devc->limit_msec > 0)
778 ? devc->limit_msec : MAX_LIMIT_MSEC;
779 acq->samples_max = (devc->limit_samples > 0)
780 ? devc->limit_samples : MAX_LIMIT_SAMPLES;
782 switch (devc->cur_clock_source) {
783 case CLOCK_SOURCE_INT:
784 if (devc->samplerate == 0)
786 /* At 125 MHz, the clock divider is bypassed. */
787 acq->bypass_clockdiv = (devc->samplerate > SR_MHZ(100));
789 /* If only one of the limits is set, derive the other one. */
790 if (devc->limit_msec == 0 && devc->limit_samples > 0)
791 acq->duration_max = devc->limit_samples
792 * 1000 / devc->samplerate + 1;
793 else if (devc->limit_samples == 0 && devc->limit_msec > 0)
794 acq->samples_max = devc->limit_msec
795 * devc->samplerate / 1000;
797 case CLOCK_SOURCE_EXT_FALL:
798 case CLOCK_SOURCE_EXT_RISE:
799 acq->bypass_clockdiv = TRUE;
802 sr_err("No valid clock source has been configured.");
806 regvals[0].reg = REG_MEM_CTRL2;
809 regvals[1].reg = REG_MEM_CTRL2;
812 regvals[2].reg = REG_CMD_CTRL2;
815 regvals[3].reg = REG_CMD_CTRL3;
816 regvals[3].val = 0x74;
818 regvals[4].reg = REG_CMD_CTRL4;
821 regvals[5].reg = REG_CMD_CTRL1;
824 regvals[6].reg = REG_DIV_BYPASS;
825 regvals[6].val = acq->bypass_clockdiv;
827 ret = lwla_write_regs(usb, regvals, G_N_ELEMENTS(regvals));
831 return capture_setup(sdi);
834 /* Start the capture operation on the LWLA device. Beginning with this
835 * function, all USB transfers will be asynchronous until the end of the
836 * acquisition session.
838 SR_PRIV int lwla_start_acquisition(const struct sr_dev_inst *sdi)
840 struct dev_context *devc;
841 struct sr_usb_dev_inst *usb;
842 struct acquisition_state *acq;
843 struct regval_pair *regvals;
847 acq = devc->acquisition;
849 acq->duration_now = 0;
851 libusb_fill_bulk_transfer(acq->xfer_out, usb->devhdl, EP_COMMAND,
852 (unsigned char *)acq->xfer_buf_out, 0,
853 &receive_transfer_out,
854 (struct sr_dev_inst *)sdi, USB_TIMEOUT);
856 libusb_fill_bulk_transfer(acq->xfer_in, usb->devhdl, EP_REPLY,
857 (unsigned char *)acq->xfer_buf_in,
858 sizeof acq->xfer_buf_in,
859 &receive_transfer_in,
860 (struct sr_dev_inst *)sdi, USB_TIMEOUT);
862 regvals = devc->reg_write_seq;
864 regvals[0].reg = REG_CMD_CTRL2;
867 regvals[1].reg = REG_CMD_CTRL3;
870 regvals[2].reg = REG_CMD_CTRL4;
873 regvals[3].reg = REG_CMD_CTRL1;
876 devc->reg_write_pos = 0;
877 devc->reg_write_len = 4;
879 devc->state = STATE_START_CAPTURE;
881 return issue_next_write_reg(sdi);
884 /* Allocate an acquisition state object.
886 SR_PRIV struct acquisition_state *lwla_alloc_acquisition_state(void)
888 struct acquisition_state *acq;
890 acq = g_try_new0(struct acquisition_state, 1);
892 sr_err("Acquisition state malloc failed.");
896 acq->xfer_in = libusb_alloc_transfer(0);
898 sr_err("Transfer malloc failed.");
903 acq->xfer_out = libusb_alloc_transfer(0);
904 if (!acq->xfer_out) {
905 sr_err("Transfer malloc failed.");
906 libusb_free_transfer(acq->xfer_in);
914 /* Deallocate an acquisition state object.
916 SR_PRIV void lwla_free_acquisition_state(struct acquisition_state *acq)
919 libusb_free_transfer(acq->xfer_out);
920 libusb_free_transfer(acq->xfer_in);
925 /* USB I/O source callback.
927 SR_PRIV int lwla_receive_data(int fd, int revents, void *cb_data)
929 struct sr_dev_inst *sdi;
930 struct dev_context *devc;
931 struct drv_context *drvc;
939 drvc = sdi->driver->priv;
944 /* No timeout: return immediately. */
948 ret = libusb_handle_events_timeout_completed(drvc->sr_ctx->libusb_ctx,
951 sr_err("Event handling failed: %s.", libusb_error_name(ret));
953 /* If no event flags are set the timeout must have expired. */
954 if (revents == 0 && devc->state == STATE_STATUS_WAIT) {
955 if (sdi->status == SR_ST_STOPPING)
956 issue_stop_capture(sdi);
958 request_capture_status(sdi);
961 /* Check if an error occurred on a transfer. */
962 if (devc->transfer_error)
963 end_acquisition(sdi);