hardware/sysclk-lwla/protocol.c

   1 /*
   2  * This file is part of the libsigrok project.
   3  *
   4  * Copyright (C) 2014 Daniel Elstner <daniel.kitta@gmail.com>
   5  *
   6  * This program is free software: you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation, either version 3 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "protocol.h"
  21 #include <string.h>
  22
  23 /* Bit mask for the RLE repeat-count-follows flag. */
  24 #define RLE_FLAG_LEN_FOLLOWS ((uint64_t)1 << 35)
  25
  26 /* Start address of capture status memory area to read. */
  27 #define CAP_STAT_ADDR 5
  28
  29 /* Number of 64-bit words read from the capture status memory. */
  30 #define CAP_STAT_LEN 5
  31
  32 /* The bitstream filenames are indexed by the clock source enumeration.
  33  */
  34 static const char bitstream_map[][32] = {
  35         "sysclk-lwla1034-off.rbf",
  36         "sysclk-lwla1034-int.rbf",
  37         "sysclk-lwla1034-extpos.rbf",
  38         "sysclk-lwla1034-extneg.rbf",
  39 };
  40
  41 /* Submit an already filled-in USB transfer.
  42  */
  43 static int submit_transfer(struct dev_context *devc,
  44                            struct libusb_transfer *xfer)
  45 {
  46         int ret;
  47
  48         ret = libusb_submit_transfer(xfer);
  49
  50         if (ret != 0) {
  51                 sr_err("Submit transfer failed: %s.", libusb_error_name(ret));
  52                 devc->transfer_error = TRUE;
  53                 return SR_ERR;
  54         }
  55
  56         return SR_OK;
  57 }
  58
  59 /* Set up the LWLA in preparation for an acquisition session.
  60  */
  61 static int capture_setup(const struct sr_dev_inst *sdi)
  62 {
  63         struct dev_context *devc;
  64         struct acquisition_state *acq;
  65         uint64_t divider_count;
  66         uint64_t memory_limit;
  67         uint16_t command[3 + 10*4];
  68
  69         devc = sdi->priv;
  70         acq  = devc->acquisition;
  71
  72         command[0] = LWLA_WORD(CMD_CAP_SETUP);
  73         command[1] = LWLA_WORD(0); /* address */
  74         command[2] = LWLA_WORD(10); /* length */
  75
  76         command[3] = LWLA_WORD_0(devc->channel_mask);
  77         command[4] = LWLA_WORD_1(devc->channel_mask);
  78         command[5] = LWLA_WORD_2(devc->channel_mask);
  79         command[6] = LWLA_WORD_3(devc->channel_mask);
  80
  81         /* Set the clock divide counter maximum for samplerates of up to
  82          * 100 MHz. At the highest samplerate of 125 MHz the clock divider
  83          * is bypassed.
  84          */
  85         if (!acq->bypass_clockdiv && devc->samplerate > 0)
  86                 divider_count = SR_MHZ(100) / devc->samplerate - 1;
  87         else
  88                 divider_count = 0;
  89
  90         command[7]  = LWLA_WORD_0(divider_count);
  91         command[8]  = LWLA_WORD_1(divider_count);
  92         command[9]  = LWLA_WORD_2(divider_count);
  93         command[10] = LWLA_WORD_3(divider_count);
  94
  95         command[11] = LWLA_WORD_0(devc->trigger_values);
  96         command[12] = LWLA_WORD_1(devc->trigger_values);
  97         command[13] = LWLA_WORD_2(devc->trigger_values);
  98         command[14] = LWLA_WORD_3(devc->trigger_values);
  99
 100         command[15] = LWLA_WORD_0(devc->trigger_edge_mask);
 101         command[16] = LWLA_WORD_1(devc->trigger_edge_mask);
 102         command[17] = LWLA_WORD_2(devc->trigger_edge_mask);
 103         command[18] = LWLA_WORD_3(devc->trigger_edge_mask);
 104
 105         command[19] = LWLA_WORD_0(devc->trigger_mask);
 106         command[20] = LWLA_WORD_1(devc->trigger_mask);
 107         command[21] = LWLA_WORD_2(devc->trigger_mask);
 108         command[22] = LWLA_WORD_3(devc->trigger_mask);
 109
 110         /* Set the capture memory full threshold. This is slightly less
 111          * than the actual maximum, most likely in order to compensate for
 112          * pipeline latency.
 113          */
 114         memory_limit = MEMORY_DEPTH - 16;
 115
 116         command[23] = LWLA_WORD_0(memory_limit);
 117         command[24] = LWLA_WORD_1(memory_limit);
 118         command[25] = LWLA_WORD_2(memory_limit);
 119         command[26] = LWLA_WORD_3(memory_limit);
 120
 121         /* Fill remaining 64-bit words with zeroes. */
 122         memset(&command[27], 0, 16 * sizeof(uint16_t));
 123
 124         return lwla_send_command(sdi->conn, command, G_N_ELEMENTS(command));
 125 }
 126
 127 /* Issue a register write command as an asynchronous USB transfer.
 128  */
 129 static int issue_write_reg(const struct sr_dev_inst *sdi,
 130                            unsigned int reg, unsigned int value)
 131 {
 132         struct dev_context *devc;
 133         struct acquisition_state *acq;
 134
 135         devc = sdi->priv;
 136         acq  = devc->acquisition;
 137
 138         acq->xfer_buf_out[0] = LWLA_WORD(CMD_WRITE_REG);
 139         acq->xfer_buf_out[1] = LWLA_WORD(reg);
 140         acq->xfer_buf_out[2] = LWLA_WORD_0(value);
 141         acq->xfer_buf_out[3] = LWLA_WORD_1(value);
 142
 143         acq->xfer_out->length = 4 * sizeof(uint16_t);
 144
 145         return submit_transfer(devc, acq->xfer_out);
 146 }
 147
 148 /* Issue a register write command as an asynchronous USB transfer for the
 149  * next register/value pair of the currently active register write sequence.
 150  */
 151 static int issue_next_write_reg(const struct sr_dev_inst *sdi)
 152 {
 153         struct dev_context *devc;
 154         struct regval_pair *regval;
 155         int ret;
 156
 157         devc = sdi->priv;
 158
 159         if (devc->reg_write_pos >= devc->reg_write_len) {
 160                 sr_err("Already written all registers in sequence.");
 161                 return SR_ERR_BUG;
 162         }
 163         regval = &devc->reg_write_seq[devc->reg_write_pos];
 164
 165         ret = issue_write_reg(sdi, regval->reg, regval->val);
 166         if (ret != SR_OK)
 167                 return ret;
 168
 169         ++devc->reg_write_pos;
 170         return SR_OK;
 171 }
 172
 173 /* Issue a capture status request as an asynchronous USB transfer.
 174  */
 175 static void request_capture_status(const struct sr_dev_inst *sdi)
 176 {
 177         struct dev_context *devc;
 178         struct acquisition_state *acq;
 179
 180         devc = sdi->priv;
 181         acq  = devc->acquisition;
 182
 183         acq->xfer_buf_out[0] = LWLA_WORD(CMD_CAP_STATUS);
 184         acq->xfer_buf_out[1] = LWLA_WORD(CAP_STAT_ADDR);
 185         acq->xfer_buf_out[2] = LWLA_WORD(CAP_STAT_LEN);
 186
 187         acq->xfer_out->length = 3 * sizeof(uint16_t);
 188
 189         if (submit_transfer(devc, acq->xfer_out) == SR_OK)
 190                 devc->state = STATE_STATUS_REQUEST;
 191 }
 192
 193 /* Issue a request for the capture buffer fill level as
 194  * an asynchronous USB transfer.
 195  */
 196 static void request_capture_length(const struct sr_dev_inst *sdi)
 197 {
 198         struct dev_context *devc;
 199         struct acquisition_state *acq;
 200
 201         devc = sdi->priv;
 202         acq  = devc->acquisition;
 203
 204         acq->xfer_buf_out[0] = LWLA_WORD(CMD_READ_REG);
 205         acq->xfer_buf_out[1] = LWLA_WORD(REG_MEM_FILL);
 206
 207         acq->xfer_out->length = 2 * sizeof(uint16_t);
 208
 209         if (submit_transfer(devc, acq->xfer_out) == SR_OK)
 210                 devc->state = STATE_LENGTH_REQUEST;
 211 }
 212
 213 /* Initiate the capture memory read operation:  Reset the acquisition state
 214  * and start a sequence of register writes in order to set up the device for
 215  * reading from the capture buffer.
 216  */
 217 static void issue_read_start(const struct sr_dev_inst *sdi)
 218 {
 219         struct dev_context *devc;
 220         struct acquisition_state *acq;
 221         struct regval_pair *regvals;
 222
 223         devc = sdi->priv;
 224         acq  = devc->acquisition;
 225
 226         /* Reset RLE state. */
 227         acq->rle = RLE_STATE_DATA;
 228         acq->sample  = 0;
 229         acq->run_len = 0;
 230
 231         acq->samples_done = 0;
 232
 233         /* For some reason, the start address is 4 rather than 0. */
 234         acq->mem_addr_done = 4;
 235         acq->mem_addr_next = 4;
 236         acq->mem_addr_stop = acq->mem_addr_fill;
 237
 238         /* Sample position in the packet output buffer. */
 239         acq->out_index = 0;
 240
 241         regvals = devc->reg_write_seq;
 242
 243         regvals[0].reg = REG_DIV_BYPASS;
 244         regvals[0].val = 1;
 245
 246         regvals[1].reg = REG_MEM_CTRL2;
 247         regvals[1].val = 2;
 248
 249         regvals[2].reg = REG_MEM_CTRL4;
 250         regvals[2].val = 4;
 251
 252         devc->reg_write_pos = 0;
 253         devc->reg_write_len = 3;
 254
 255         if (issue_next_write_reg(sdi) == SR_OK)
 256                 devc->state = STATE_READ_PREPARE;
 257 }
 258
 259 /* Issue a command as an asynchronous USB transfer which returns the device
 260  * to normal state after a read operation.  Sets a new device context state
 261  * on success.
 262  */
 263 static void issue_read_end(const struct sr_dev_inst *sdi)
 264 {
 265         struct dev_context *devc;
 266
 267         devc = sdi->priv;
 268
 269         if (issue_write_reg(sdi, REG_DIV_BYPASS, 0) == SR_OK)
 270                 devc->state = STATE_READ_END;
 271 }
 272
 273 /* Decode an incoming reponse to a buffer fill level request and act on it
 274  * as appropriate.  Note that this function changes the device context state.
 275  */
 276 static void process_capture_length(const struct sr_dev_inst *sdi)
 277 {
 278         struct dev_context *devc;
 279         struct acquisition_state *acq;
 280
 281         devc = sdi->priv;
 282         acq  = devc->acquisition;
 283
 284         if (acq->xfer_in->actual_length != 4) {
 285                 sr_err("Received size %d doesn't match expected size 4.",
 286                        acq->xfer_in->actual_length);
 287                 devc->transfer_error = TRUE;
 288                 return;
 289         }
 290         acq->mem_addr_fill = LWLA_TO_UINT32(acq->xfer_buf_in[0]);
 291
 292         sr_dbg("%zu words in capture buffer.", acq->mem_addr_fill);
 293
 294         if (acq->mem_addr_fill > 0 && sdi->status == SR_ST_ACTIVE)
 295                 issue_read_start(sdi);
 296         else
 297                 issue_read_end(sdi);
 298 }
 299
 300 /* Initiate a sequence of register write commands with the effect of
 301  * cancelling a running capture operation.  This sets a new device state
 302  * if issuing the first command succeeds.
 303  */
 304 static void issue_stop_capture(const struct sr_dev_inst *sdi)
 305 {
 306         struct dev_context *devc;
 307         struct regval_pair *regvals;
 308
 309         devc = sdi->priv;
 310
 311         if (devc->stopping_in_progress)
 312                 return;
 313
 314         regvals = devc->reg_write_seq;
 315
 316         regvals[0].reg = REG_CMD_CTRL2;
 317         regvals[0].val = 10;
 318
 319         regvals[1].reg = REG_CMD_CTRL3;
 320         regvals[1].val = 0;
 321
 322         regvals[2].reg = REG_CMD_CTRL4;
 323         regvals[2].val = 0;
 324
 325         regvals[3].reg = REG_CMD_CTRL1;
 326         regvals[3].val = 0;
 327
 328         regvals[4].reg = REG_DIV_BYPASS;
 329         regvals[4].val = 0;
 330
 331         devc->reg_write_pos = 0;
 332         devc->reg_write_len = 5;
 333
 334         if (issue_next_write_reg(sdi) == SR_OK) {
 335                 devc->stopping_in_progress = TRUE;
 336                 devc->state = STATE_STOP_CAPTURE;
 337         }
 338 }
 339
 340 /* Decode an incoming capture status reponse and act on it as appropriate.
 341  * Note that this function changes the device state.
 342  */
 343 static void process_capture_status(const struct sr_dev_inst *sdi)
 344 {
 345         uint64_t duration;
 346         struct dev_context *devc;
 347         struct acquisition_state *acq;
 348         unsigned int mem_fill;
 349         unsigned int flags;
 350
 351         devc = sdi->priv;
 352         acq  = devc->acquisition;
 353
 354         if (acq->xfer_in->actual_length != CAP_STAT_LEN * 8) {
 355                 sr_err("Received size %d doesn't match expected size %d.",
 356                        acq->xfer_in->actual_length, CAP_STAT_LEN * 8);
 357                 devc->transfer_error = TRUE;
 358                 return;
 359         }
 360
 361         /* TODO: Find out the actual bit width of these fields as stored
 362          * in the FPGA.  These fields are definitely less than 64 bit wide
 363          * internally, and the unused bits occasionally even contain garbage.
 364          */
 365         mem_fill = LWLA_TO_UINT32(acq->xfer_buf_in[0]);
 366         duration = LWLA_TO_UINT32(acq->xfer_buf_in[4]);
 367         flags    = LWLA_TO_UINT32(acq->xfer_buf_in[8]) & STATUS_FLAG_MASK;
 368
 369         /* The LWLA1034 runs at 125 MHz if the clock divider is bypassed.
 370          * However, the time base used for the duration is apparently not
 371          * adjusted for this "boost" mode.  Whereas normally the duration
 372          * unit is 1 ms, it is 0.8 ms when the clock divider is bypassed.
 373          * As 0.8 = 100 MHz / 125 MHz, it seems that the internal cycle
 374          * counter period is the same as at the 100 MHz setting.
 375          */
 376         if (acq->bypass_clockdiv)
 377                 acq->duration_now = duration * 4 / 5;
 378         else
 379                 acq->duration_now = duration;
 380
 381         sr_spew("Captured %u words, %" PRIu64 " ms, flags 0x%02X.",
 382                 mem_fill, acq->duration_now, flags);
 383
 384         if ((flags & STATUS_TRIGGERED) > (acq->capture_flags & STATUS_TRIGGERED))
 385                 sr_info("Capture triggered.");
 386
 387         acq->capture_flags = flags;
 388
 389         if (acq->duration_now >= acq->duration_max) {
 390                 sr_dbg("Time limit reached, stopping capture.");
 391                 issue_stop_capture(sdi);
 392                 return;
 393         }
 394         devc->state = STATE_STATUS_WAIT;
 395
 396         if ((acq->capture_flags & STATUS_TRIGGERED) == 0) {
 397                 sr_spew("Waiting for trigger.");
 398         } else if ((acq->capture_flags & STATUS_MEM_AVAIL) == 0) {
 399                 sr_dbg("Capture memory filled.");
 400                 request_capture_length(sdi);
 401         } else if ((acq->capture_flags & STATUS_CAPTURING) != 0) {
 402                 sr_spew("Sampling in progress.");
 403         }
 404 }
 405
 406 /* Issue a capture buffer read request as an asynchronous USB transfer.
 407  * The address and size of the memory area to read are derived from the
 408  * current acquisition state.
 409  */
 410 static void request_read_mem(const struct sr_dev_inst *sdi)
 411 {
 412         struct dev_context *devc;
 413         struct acquisition_state *acq;
 414         size_t count;
 415
 416         devc = sdi->priv;
 417         acq  = devc->acquisition;
 418
 419         if (acq->mem_addr_next >= acq->mem_addr_stop)
 420                 return;
 421
 422         /* Always read a multiple of 8 device words. */
 423         count = (acq->mem_addr_stop - acq->mem_addr_next + 7) / 8 * 8;
 424         count = MIN(count, READ_CHUNK_LEN);
 425
 426         acq->xfer_buf_out[0] = LWLA_WORD(CMD_READ_MEM);
 427         acq->xfer_buf_out[1] = LWLA_WORD_0(acq->mem_addr_next);
 428         acq->xfer_buf_out[2] = LWLA_WORD_1(acq->mem_addr_next);
 429         acq->xfer_buf_out[3] = LWLA_WORD_0(count);
 430         acq->xfer_buf_out[4] = LWLA_WORD_1(count);
 431
 432         acq->xfer_out->length = 5 * sizeof(uint16_t);
 433
 434         if (submit_transfer(devc, acq->xfer_out) == SR_OK) {
 435                 acq->mem_addr_next += count;
 436                 devc->state = STATE_READ_REQUEST;
 437         }
 438 }
 439
 440 /* Demangle and decompress incoming sample data from the capture buffer.
 441  * The data chunk is taken from the acquisition state, and is expected to
 442  * contain a multiple of 8 device words.
 443  * All data currently in the acquisition buffer will be processed.  Packets
 444  * of decoded samples are sent off to the session bus whenever the output
 445  * buffer becomes full while decoding.
 446  */
 447 static int process_sample_data(const struct sr_dev_inst *sdi)
 448 {
 449         uint64_t sample;
 450         uint64_t high_nibbles;
 451         uint64_t word;
 452         struct dev_context *devc;
 453         struct acquisition_state *acq;
 454         uint8_t *out_p;
 455         uint32_t *slice;
 456         struct sr_datafeed_packet packet;
 457         struct sr_datafeed_logic logic;
 458         size_t expect_len;
 459         size_t actual_len;
 460         size_t out_max_samples;
 461         size_t out_run_samples;
 462         size_t ri;
 463         size_t in_words_left;
 464         size_t si;
 465
 466         devc = sdi->priv;
 467         acq  = devc->acquisition;
 468
 469         if (acq->mem_addr_done >= acq->mem_addr_stop
 470                         || acq->samples_done >= acq->samples_max)
 471                 return SR_OK;
 472
 473         in_words_left = MIN(acq->mem_addr_stop - acq->mem_addr_done,
 474                             READ_CHUNK_LEN);
 475         expect_len = LWLA1034_MEMBUF_LEN(in_words_left) * sizeof(uint32_t);
 476         actual_len = acq->xfer_in->actual_length;
 477
 478         if (actual_len != expect_len) {
 479                 sr_err("Received size %zu does not match expected size %zu.",
 480                        actual_len, expect_len);
 481                 devc->transfer_error = TRUE;
 482                 return SR_ERR;
 483         }
 484         acq->mem_addr_done += in_words_left;
 485
 486         /* Prepare session packet. */
 487         packet.type    = SR_DF_LOGIC;
 488         packet.payload = &logic;
 489         logic.unitsize = UNIT_SIZE;
 490         logic.data     = acq->out_packet;
 491
 492         slice = acq->xfer_buf_in;
 493         si = 0; /* word index within slice */
 494
 495         for (;;) {
 496                 /* Calculate number of samples to write into packet. */
 497                 out_max_samples = MIN(acq->samples_max - acq->samples_done,
 498                                       PACKET_LENGTH - acq->out_index);
 499                 out_run_samples = MIN(acq->run_len, out_max_samples);
 500
 501                 /* Expand run-length samples into session packet. */
 502                 sample = acq->sample;
 503                 out_p = &acq->out_packet[acq->out_index * UNIT_SIZE];
 504
 505                 for (ri = 0; ri < out_run_samples; ++ri) {
 506                         out_p[0] =  sample        & 0xFF;
 507                         out_p[1] = (sample >>  8) & 0xFF;
 508                         out_p[2] = (sample >> 16) & 0xFF;
 509                         out_p[3] = (sample >> 24) & 0xFF;
 510                         out_p[4] = (sample >> 32) & 0xFF;
 511                         out_p += UNIT_SIZE;
 512                 }
 513                 acq->run_len -= out_run_samples;
 514                 acq->out_index += out_run_samples;
 515                 acq->samples_done += out_run_samples;
 516
 517                 /* Packet full or sample count limit reached? */
 518                 if (out_run_samples == out_max_samples) {
 519                         logic.length = acq->out_index * UNIT_SIZE;
 520                         sr_session_send(sdi, &packet);
 521                         acq->out_index = 0;
 522
 523                         if (acq->samples_done >= acq->samples_max)
 524                                 return SR_OK; /* sample limit reached */
 525                         if (acq->run_len > 0)
 526                                 continue; /* need another packet */
 527                 }
 528
 529                 if (in_words_left == 0)
 530                         break; /* done with current chunk */
 531
 532                 /* Now work on the current slice. */
 533                 high_nibbles = LWLA_TO_UINT32(slice[8]);
 534                 word = LWLA_TO_UINT32(slice[si]);
 535                 word |= (high_nibbles << (4 * si + 4)) & ((uint64_t)0xF << 32);
 536
 537                 if (acq->rle == RLE_STATE_DATA) {
 538                         acq->sample = word & ALL_CHANNELS_MASK;
 539                         acq->run_len = ((word >> NUM_PROBES) & 1) + 1;
 540                         if (word & RLE_FLAG_LEN_FOLLOWS)
 541                                 acq->rle = RLE_STATE_LEN;
 542                 } else {
 543                         acq->run_len += word << 1;
 544                         acq->rle = RLE_STATE_DATA;
 545                 }
 546
 547                 /* Move to next word. */
 548                 si = (si + 1) % 8;
 549                 if (si == 0)
 550                         slice += 9;
 551                 --in_words_left;
 552         }
 553
 554         /* Send out partially filled packet if this was the last chunk. */
 555         if (acq->mem_addr_done >= acq->mem_addr_stop && acq->out_index > 0) {
 556                 logic.length = acq->out_index * UNIT_SIZE;
 557                 sr_session_send(sdi, &packet);
 558                 acq->out_index = 0;
 559         }
 560         return SR_OK;
 561 }
 562
 563 /* Finish an acquisition session.  This sends the end packet to the session
 564  * bus and removes the listener for asynchronous USB transfers.
 565  */
 566 static void end_acquisition(struct sr_dev_inst *sdi)
 567 {
 568         struct drv_context *drvc;
 569         struct dev_context *devc;
 570         struct sr_datafeed_packet packet;
 571
 572         drvc = sdi->driver->priv;
 573         devc = sdi->priv;
 574
 575         if (devc->state == STATE_IDLE)
 576                 return;
 577
 578         devc->state = STATE_IDLE;
 579
 580         /* Remove USB file descriptors from polling. */
 581         usb_source_remove(drvc->sr_ctx);
 582
 583         packet.type = SR_DF_END;
 584         sr_session_send(sdi, &packet);
 585
 586         lwla_free_acquisition_state(devc->acquisition);
 587         devc->acquisition = NULL;
 588
 589         sdi->status = SR_ST_ACTIVE;
 590 }
 591
 592 /* USB output transfer completion callback.
 593  */
 594 static void receive_transfer_out(struct libusb_transfer *transfer)
 595 {
 596         struct sr_dev_inst *sdi;
 597         struct dev_context *devc;
 598
 599         sdi  = transfer->user_data;
 600         devc = sdi->priv;
 601
 602         if (transfer->status != LIBUSB_TRANSFER_COMPLETED) {
 603                 sr_err("Transfer to device failed: %d.", transfer->status);
 604                 devc->transfer_error = TRUE;
 605                 return;
 606         }
 607
 608         if (devc->reg_write_pos < devc->reg_write_len) {
 609                 issue_next_write_reg(sdi);
 610         } else {
 611                 switch (devc->state) {
 612                 case STATE_START_CAPTURE:
 613                         devc->state = STATE_STATUS_WAIT;
 614                         break;
 615                 case STATE_STATUS_REQUEST:
 616                         devc->state = STATE_STATUS_RESPONSE;
 617                         submit_transfer(devc, devc->acquisition->xfer_in);
 618                         break;
 619                 case STATE_STOP_CAPTURE:
 620                         if (sdi->status == SR_ST_ACTIVE)
 621                                 request_capture_length(sdi);
 622                         else
 623                                 end_acquisition(sdi);
 624                         break;
 625                 case STATE_LENGTH_REQUEST:
 626                         devc->state = STATE_LENGTH_RESPONSE;
 627                         submit_transfer(devc, devc->acquisition->xfer_in);
 628                         break;
 629                 case STATE_READ_PREPARE:
 630                         request_read_mem(sdi);
 631                         break;
 632                 case STATE_READ_REQUEST:
 633                         devc->state = STATE_READ_RESPONSE;
 634                         submit_transfer(devc, devc->acquisition->xfer_in);
 635                         break;
 636                 case STATE_READ_END:
 637                         end_acquisition(sdi);
 638                         break;
 639                 default:
 640                         sr_err("Unexpected device state %d.", devc->state);
 641                         break;
 642                 }
 643         }
 644 }
 645
 646 /* USB input transfer completion callback.
 647  */
 648 static void receive_transfer_in(struct libusb_transfer *transfer)
 649 {
 650         struct sr_dev_inst *sdi;
 651         struct dev_context *devc;
 652         struct acquisition_state *acq;
 653
 654         sdi  = transfer->user_data;
 655         devc = sdi->priv;
 656         acq  = devc->acquisition;
 657
 658         if (transfer->status != LIBUSB_TRANSFER_COMPLETED) {
 659                 sr_err("Transfer from device failed: %d.", transfer->status);
 660                 devc->transfer_error = TRUE;
 661                 return;
 662         }
 663
 664         switch (devc->state) {
 665         case STATE_STATUS_RESPONSE:
 666                 process_capture_status(sdi);
 667                 break;
 668         case STATE_LENGTH_RESPONSE:
 669                 process_capture_length(sdi);
 670                 break;
 671         case STATE_READ_RESPONSE:
 672                 if (process_sample_data(sdi) == SR_OK
 673                                 && acq->mem_addr_next < acq->mem_addr_stop
 674                                 && acq->samples_done < acq->samples_max)
 675                         request_read_mem(sdi);
 676                 else
 677                         issue_read_end(sdi);
 678                 break;
 679         default:
 680                 sr_err("Unexpected device state %d.", devc->state);
 681                 break;
 682         }
 683 }
 684
 685 /* Initialize the LWLA.  This downloads a bitstream into the FPGA
 686  * and executes a simple device test sequence.
 687  */
 688 SR_PRIV int lwla_init_device(const struct sr_dev_inst *sdi)
 689 {
 690         struct dev_context *devc;
 691         int ret;
 692         uint32_t value;
 693
 694         devc = sdi->priv;
 695
 696         /* Select internal clock if it hasn't been set yet */
 697         if (devc->selected_clock_source == CLOCK_SOURCE_NONE)
 698                 devc->selected_clock_source = CLOCK_SOURCE_INT;
 699
 700         /* Force reload of bitstream */
 701         devc->cur_clock_source = CLOCK_SOURCE_NONE;
 702
 703         ret = lwla_set_clock_source(sdi);
 704
 705         if (ret != SR_OK)
 706                 return ret;
 707
 708         ret = lwla_write_reg(sdi->conn, REG_CMD_CTRL2, 100);
 709         if (ret != SR_OK)
 710                 return ret;
 711
 712         ret = lwla_read_reg(sdi->conn, REG_CMD_CTRL1, &value);
 713         if (ret != SR_OK)
 714                 return ret;
 715         sr_dbg("Received test word 0x%08X back.", value);
 716         if (value != 0x12345678)
 717                 return SR_ERR;
 718
 719         ret = lwla_read_reg(sdi->conn, REG_CMD_CTRL4, &value);
 720         if (ret != SR_OK)
 721                 return ret;
 722         sr_dbg("Received test word 0x%08X back.", value);
 723         if (value != 0x12345678)
 724                 return SR_ERR;
 725
 726         ret = lwla_read_reg(sdi->conn, REG_CMD_CTRL3, &value);
 727         if (ret != SR_OK)
 728                 return ret;
 729         sr_dbg("Received test word 0x%08X back.", value);
 730         if (value != 0x87654321)
 731                 return SR_ERR;
 732
 733         return ret;
 734 }
 735
 736 /* Select the LWLA clock source.  If the clock source changed from the
 737  * previous setting, this will download a new bitstream to the FPGA.
 738  */
 739 SR_PRIV int lwla_set_clock_source(const struct sr_dev_inst *sdi)
 740 {
 741         struct dev_context *devc;
 742         int ret;
 743         enum clock_source selected;
 744         size_t idx;
 745
 746         devc = sdi->priv;
 747         selected = devc->selected_clock_source;
 748
 749         if (devc->cur_clock_source != selected) {
 750                 devc->cur_clock_source = CLOCK_SOURCE_NONE;
 751                 idx = selected;
 752                 if (idx >= G_N_ELEMENTS(bitstream_map)) {
 753                         sr_err("Clock source (%d) out of range", selected);
 754                         return SR_ERR_BUG;
 755                 }
 756                 ret = lwla_send_bitstream(sdi->conn, bitstream_map[idx]);
 757                 if (ret == SR_OK)
 758                         devc->cur_clock_source = selected;
 759                 return ret;
 760         }
 761         return SR_OK;
 762 }
 763
 764 /* Configure the LWLA in preparation for an acquisition session.
 765  */
 766 SR_PRIV int lwla_setup_acquisition(const struct sr_dev_inst *sdi)
 767 {
 768         struct dev_context *devc;
 769         struct sr_usb_dev_inst *usb;
 770         struct acquisition_state *acq;
 771         struct regval_pair regvals[7];
 772         int ret;
 773
 774         devc = sdi->priv;
 775         usb  = sdi->conn;
 776         acq  = devc->acquisition;
 777
 778         if (devc->limit_msec > 0) {
 779                 acq->duration_max = devc->limit_msec;
 780                 sr_info("Acquisition time limit %" PRIu64 " ms.",
 781                         devc->limit_msec);
 782         } else
 783                 acq->duration_max = MAX_LIMIT_MSEC;
 784
 785         if (devc->limit_samples > 0) {
 786                 acq->samples_max = devc->limit_samples;
 787                 sr_info("Acquisition sample count limit %" PRIu64 ".",
 788                         devc->limit_samples);
 789         } else
 790                 acq->samples_max = MAX_LIMIT_SAMPLES;
 791
 792         switch (devc->cur_clock_source) {
 793         case CLOCK_SOURCE_INT:
 794                 sr_info("Internal clock, samplerate %" PRIu64 ".",
 795                         devc->samplerate);
 796                 if (devc->samplerate == 0)
 797                         return SR_ERR_BUG;
 798                 /* At 125 MHz, the clock divider is bypassed. */
 799                 acq->bypass_clockdiv = (devc->samplerate > SR_MHZ(100));
 800
 801                 /* If only one of the limits is set, derive the other one. */
 802                 if (devc->limit_msec == 0 && devc->limit_samples > 0)
 803                         acq->duration_max = devc->limit_samples
 804                                         * 1000 / devc->samplerate + 1;
 805                 else if (devc->limit_samples == 0 && devc->limit_msec > 0)
 806                         acq->samples_max = devc->limit_msec
 807                                         * devc->samplerate / 1000;
 808                 break;
 809         case CLOCK_SOURCE_EXT_FALL:
 810                 sr_info("External clock, falling edge.");
 811                 acq->bypass_clockdiv = TRUE;
 812                 break;
 813         case CLOCK_SOURCE_EXT_RISE:
 814                 sr_info("External clock, rising edge.");
 815                 acq->bypass_clockdiv = TRUE;
 816                 break;
 817         default:
 818                 sr_err("No valid clock source has been configured.");
 819                 return SR_ERR;
 820         }
 821
 822         regvals[0].reg = REG_MEM_CTRL2;
 823         regvals[0].val = 2;
 824
 825         regvals[1].reg = REG_MEM_CTRL2;
 826         regvals[1].val = 1;
 827
 828         regvals[2].reg = REG_CMD_CTRL2;
 829         regvals[2].val = 10;
 830
 831         regvals[3].reg = REG_CMD_CTRL3;
 832         regvals[3].val = 0x74;
 833
 834         regvals[4].reg = REG_CMD_CTRL4;
 835         regvals[4].val = 0;
 836
 837         regvals[5].reg = REG_CMD_CTRL1;
 838         regvals[5].val = 0;
 839
 840         regvals[6].reg = REG_DIV_BYPASS;
 841         regvals[6].val = acq->bypass_clockdiv;
 842
 843         ret = lwla_write_regs(usb, regvals, G_N_ELEMENTS(regvals));
 844         if (ret != SR_OK)
 845                 return ret;
 846
 847         return capture_setup(sdi);
 848 }
 849
 850 /* Start the capture operation on the LWLA device.  Beginning with this
 851  * function, all USB transfers will be asynchronous until the end of the
 852  * acquisition session.
 853  */
 854 SR_PRIV int lwla_start_acquisition(const struct sr_dev_inst *sdi)
 855 {
 856         struct dev_context *devc;
 857         struct sr_usb_dev_inst *usb;
 858         struct acquisition_state *acq;
 859         struct regval_pair *regvals;
 860
 861         devc = sdi->priv;
 862         usb  = sdi->conn;
 863         acq  = devc->acquisition;
 864
 865         acq->duration_now  = 0;
 866         acq->mem_addr_fill = 0;
 867         acq->capture_flags = 0;
 868
 869         libusb_fill_bulk_transfer(acq->xfer_out, usb->devhdl, EP_COMMAND,
 870                                   (unsigned char *)acq->xfer_buf_out, 0,
 871                                   &receive_transfer_out,
 872                                   (struct sr_dev_inst *)sdi, USB_TIMEOUT);
 873
 874         libusb_fill_bulk_transfer(acq->xfer_in, usb->devhdl, EP_REPLY,
 875                                   (unsigned char *)acq->xfer_buf_in,
 876                                   sizeof acq->xfer_buf_in,
 877                                   &receive_transfer_in,
 878                                   (struct sr_dev_inst *)sdi, USB_TIMEOUT);
 879
 880         regvals = devc->reg_write_seq;
 881
 882         regvals[0].reg = REG_CMD_CTRL2;
 883         regvals[0].val = 10;
 884
 885         regvals[1].reg = REG_CMD_CTRL3;
 886         regvals[1].val = 1;
 887
 888         regvals[2].reg = REG_CMD_CTRL4;
 889         regvals[2].val = 0;
 890
 891         regvals[3].reg = REG_CMD_CTRL1;
 892         regvals[3].val = 0;
 893
 894         devc->reg_write_pos = 0;
 895         devc->reg_write_len = 4;
 896
 897         devc->state = STATE_START_CAPTURE;
 898
 899         return issue_next_write_reg(sdi);
 900 }
 901
 902 /* Allocate an acquisition state object.
 903  */
 904 SR_PRIV struct acquisition_state *lwla_alloc_acquisition_state(void)
 905 {
 906         struct acquisition_state *acq;
 907
 908         acq = g_try_new0(struct acquisition_state, 1);
 909         if (!acq) {
 910                 sr_err("Acquisition state malloc failed.");
 911                 return NULL;
 912         }
 913
 914         acq->xfer_in = libusb_alloc_transfer(0);
 915         if (!acq->xfer_in) {
 916                 sr_err("Transfer malloc failed.");
 917                 g_free(acq);
 918                 return NULL;
 919         }
 920
 921         acq->xfer_out = libusb_alloc_transfer(0);
 922         if (!acq->xfer_out) {
 923                 sr_err("Transfer malloc failed.");
 924                 libusb_free_transfer(acq->xfer_in);
 925                 g_free(acq);
 926                 return NULL;
 927         }
 928
 929         return acq;
 930 }
 931
 932 /* Deallocate an acquisition state object.
 933  */
 934 SR_PRIV void lwla_free_acquisition_state(struct acquisition_state *acq)
 935 {
 936         if (acq) {
 937                 libusb_free_transfer(acq->xfer_out);
 938                 libusb_free_transfer(acq->xfer_in);
 939                 g_free(acq);
 940         }
 941 }
 942
 943 /* USB I/O source callback.
 944  */
 945 SR_PRIV int lwla_receive_data(int fd, int revents, void *cb_data)
 946 {
 947         struct sr_dev_inst *sdi;
 948         struct dev_context *devc;
 949         struct drv_context *drvc;
 950         struct timeval tv;
 951         int ret;
 952
 953         (void)fd;
 954
 955         sdi  = cb_data;
 956         devc = sdi->priv;
 957         drvc = sdi->driver->priv;
 958
 959         if (!devc || !drvc)
 960                 return FALSE;
 961
 962         /* No timeout: return immediately. */
 963         tv.tv_sec  = 0;
 964         tv.tv_usec = 0;
 965
 966         ret = libusb_handle_events_timeout_completed(drvc->sr_ctx->libusb_ctx,
 967                                                      &tv, NULL);
 968         if (ret != 0)
 969                 sr_err("Event handling failed: %s.", libusb_error_name(ret));
 970
 971         /* If no event flags are set the timeout must have expired. */
 972         if (revents == 0 && devc->state == STATE_STATUS_WAIT) {
 973                 if (sdi->status == SR_ST_STOPPING)
 974                         issue_stop_capture(sdi);
 975                 else
 976                         request_capture_status(sdi);
 977         }
 978
 979         /* Check if an error occurred on a transfer. */
 980         if (devc->transfer_error)
 981                 end_acquisition(sdi);
 982
 983         return TRUE;
 984 }