hardware/saleae-logic16/protocol.c

   1 /*
   2  * This file is part of the libsigrok project.
   3  *
   4  * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se>
   5  * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
   6  * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
   7  *
   8  * This program is free software: you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation, either version 3 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include "protocol.h"
  23
  24 #include <stdint.h>
  25 #include <string.h>
  26 #include <glib.h>
  27 #include <glib/gstdio.h>
  28 #include <stdio.h>
  29 #include <errno.h>
  30 #include <math.h>
  31 #include "libsigrok.h"
  32 #include "libsigrok-internal.h"
  33
  34 #define FPGA_FIRMWARE_18        FIRMWARE_DIR"/saleae-logic16-fpga-18.bitstream"
  35 #define FPGA_FIRMWARE_33        FIRMWARE_DIR"/saleae-logic16-fpga-33.bitstream"
  36
  37 #define MAX_SAMPLE_RATE         SR_MHZ(100)
  38 #define MAX_4CH_SAMPLE_RATE     SR_MHZ(50)
  39 #define MAX_7CH_SAMPLE_RATE     SR_MHZ(40)
  40 #define MAX_8CH_SAMPLE_RATE     SR_MHZ(32)
  41 #define MAX_10CH_SAMPLE_RATE    SR_MHZ(25)
  42 #define MAX_13CH_SAMPLE_RATE    SR_MHZ(16)
  43
  44 #define BASE_CLOCK_0_FREQ       SR_MHZ(100)
  45 #define BASE_CLOCK_1_FREQ       SR_MHZ(160)
  46
  47 #define COMMAND_START_ACQUISITION       1
  48 #define COMMAND_ABORT_ACQUISITION_ASYNC 2
  49 #define COMMAND_WRITE_EEPROM            6
  50 #define COMMAND_READ_EEPROM             7
  51 #define COMMAND_WRITE_LED_TABLE         0x7a
  52 #define COMMAND_SET_LED_MODE            0x7b
  53 #define COMMAND_RETURN_TO_BOOTLOADER    0x7c
  54 #define COMMAND_ABORT_ACQUISITION_SYNC  0x7d
  55 #define COMMAND_FPGA_UPLOAD_INIT        0x7e
  56 #define COMMAND_FPGA_UPLOAD_SEND_DATA   0x7f
  57 #define COMMAND_FPGA_WRITE_REGISTER     0x80
  58 #define COMMAND_FPGA_READ_REGISTER      0x81
  59 #define COMMAND_GET_REVID               0x82
  60
  61 #define WRITE_EEPROM_COOKIE1            0x42
  62 #define WRITE_EEPROM_COOKIE2            0x55
  63 #define READ_EEPROM_COOKIE1             0x33
  64 #define READ_EEPROM_COOKIE2             0x81
  65 #define ABORT_ACQUISITION_SYNC_PATTERN  0x55
  66
  67 #define MAX_EMPTY_TRANSFERS             64
  68
  69
  70 static void encrypt(uint8_t *dest, const uint8_t *src, uint8_t cnt)
  71 {
  72         uint8_t state1 = 0x9b, state2 = 0x54;
  73         int i;
  74
  75         for (i=0; i<cnt; i++) {
  76                 uint8_t t, v = src[i];
  77                 t = (((v ^ state2 ^ 0x2b) - 0x05) ^ 0x35) - 0x39;
  78                 t = (((t ^ state1 ^ 0x5a) - 0xb0) ^ 0x38) - 0x45;
  79                 dest[i] = state2 = t;
  80                 state1 = v;
  81         }
  82 }
  83
  84 static void decrypt(uint8_t *dest, const uint8_t *src, uint8_t cnt)
  85 {
  86         uint8_t state1 = 0x9b, state2 = 0x54;
  87         int i;
  88         for (i=0; i<cnt; i++) {
  89                 uint8_t t, v = src[i];
  90                 t = (((v + 0x45) ^ 0x38) + 0xb0) ^ 0x5a ^ state1;
  91                 t = (((t + 0x39) ^ 0x35) + 0x05) ^ 0x2b ^ state2;
  92                 dest[i] = state1 = t;
  93                 state2 = v;
  94         }
  95 }
  96
  97 static int do_ep1_command(const struct sr_dev_inst *sdi,
  98                           const uint8_t *command, uint8_t cmd_len,
  99                           uint8_t *reply, uint8_t reply_len)
 100 {
 101         uint8_t buf[64];
 102         struct sr_usb_dev_inst *usb;
 103         int ret, xfer;
 104
 105         usb = sdi->conn;
 106
 107         if (cmd_len < 1 || cmd_len > 64 || reply_len > 64 ||
 108             command == NULL || (reply_len > 0 && reply == NULL))
 109                 return SR_ERR_ARG;
 110
 111         encrypt(buf, command, cmd_len);
 112
 113         ret = libusb_bulk_transfer(usb->devhdl, 1, buf, cmd_len, &xfer, 1000);
 114         if (ret != 0) {
 115                 sr_dbg("Failed to send EP1 command 0x%02x: %s",
 116                        command[0], libusb_error_name(ret));
 117                 return SR_ERR;
 118         }
 119         if (xfer != cmd_len) {
 120                 sr_dbg("Failed to send EP1 command 0x%02x: incorrect length %d != %d",
 121                        xfer, cmd_len);
 122                 return SR_ERR;
 123         }
 124
 125         if (reply_len == 0)
 126                 return SR_OK;
 127
 128         ret = libusb_bulk_transfer(usb->devhdl, 0x80 | 1, buf, reply_len, &xfer, 1000);
 129         if (ret != 0) {
 130                 sr_dbg("Failed to receive reply to EP1 command 0x%02x: %s",
 131                        command[0], libusb_error_name(ret));
 132                 return SR_ERR;
 133         }
 134         if (xfer != reply_len) {
 135                 sr_dbg("Failed to receive reply to EP1 command 0x%02x: incorrect length %d != %d",
 136                        xfer, reply_len);
 137                 return SR_ERR;
 138         }
 139
 140         decrypt(reply, buf, reply_len);
 141
 142         return SR_OK;
 143 }
 144
 145 static int read_eeprom(const struct sr_dev_inst *sdi,
 146                        uint8_t address, uint8_t length, uint8_t *buf)
 147 {
 148         uint8_t command[5] = {
 149                 COMMAND_READ_EEPROM,
 150                 READ_EEPROM_COOKIE1,
 151                 READ_EEPROM_COOKIE2,
 152                 address,
 153                 length,
 154         };
 155
 156         return do_ep1_command(sdi, command, 5, buf, length);
 157 }
 158
 159 static int upload_led_table(const struct sr_dev_inst *sdi,
 160                             const uint8_t *table, uint8_t offset, uint8_t cnt)
 161 {
 162         uint8_t command[64];
 163         int ret;
 164
 165         if (cnt < 1 || cnt+offset > 64 || table == NULL)
 166                 return SR_ERR_ARG;
 167
 168         while (cnt > 0) {
 169                 uint8_t chunk = (cnt > 32? 32 : cnt);
 170
 171                 command[0] = COMMAND_WRITE_LED_TABLE;
 172                 command[1] = offset;
 173                 command[2] = chunk;
 174                 memcpy(command+3, table, chunk);
 175
 176                 if ((ret = do_ep1_command(sdi, command, 3+chunk, NULL, 0)) != SR_OK)
 177                         return ret;
 178
 179                 table += chunk;
 180                 offset += chunk;
 181                 cnt -= chunk;
 182         }
 183
 184         return SR_OK;
 185 }
 186
 187 static int set_led_mode(const struct sr_dev_inst *sdi,
 188                         uint8_t animate, uint16_t t2reload, uint8_t div,
 189                         uint8_t repeat)
 190 {
 191         uint8_t command[6] = {
 192                 COMMAND_SET_LED_MODE,
 193                 animate,
 194                 t2reload&0xff,
 195                 t2reload>>8,
 196                 div,
 197                 repeat,
 198         };
 199
 200         return do_ep1_command(sdi, command, 6, NULL, 0);
 201 }
 202
 203 static int read_fpga_register(const struct sr_dev_inst *sdi,
 204                               uint8_t address, uint8_t *value)
 205 {
 206         uint8_t command[3] = {
 207                 COMMAND_FPGA_READ_REGISTER,
 208                 1,
 209                 address,
 210         };
 211
 212         return do_ep1_command(sdi, command, 3, value, 1);
 213 }
 214
 215 static int write_fpga_registers(const struct sr_dev_inst *sdi,
 216                                 uint8_t (*regs)[2], uint8_t cnt)
 217 {
 218         uint8_t command[64];
 219         int i;
 220
 221         if (cnt < 1 || cnt > 31)
 222                 return SR_ERR_ARG;
 223
 224         command[0] = COMMAND_FPGA_WRITE_REGISTER;
 225         command[1] = cnt;
 226         for (i=0; i<cnt; i++) {
 227                 command[2+2*i] = regs[i][0];
 228                 command[3+2*i] = regs[i][1];
 229         }
 230
 231         return do_ep1_command(sdi, command, 2*(cnt+1), NULL, 0);
 232 }
 233
 234 static int write_fpga_register(const struct sr_dev_inst *sdi,
 235                                uint8_t address, uint8_t value)
 236 {
 237         uint8_t regs[2] = { address, value };
 238         return write_fpga_registers(sdi, &regs, 1);
 239 }
 240
 241
 242 static uint8_t map_eeprom_data(uint8_t v)
 243 {
 244         return (((v ^ 0x80) + 0x44) ^ 0xd5) + 0x69;
 245 }
 246
 247 static int prime_fpga(const struct sr_dev_inst *sdi)
 248 {
 249         uint8_t eeprom_data[16];
 250         uint8_t old_reg_10, version;
 251         uint8_t regs[8][2] = {
 252                 {10, 0x00},
 253                 {10, 0x40},
 254                 {12, 0},
 255                 {10, 0xc0},
 256                 {10, 0x40},
 257                 { 6, 0},
 258                 { 7, 1},
 259                 { 7, 0}
 260         };
 261         int i, ret;
 262
 263         if ((ret = read_eeprom(sdi, 16, 16, eeprom_data)) != SR_OK)
 264                 return ret;
 265
 266         if ((ret = read_fpga_register(sdi, 10, &old_reg_10)) != SR_OK)
 267                 return ret;
 268
 269         regs[0][1] = (old_reg_10 &= 0x7f);
 270         regs[1][1] |= old_reg_10;
 271         regs[3][1] |= old_reg_10;
 272         regs[4][1] |= old_reg_10;
 273
 274         for (i=0; i<16; i++) {
 275                 regs[2][1] = eeprom_data[i];
 276                 regs[5][1] = map_eeprom_data(eeprom_data[i]);
 277                 if (i)
 278                         ret = write_fpga_registers(sdi, &regs[2], 6);
 279                 else
 280                         ret = write_fpga_registers(sdi, &regs[0], 8);
 281                 if (ret != SR_OK)
 282                         return ret;
 283         }
 284
 285         if ((ret = write_fpga_register(sdi, 10, old_reg_10)) != SR_OK)
 286                 return ret;
 287
 288         if ((ret = read_fpga_register(sdi, 0, &version)) != SR_OK)
 289                 return ret;
 290
 291         if (version != 0x10) {
 292                 sr_err("Invalid FPGA bitstream version: 0x%02x != 0x10", version);
 293                 return SR_ERR;
 294         }
 295
 296         return SR_OK;
 297 }
 298
 299 static void make_heartbeat(uint8_t *table, int len)
 300 {
 301         int i, j;
 302
 303         memset(table, 0, len);
 304         len >>= 3;
 305         for (i=0; i<2; i++)
 306                 for (j=0; j<len; j++)
 307                         *table++ = sin(j*M_PI/len)*255;
 308 }
 309
 310 static int configure_led(const struct sr_dev_inst *sdi)
 311 {
 312         uint8_t table[64];
 313         int ret;
 314
 315         make_heartbeat(table, 64);
 316         if ((ret = upload_led_table(sdi, table, 0, 64)) != SR_OK)
 317                 return ret;
 318
 319         return set_led_mode(sdi, 1, 6250, 0, 1);
 320 }
 321
 322 static int upload_fpga_bitstream(const struct sr_dev_inst *sdi,
 323                                  enum voltage_range vrange)
 324 {
 325         struct dev_context *devc;
 326         int offset, chunksize, ret;
 327         const char *filename;
 328         FILE *fw;
 329         unsigned char buf[256*62];
 330
 331         devc = sdi->priv;
 332
 333         if (devc->cur_voltage_range == vrange)
 334                 return SR_OK;
 335
 336         switch (vrange) {
 337         case VOLTAGE_RANGE_18_33_V:
 338                 filename = FPGA_FIRMWARE_18;
 339                 break;
 340         case VOLTAGE_RANGE_5_V:
 341                 filename = FPGA_FIRMWARE_33;
 342                 break;
 343         default:
 344                 sr_err("Unsupported voltage range");
 345                 return SR_ERR;
 346         }
 347
 348         sr_info("Uploading FPGA bitstream at %s", filename);
 349         if ((fw = g_fopen(filename, "rb")) == NULL) {
 350                 sr_err("Unable to open bitstream file %s for reading: %s",
 351                        filename, strerror(errno));
 352                 return SR_ERR;
 353         }
 354
 355         buf[0] = COMMAND_FPGA_UPLOAD_INIT;
 356         if ((ret = do_ep1_command(sdi, buf, 1, NULL, 0)) != SR_OK) {
 357                 fclose(fw);
 358                 return ret;
 359         }
 360
 361         while (1) {
 362                 chunksize = fread(buf, 1, sizeof(buf), fw);
 363                 if (chunksize == 0)
 364                         break;
 365
 366                 for (offset = 0; offset < chunksize; offset += 62) {
 367                         uint8_t command[64];
 368                         uint8_t len = (offset + 62 > chunksize?
 369                                        chunksize - offset : 62);
 370                         command[0] = COMMAND_FPGA_UPLOAD_SEND_DATA;
 371                         command[1] = len;
 372                         memcpy(command+2, buf+offset, len);
 373                         if ((ret = do_ep1_command(sdi, command, len+2, NULL, 0)) != SR_OK) {
 374                                 fclose(fw);
 375                                 return ret;
 376                         }
 377                 }
 378
 379                 sr_info("Uploaded %d bytes", chunksize);
 380         }
 381         fclose(fw);
 382         sr_info("FPGA bitstream upload done");
 383
 384         if ((ret = prime_fpga(sdi)) != SR_OK)
 385                 return ret;
 386
 387         if ((ret = configure_led(sdi)) != SR_OK)
 388                 return ret;
 389
 390         devc->cur_voltage_range = vrange;
 391         return SR_OK;
 392 }
 393
 394 static int abort_acquisition_sync(const struct sr_dev_inst *sdi)
 395 {
 396         static const uint8_t command[2] = {
 397                 COMMAND_ABORT_ACQUISITION_SYNC,
 398                 ABORT_ACQUISITION_SYNC_PATTERN,
 399         };
 400         uint8_t reply, expected_reply;
 401         int ret;
 402
 403         if ((ret = do_ep1_command(sdi, command, 2, &reply, 1)) != SR_OK)
 404                 return ret;
 405
 406         expected_reply = ~command[1];
 407         if (reply != expected_reply) {
 408                 sr_err("Invalid response for abort acquisition command: "
 409                        "0x%02x != 0x%02x", reply, expected_reply);
 410                 return SR_ERR;
 411         }
 412
 413         return SR_OK;
 414 }
 415
 416 SR_PRIV int saleae_logic16_setup_acquisition(const struct sr_dev_inst *sdi,
 417                                              uint64_t samplerate,
 418                                              uint16_t channels)
 419 {
 420         uint8_t clock_select, reg1, reg10;
 421         uint64_t div;
 422         int i, ret, nchan = 0;
 423         struct dev_context *devc;
 424
 425         devc = sdi->priv;
 426
 427         if (samplerate == 0 || samplerate > MAX_SAMPLE_RATE) {
 428                 sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate);
 429                 return SR_ERR;
 430         }
 431
 432         if (BASE_CLOCK_0_FREQ % samplerate == 0 &&
 433             (div = BASE_CLOCK_0_FREQ / samplerate) <= 256) {
 434                 clock_select = 0;
 435         } else if (BASE_CLOCK_1_FREQ % samplerate == 0 &&
 436                    (div = BASE_CLOCK_1_FREQ / samplerate) <= 256) {
 437                 clock_select = 1;
 438         } else {
 439                 sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate);
 440                 return SR_ERR;
 441         }
 442
 443         for (i=0; i<16; i++)
 444                 if (channels & (1U<<i))
 445                         nchan++;
 446
 447         if ((nchan >= 13 && samplerate > MAX_13CH_SAMPLE_RATE) ||
 448             (nchan >= 10 && samplerate > MAX_10CH_SAMPLE_RATE) ||
 449             (nchan >= 8  && samplerate > MAX_8CH_SAMPLE_RATE) ||
 450             (nchan >= 7  && samplerate > MAX_7CH_SAMPLE_RATE) ||
 451             (nchan >= 4  && samplerate > MAX_4CH_SAMPLE_RATE)) {
 452                 sr_err("Unable to sample at %" PRIu64 "Hz "
 453                        "with this many channels.", samplerate);
 454                 return SR_ERR;
 455         }
 456
 457         if ((ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range)) != SR_OK)
 458                 return ret;
 459
 460         if ((ret = read_fpga_register(sdi, 1, &reg1)) != SR_OK)
 461                 return ret;
 462
 463         if (reg1 != 0x08) {
 464                 sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x08", reg1);
 465                 return SR_ERR;
 466         }
 467
 468         if ((ret = write_fpga_register(sdi, 1, 0x40)) != SR_OK)
 469                 return ret;
 470
 471         if ((ret = write_fpga_register(sdi, 10, clock_select)) != SR_OK)
 472                 return ret;
 473
 474         if ((ret = write_fpga_register(sdi, 4, (uint8_t)(div-1))) != SR_OK)
 475                 return ret;
 476
 477         if ((ret = write_fpga_register(sdi, 2, (uint8_t)(channels & 0xff))) != SR_OK)
 478                 return ret;
 479
 480         if ((ret = write_fpga_register(sdi, 3, (uint8_t)(channels >> 8))) != SR_OK)
 481                 return ret;
 482
 483         if ((ret = write_fpga_register(sdi, 1, 0x42)) != SR_OK)
 484                 return ret;
 485
 486         if ((ret = write_fpga_register(sdi, 1, 0x40)) != SR_OK)
 487                 return ret;
 488
 489         if ((ret = read_fpga_register(sdi, 1, &reg1)) != SR_OK)
 490                 return ret;
 491
 492         if (reg1 != 0x48) {
 493                 sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x48", reg1);
 494                 return SR_ERR;
 495         }
 496
 497         if ((ret = read_fpga_register(sdi, 10, &reg10)) != SR_OK)
 498                 return ret;
 499
 500         if (reg10 != clock_select) {
 501                 sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x%02x",
 502                        reg10, (unsigned)clock_select);
 503                 return SR_ERR;
 504         }
 505
 506         return SR_OK;
 507 }
 508
 509 SR_PRIV int saleae_logic16_start_acquisition(const struct sr_dev_inst *sdi)
 510 {
 511         static const uint8_t command[1] = {
 512                 COMMAND_START_ACQUISITION,
 513         };
 514         int ret;
 515
 516         if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK)
 517                 return ret;
 518
 519         return write_fpga_register(sdi, 1, 0x41);
 520 }
 521
 522 SR_PRIV int saleae_logic16_abort_acquisition(const struct sr_dev_inst *sdi)
 523 {
 524         static const uint8_t command[1] = {
 525                 COMMAND_ABORT_ACQUISITION_ASYNC,
 526         };
 527         int ret;
 528         uint8_t reg1, reg8, reg9;
 529
 530         if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK)
 531                 return ret;
 532
 533         if ((ret = write_fpga_register(sdi, 1, 0x00)) != SR_OK)
 534                 return ret;
 535
 536         if ((ret = read_fpga_register(sdi, 1, &reg1)) != SR_OK)
 537                 return ret;
 538
 539         if (reg1 != 0x08) {
 540                 sr_dbg("Invalid state at acquisition stop: 0x%02x != 0x08", reg1);
 541                 return SR_ERR;
 542         }
 543
 544         if ((ret = read_fpga_register(sdi, 8, &reg8)) != SR_OK)
 545                 return ret;
 546
 547         if ((ret = read_fpga_register(sdi, 9, &reg9)) != SR_OK)
 548                 return ret;
 549
 550         return SR_OK;
 551 }
 552
 553 SR_PRIV int saleae_logic16_init_device(const struct sr_dev_inst *sdi)
 554 {
 555         struct dev_context *devc;
 556         int ret;
 557
 558         devc = sdi->priv;
 559
 560         devc->cur_voltage_range = VOLTAGE_RANGE_UNKNOWN;
 561
 562         if ((ret = abort_acquisition_sync(sdi)) != SR_OK)
 563                 return ret;
 564
 565         if ((ret = read_eeprom(sdi, 8, 8, devc->eeprom_data)) != SR_OK)
 566                 return ret;
 567
 568         if ((ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range)) != SR_OK)
 569                 return ret;
 570
 571         return SR_OK;
 572 }
 573
 574 static void finish_acquisition(struct dev_context *devc)
 575 {
 576         struct sr_datafeed_packet packet;
 577         int i;
 578
 579         /* Terminate session. */
 580         packet.type = SR_DF_END;
 581         sr_session_send(devc->cb_data, &packet);
 582
 583         /* Remove fds from polling. */
 584         if (devc->usbfd != NULL) {
 585                 for (i = 0; devc->usbfd[i] != -1; i++)
 586                         sr_source_remove(devc->usbfd[i]);
 587                 g_free(devc->usbfd);
 588         }
 589
 590         devc->num_transfers = 0;
 591         g_free(devc->transfers);
 592         g_free(devc->convbuffer);
 593 }
 594
 595 static void free_transfer(struct libusb_transfer *transfer)
 596 {
 597         struct dev_context *devc;
 598         unsigned int i;
 599
 600         devc = transfer->user_data;
 601
 602         g_free(transfer->buffer);
 603         transfer->buffer = NULL;
 604         libusb_free_transfer(transfer);
 605
 606         for (i = 0; i < devc->num_transfers; i++) {
 607                 if (devc->transfers[i] == transfer) {
 608                         devc->transfers[i] = NULL;
 609                         break;
 610                 }
 611         }
 612
 613         devc->submitted_transfers--;
 614         if (devc->submitted_transfers == 0)
 615                 finish_acquisition(devc);
 616 }
 617
 618 static void resubmit_transfer(struct libusb_transfer *transfer)
 619 {
 620         int ret;
 621
 622         if ((ret = libusb_submit_transfer(transfer)) == LIBUSB_SUCCESS)
 623                 return;
 624
 625         free_transfer(transfer);
 626         /* TODO: Stop session? */
 627
 628         sr_err("%s: %s", __func__, libusb_error_name(ret));
 629 }
 630
 631 static size_t convert_sample_data(struct dev_context *devc,
 632                                   uint8_t *dest, size_t destcnt,
 633                                   const uint8_t *src, size_t srccnt)
 634 {
 635         uint16_t *channel_data;
 636         int i, cur_channel;
 637         size_t ret = 0;
 638
 639         srccnt /= 2;
 640
 641         channel_data = devc->channel_data;
 642         cur_channel = devc->cur_channel;
 643
 644         while(srccnt--) {
 645                 uint16_t sample, channel_mask;
 646
 647                 sample = src[0] | (src[1] << 8);
 648                 src += 2;
 649
 650                 channel_mask = devc->channel_masks[cur_channel];
 651
 652                 for (i=15; i>=0; --i, sample >>= 1)
 653                         if (sample & 1)
 654                                 channel_data[i] |= channel_mask;
 655
 656                 if (++cur_channel == devc->num_channels) {
 657                         cur_channel = 0;
 658                         if (destcnt < 16*2) {
 659                                 sr_err("Conversion buffer too small!");
 660                                 break;
 661                         }
 662                         memcpy(dest, channel_data, 16*2);
 663                         memset(channel_data, 0, 16*2);
 664                         dest += 16*2;
 665                         ret += 16*2;
 666                         destcnt -= 16*2;
 667                 }
 668         }
 669
 670         devc->cur_channel = cur_channel;
 671
 672         return ret;
 673 }
 674
 675 SR_PRIV void saleae_logic16_receive_transfer(struct libusb_transfer *transfer)
 676 {
 677         gboolean packet_has_error = FALSE;
 678         struct sr_datafeed_packet packet;
 679         struct sr_datafeed_logic logic;
 680         struct dev_context *devc;
 681         size_t converted_length;
 682
 683         devc = transfer->user_data;
 684
 685         /*
 686          * If acquisition has already ended, just free any queued up
 687          * transfer that come in.
 688          */
 689         if (devc->num_samples < 0) {
 690                 free_transfer(transfer);
 691                 return;
 692         }
 693
 694         sr_info("receive_transfer(): status %d received %d bytes.",
 695                 transfer->status, transfer->actual_length);
 696
 697         switch (transfer->status) {
 698         case LIBUSB_TRANSFER_NO_DEVICE:
 699                 devc->num_samples = -2;
 700                 free_transfer(transfer);
 701                 return;
 702         case LIBUSB_TRANSFER_COMPLETED:
 703         case LIBUSB_TRANSFER_TIMED_OUT: /* We may have received some data though. */
 704                 break;
 705         default:
 706                 packet_has_error = TRUE;
 707                 break;
 708         }
 709
 710         if (transfer->actual_length & 1) {
 711                 sr_err("Got an odd number of bytes from the device.  This should not happen.");
 712                 /* Bail out right away */
 713                 packet_has_error = TRUE;
 714                 devc->empty_transfer_count = MAX_EMPTY_TRANSFERS;
 715         }
 716
 717         if (transfer->actual_length == 0 || packet_has_error) {
 718                 devc->empty_transfer_count++;
 719                 if (devc->empty_transfer_count > MAX_EMPTY_TRANSFERS) {
 720                         /*
 721                          * The FX2 gave up. End the acquisition, the frontend
 722                          * will work out that the samplecount is short.
 723                          */
 724                         devc->num_samples = -2;
 725                         free_transfer(transfer);
 726                 } else {
 727                         resubmit_transfer(transfer);
 728                 }
 729                 return;
 730         } else {
 731                 devc->empty_transfer_count = 0;
 732         }
 733
 734         converted_length =
 735                 convert_sample_data(devc,
 736                                     devc->convbuffer, devc->convbuffer_size,
 737                                     transfer->buffer, transfer->actual_length);
 738
 739         if (converted_length > 0) {
 740                 /* Send the incoming transfer to the session bus. */
 741                 packet.type = SR_DF_LOGIC;
 742                 packet.payload = &logic;
 743                 logic.length = converted_length;
 744                 logic.unitsize = 2;
 745                 logic.data = devc->convbuffer;
 746                 sr_session_send(devc->cb_data, &packet);
 747
 748                 devc->num_samples += converted_length / 2;
 749                 if (devc->limit_samples &&
 750                     (uint64_t)devc->num_samples > devc->limit_samples) {
 751                         devc->num_samples = -2;
 752                         free_transfer(transfer);
 753                         return;
 754                 }
 755         }
 756
 757         resubmit_transfer(transfer);
 758 }