hardware/saleae-logic16/protocol.c

   1 /*
   2  * This file is part of the libsigrok project.
   3  *
   4  * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se>
   5  *
   6  * This program is free software: you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation, either version 3 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "protocol.h"
  21
  22 #include <stdint.h>
  23 #include <string.h>
  24 #include <glib.h>
  25 #include <glib/gstdio.h>
  26 #include <stdio.h>
  27 #include <errno.h>
  28 #include <math.h>
  29 #include "libsigrok.h"
  30 #include "libsigrok-internal.h"
  31
  32 #define FPGA_FIRMWARE_18        FIRMWARE_DIR"/saleae-logic16-fpga-18.bitstream"
  33 #define FPGA_FIRMWARE_33        FIRMWARE_DIR"/saleae-logic16-fpga-33.bitstream"
  34
  35 #define MAX_SAMPLE_RATE         SR_MHZ(100)
  36 #define MAX_4CH_SAMPLE_RATE     SR_MHZ(50)
  37 #define MAX_7CH_SAMPLE_RATE     SR_MHZ(40)
  38 #define MAX_8CH_SAMPLE_RATE     SR_MHZ(32)
  39 #define MAX_10CH_SAMPLE_RATE    SR_MHZ(25)
  40 #define MAX_13CH_SAMPLE_RATE    SR_MHZ(16)
  41
  42 #define BASE_CLOCK_0_FREQ       SR_MHZ(100)
  43 #define BASE_CLOCK_1_FREQ       SR_MHZ(160)
  44
  45 #define COMMAND_START_ACQUISITION       1
  46 #define COMMAND_ABORT_ACQUISITION_ASYNC 2
  47 #define COMMAND_WRITE_EEPROM            6
  48 #define COMMAND_READ_EEPROM             7
  49 #define COMMAND_WRITE_LED_TABLE         0x7a
  50 #define COMMAND_SET_LED_MODE            0x7b
  51 #define COMMAND_RETURN_TO_BOOTLOADER    0x7c
  52 #define COMMAND_ABORT_ACQUISITION_SYNC  0x7d
  53 #define COMMAND_FPGA_UPLOAD_INIT        0x7e
  54 #define COMMAND_FPGA_UPLOAD_SEND_DATA   0x7f
  55 #define COMMAND_FPGA_WRITE_REGISTER     0x80
  56 #define COMMAND_FPGA_READ_REGISTER      0x81
  57 #define COMMAND_GET_REVID               0x82
  58
  59 #define WRITE_EEPROM_COOKIE1            0x42
  60 #define WRITE_EEPROM_COOKIE2            0x55
  61 #define READ_EEPROM_COOKIE1             0x33
  62 #define READ_EEPROM_COOKIE2             0x81
  63 #define ABORT_ACQUISITION_SYNC_PATTERN  0x55
  64
  65 #define MAX_EMPTY_TRANSFERS             64
  66
  67
  68 static void encrypt(uint8_t *dest, const uint8_t *src, uint8_t cnt)
  69 {
  70         uint8_t state1 = 0x9b, state2 = 0x54;
  71         int i;
  72
  73         for (i=0; i<cnt; i++) {
  74                 uint8_t t, v = src[i];
  75                 t = (((v ^ state2 ^ 0x2b) - 0x05) ^ 0x35) - 0x39;
  76                 t = (((t ^ state1 ^ 0x5a) - 0xb0) ^ 0x38) - 0x45;
  77                 dest[i] = state2 = t;
  78                 state1 = v;
  79         }
  80 }
  81
  82 static void decrypt(uint8_t *dest, const uint8_t *src, uint8_t cnt)
  83 {
  84         uint8_t state1 = 0x9b, state2 = 0x54;
  85         int i;
  86         for (i=0; i<cnt; i++) {
  87                 uint8_t t, v = src[i];
  88                 t = (((v + 0x45) ^ 0x38) + 0xb0) ^ 0x5a ^ state1;
  89                 t = (((t + 0x39) ^ 0x35) + 0x05) ^ 0x2b ^ state2;
  90                 dest[i] = state1 = t;
  91                 state2 = v;
  92         }
  93 }
  94
  95 static int do_ep1_command(const struct sr_dev_inst *sdi,
  96                           const uint8_t *command, uint8_t cmd_len,
  97                           uint8_t *reply, uint8_t reply_len)
  98 {
  99         uint8_t buf[64];
 100         struct sr_usb_dev_inst *usb;
 101         int ret, xfer;
 102
 103         usb = sdi->conn;
 104
 105         if (cmd_len < 1 || cmd_len > 64 || reply_len > 64 ||
 106             command == NULL || (reply_len > 0 && reply == NULL))
 107                 return SR_ERR_ARG;
 108
 109         encrypt(buf, command, cmd_len);
 110
 111         ret = libusb_bulk_transfer(usb->devhdl, 1, buf, cmd_len, &xfer, 1000);
 112         if (ret != 0) {
 113                 sr_dbg("Failed to send EP1 command 0x%02x: %s",
 114                        command[0], libusb_error_name(ret));
 115                 return SR_ERR;
 116         }
 117         if (xfer != cmd_len) {
 118                 sr_dbg("Failed to send EP1 command 0x%02x: incorrect length %d != %d",
 119                        xfer, cmd_len);
 120                 return SR_ERR;
 121         }
 122
 123         if (reply_len == 0)
 124                 return SR_OK;
 125
 126         ret = libusb_bulk_transfer(usb->devhdl, 0x80 | 1, buf, reply_len, &xfer, 1000);
 127         if (ret != 0) {
 128                 sr_dbg("Failed to receive reply to EP1 command 0x%02x: %s",
 129                        command[0], libusb_error_name(ret));
 130                 return SR_ERR;
 131         }
 132         if (xfer != reply_len) {
 133                 sr_dbg("Failed to receive reply to EP1 command 0x%02x: incorrect length %d != %d",
 134                        xfer, reply_len);
 135                 return SR_ERR;
 136         }
 137
 138         decrypt(reply, buf, reply_len);
 139
 140         return SR_OK;
 141 }
 142
 143 static int read_eeprom(const struct sr_dev_inst *sdi,
 144                        uint8_t address, uint8_t length, uint8_t *buf)
 145 {
 146         uint8_t command[5] = {
 147                 COMMAND_READ_EEPROM,
 148                 READ_EEPROM_COOKIE1,
 149                 READ_EEPROM_COOKIE2,
 150                 address,
 151                 length,
 152         };
 153
 154         return do_ep1_command(sdi, command, 5, buf, length);
 155 }
 156
 157 static int upload_led_table(const struct sr_dev_inst *sdi,
 158                             const uint8_t *table, uint8_t offset, uint8_t cnt)
 159 {
 160         uint8_t command[64];
 161         int ret;
 162
 163         if (cnt < 1 || cnt+offset > 64 || table == NULL)
 164                 return SR_ERR_ARG;
 165
 166         while (cnt > 0) {
 167                 uint8_t chunk = (cnt > 32? 32 : cnt);
 168
 169                 command[0] = COMMAND_WRITE_LED_TABLE;
 170                 command[1] = offset;
 171                 command[2] = chunk;
 172                 memcpy(command+3, table, chunk);
 173
 174                 if ((ret = do_ep1_command(sdi, command, 3+chunk, NULL, 0)) != SR_OK)
 175                         return ret;
 176
 177                 table += chunk;
 178                 offset += chunk;
 179                 cnt -= chunk;
 180         }
 181
 182         return SR_OK;
 183 }
 184
 185 static int set_led_mode(const struct sr_dev_inst *sdi,
 186                         uint8_t animate, uint16_t t2reload, uint8_t div,
 187                         uint8_t repeat)
 188 {
 189         uint8_t command[6] = {
 190                 COMMAND_SET_LED_MODE,
 191                 animate,
 192                 t2reload&0xff,
 193                 t2reload>>8,
 194                 div,
 195                 repeat,
 196         };
 197
 198         return do_ep1_command(sdi, command, 6, NULL, 0);
 199 }
 200
 201 static int read_fpga_register(const struct sr_dev_inst *sdi,
 202                               uint8_t address, uint8_t *value)
 203 {
 204         uint8_t command[3] = {
 205                 COMMAND_FPGA_READ_REGISTER,
 206                 1,
 207                 address,
 208         };
 209
 210         return do_ep1_command(sdi, command, 3, value, 1);
 211 }
 212
 213 static int write_fpga_registers(const struct sr_dev_inst *sdi,
 214                                 uint8_t (*regs)[2], uint8_t cnt)
 215 {
 216         uint8_t command[64];
 217         int i;
 218
 219         if (cnt < 1 || cnt > 31)
 220                 return SR_ERR_ARG;
 221
 222         command[0] = COMMAND_FPGA_WRITE_REGISTER;
 223         command[1] = cnt;
 224         for (i=0; i<cnt; i++) {
 225                 command[2+2*i] = regs[i][0];
 226                 command[3+2*i] = regs[i][1];
 227         }
 228
 229         return do_ep1_command(sdi, command, 2*(cnt+1), NULL, 0);
 230 }
 231
 232 static int write_fpga_register(const struct sr_dev_inst *sdi,
 233                                uint8_t address, uint8_t value)
 234 {
 235         uint8_t regs[2] = { address, value };
 236         return write_fpga_registers(sdi, &regs, 1);
 237 }
 238
 239
 240 static uint8_t map_eeprom_data(uint8_t v)
 241 {
 242         /* ??? */
 243         switch (v) {
 244         case 0x00: return 0x7a;
 245         case 0x01: return 0x79;
 246         case 0x05: return 0x85;
 247         case 0x10: return 0x6a;
 248         case 0x11: return 0x69;
 249         case 0x14: return 0x76;
 250         case 0x15: return 0x75;
 251         case 0x41: return 0x39;
 252         case 0x50: return 0x2a;
 253         case 0x51: return 0x29;
 254         case 0x55: return 0x35;
 255         default:
 256                 sr_err("No mapping of 0x%02x defined", v);
 257                 return 0xff;
 258         }
 259 }
 260
 261 static int prime_fpga(const struct sr_dev_inst *sdi)
 262 {
 263         uint8_t eeprom_data[16];
 264         uint8_t old_reg_10, status;
 265         uint8_t regs[8][2] = {
 266                 {10, 0x00},
 267                 {10, 0x40},
 268                 {12, 0},
 269                 {10, 0xc0},
 270                 {10, 0x40},
 271                 { 6, 0},
 272                 { 7, 1},
 273                 { 7, 0}
 274         };
 275         int i, ret;
 276
 277         if ((ret = read_eeprom(sdi, 16, 16, eeprom_data)) != SR_OK)
 278                 return ret;
 279
 280         if ((ret = read_fpga_register(sdi, 10, &old_reg_10)) != SR_OK)
 281                 return ret;
 282
 283         for (i=0; i<16; i++) {
 284                 regs[2][1] = eeprom_data[i];
 285                 regs[5][1] = map_eeprom_data(eeprom_data[i]);
 286                 if (i)
 287                         ret = write_fpga_registers(sdi, &regs[2], 6);
 288                 else
 289                         ret = write_fpga_registers(sdi, &regs[0], 8);
 290                 if (ret != SR_OK)
 291                         return ret;
 292         }
 293
 294         if ((ret = write_fpga_register(sdi, 10, old_reg_10)) != SR_OK)
 295                 return ret;
 296
 297         if ((ret = read_fpga_register(sdi, 0, &status)) != SR_OK)
 298                 return ret;
 299
 300         if (status != 0x10) {
 301                 sr_err("Invalid FPGA status: 0x%02x != 0x10", status);
 302                 return SR_ERR;
 303         }
 304
 305         return SR_OK;
 306 }
 307
 308 static void make_heartbeat(uint8_t *table, int len)
 309 {
 310         int i, j;
 311
 312         memset(table, 0, len);
 313         len >>= 3;
 314         for (i=0; i<2; i++)
 315                 for (j=0; j<len; j++)
 316                         *table++ = sin(j*M_PI/len)*255;
 317 }
 318
 319 static int configure_led(const struct sr_dev_inst *sdi)
 320 {
 321         uint8_t table[64];
 322         int ret;
 323
 324         make_heartbeat(table, 64);
 325         if ((ret = upload_led_table(sdi, table, 0, 64)) != SR_OK)
 326                 return ret;
 327
 328         return set_led_mode(sdi, 1, 6250, 0, 1);
 329 }
 330
 331 static int upload_fpga_bitstream(const struct sr_dev_inst *sdi,
 332                                  enum voltage_range vrange)
 333 {
 334         struct dev_context *devc;
 335         int offset, chunksize, ret;
 336         const char *filename;
 337         FILE *fw;
 338         unsigned char buf[256*62];
 339
 340         devc = sdi->priv;
 341
 342         if (devc->cur_voltage_range == vrange)
 343                 return SR_OK;
 344
 345         switch (vrange) {
 346         case VOLTAGE_RANGE_18_33_V:
 347                 filename = FPGA_FIRMWARE_18;
 348                 break;
 349         case VOLTAGE_RANGE_5_V:
 350                 filename = FPGA_FIRMWARE_33;
 351                 break;
 352         default:
 353                 sr_err("Unsupported voltage range");
 354                 return SR_ERR;
 355         }
 356
 357         sr_info("Uploading FPGA bitstream at %s", filename);
 358         if ((fw = g_fopen(filename, "rb")) == NULL) {
 359                 sr_err("Unable to open bitstream file %s for reading: %s",
 360                        filename, strerror(errno));
 361                 return SR_ERR;
 362         }
 363
 364         buf[0] = COMMAND_FPGA_UPLOAD_INIT;
 365         if ((ret = do_ep1_command(sdi, buf, 1, NULL, 0)) != SR_OK) {
 366                 fclose(fw);
 367                 return ret;
 368         }
 369
 370         while (1) {
 371                 chunksize = fread(buf, 1, sizeof(buf), fw);
 372                 if (chunksize == 0)
 373                         break;
 374
 375                 for (offset = 0; offset < chunksize; offset += 62) {
 376                         uint8_t command[64];
 377                         uint8_t len = (offset + 62 > chunksize?
 378                                        chunksize - offset : 62);
 379                         command[0] = COMMAND_FPGA_UPLOAD_SEND_DATA;
 380                         command[1] = len;
 381                         memcpy(command+2, buf+offset, len);
 382                         if ((ret = do_ep1_command(sdi, command, len+2, NULL, 0)) != SR_OK) {
 383                                 fclose(fw);
 384                                 return ret;
 385                         }
 386                 }
 387
 388                 sr_info("Uploaded %d bytes", chunksize);
 389         }
 390         fclose(fw);
 391         sr_info("FPGA bitstream upload done");
 392
 393         if ((ret = prime_fpga(sdi)) != SR_OK)
 394                 return ret;
 395
 396         if ((ret = configure_led(sdi)) != SR_OK)
 397                 return ret;
 398
 399         devc->cur_voltage_range = vrange;
 400         return SR_OK;
 401 }
 402
 403 static int abort_acquisition_sync(const struct sr_dev_inst *sdi)
 404 {
 405         static const uint8_t command[2] = {
 406                 COMMAND_ABORT_ACQUISITION_SYNC,
 407                 ABORT_ACQUISITION_SYNC_PATTERN,
 408         };
 409         uint8_t reply, expected_reply;
 410         int ret;
 411
 412         if ((ret = do_ep1_command(sdi, command, 2, &reply, 1)) != SR_OK)
 413                 return ret;
 414
 415         expected_reply = ~command[1];
 416         if (reply != expected_reply) {
 417                 sr_err("Invalid response for abort acquisition command: "
 418                        "0x%02x != 0x%02x", reply, expected_reply);
 419                 return SR_ERR;
 420         }
 421
 422         return SR_OK;
 423 }
 424
 425 SR_PRIV int saleae_logic16_setup_acquisition(const struct sr_dev_inst *sdi,
 426                                              uint64_t samplerate,
 427                                              uint16_t channels)
 428 {
 429         uint8_t clock_select, reg1, reg10;
 430         uint64_t div;
 431         int i, ret, nchan = 0;
 432         struct dev_context *devc;
 433
 434         devc = sdi->priv;
 435
 436         if (samplerate == 0 || samplerate > MAX_SAMPLE_RATE) {
 437                 sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate);
 438                 return SR_ERR;
 439         }
 440
 441         if (BASE_CLOCK_0_FREQ % samplerate == 0 &&
 442             (div = BASE_CLOCK_0_FREQ / samplerate) <= 256) {
 443                 clock_select = 0;
 444         } else if (BASE_CLOCK_1_FREQ % samplerate == 0 &&
 445                    (div = BASE_CLOCK_1_FREQ / samplerate) <= 256) {
 446                 clock_select = 1;
 447         } else {
 448                 sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate);
 449                 return SR_ERR;
 450         }
 451
 452         for (i=0; i<16; i++)
 453                 if (channels & (1U<<i))
 454                         nchan++;
 455
 456         if ((nchan >= 13 && samplerate > MAX_13CH_SAMPLE_RATE) ||
 457             (nchan >= 10 && samplerate > MAX_10CH_SAMPLE_RATE) ||
 458             (nchan >= 8  && samplerate > MAX_8CH_SAMPLE_RATE) ||
 459             (nchan >= 7  && samplerate > MAX_7CH_SAMPLE_RATE) ||
 460             (nchan >= 4  && samplerate > MAX_4CH_SAMPLE_RATE)) {
 461                 sr_err("Unable to sample at %" PRIu64 "Hz "
 462                        "with this many channels.", samplerate);
 463                 return SR_ERR;
 464         }
 465
 466         if ((ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range)) != SR_OK)
 467                 return ret;
 468
 469         if ((ret = read_fpga_register(sdi, 1, &reg1)) != SR_OK)
 470                 return ret;
 471
 472         if (reg1 != 0x08) {
 473                 sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x08", reg1);
 474                 return SR_ERR;
 475         }
 476
 477         if ((ret = write_fpga_register(sdi, 1, 0x40)) != SR_OK)
 478                 return ret;
 479
 480         if ((ret = write_fpga_register(sdi, 10, clock_select)) != SR_OK)
 481                 return ret;
 482
 483         if ((ret = write_fpga_register(sdi, 4, (uint8_t)(div-1))) != SR_OK)
 484                 return ret;
 485
 486         if ((ret = write_fpga_register(sdi, 2, (uint8_t)(channels & 0xff))) != SR_OK)
 487                 return ret;
 488
 489         if ((ret = write_fpga_register(sdi, 3, (uint8_t)(channels >> 8))) != SR_OK)
 490                 return ret;
 491
 492         if ((ret = write_fpga_register(sdi, 1, 0x42)) != SR_OK)
 493                 return ret;
 494
 495         if ((ret = write_fpga_register(sdi, 1, 0x40)) != SR_OK)
 496                 return ret;
 497
 498         if ((ret = read_fpga_register(sdi, 1, &reg1)) != SR_OK)
 499                 return ret;
 500
 501         if (reg1 != 0x48) {
 502                 sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x48", reg1);
 503                 return SR_ERR;
 504         }
 505
 506         if ((ret = read_fpga_register(sdi, 10, &reg10)) != SR_OK)
 507                 return ret;
 508
 509         if (reg10 != clock_select) {
 510                 sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x%02x",
 511                        reg10, (unsigned)clock_select);
 512                 return SR_ERR;
 513         }
 514
 515         return SR_OK;
 516 }
 517
 518 SR_PRIV int saleae_logic16_start_acquisition(const struct sr_dev_inst *sdi)
 519 {
 520         static const uint8_t command[1] = {
 521                 COMMAND_START_ACQUISITION,
 522         };
 523         int ret;
 524
 525         if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK)
 526                 return ret;
 527
 528         return write_fpga_register(sdi, 1, 0x41);
 529 }
 530
 531 SR_PRIV int saleae_logic16_abort_acquisition(const struct sr_dev_inst *sdi)
 532 {
 533         static const uint8_t command[1] = {
 534                 COMMAND_ABORT_ACQUISITION_ASYNC,
 535         };
 536         int ret;
 537         uint8_t reg1, reg8, reg9;
 538
 539         if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK)
 540                 return ret;
 541
 542         if ((ret = write_fpga_register(sdi, 1, 0x00)) != SR_OK)
 543                 return ret;
 544
 545         if ((ret = read_fpga_register(sdi, 1, &reg1)) != SR_OK)
 546                 return ret;
 547
 548         if (reg1 != 0x08) {
 549                 sr_dbg("Invalid state at acquisition stop: 0x%02x != 0x08", reg1);
 550                 return SR_ERR;
 551         }
 552
 553         if ((ret = read_fpga_register(sdi, 8, &reg8)) != SR_OK)
 554                 return ret;
 555
 556         if ((ret = read_fpga_register(sdi, 9, &reg9)) != SR_OK)
 557                 return ret;
 558
 559         return SR_OK;
 560 }
 561
 562 SR_PRIV int saleae_logic16_init_device(const struct sr_dev_inst *sdi)
 563 {
 564         struct dev_context *devc;
 565         int ret;
 566
 567         devc = sdi->priv;
 568
 569         devc->cur_voltage_range = VOLTAGE_RANGE_UNKNOWN;
 570
 571         if ((ret = abort_acquisition_sync(sdi)) != SR_OK)
 572                 return ret;
 573
 574         if ((ret = read_eeprom(sdi, 8, 8, devc->eeprom_data)) != SR_OK)
 575                 return ret;
 576
 577         if ((ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range)) != SR_OK)
 578                 return ret;
 579
 580         return SR_OK;
 581 }
 582
 583 static void finish_acquisition(struct dev_context *devc)
 584 {
 585         struct sr_datafeed_packet packet;
 586         int i;
 587
 588         /* Terminate session. */
 589         packet.type = SR_DF_END;
 590         sr_session_send(devc->cb_data, &packet);
 591
 592         /* Remove fds from polling. */
 593         if (devc->usbfd != NULL) {
 594                 for (i = 0; devc->usbfd[i] != -1; i++)
 595                         sr_source_remove(devc->usbfd[i]);
 596                 g_free(devc->usbfd);
 597         }
 598
 599         devc->num_transfers = 0;
 600         g_free(devc->transfers);
 601         g_free(devc->convbuffer);
 602 }
 603
 604 static void free_transfer(struct libusb_transfer *transfer)
 605 {
 606         struct dev_context *devc;
 607         unsigned int i;
 608
 609         devc = transfer->user_data;
 610
 611         g_free(transfer->buffer);
 612         transfer->buffer = NULL;
 613         libusb_free_transfer(transfer);
 614
 615         for (i = 0; i < devc->num_transfers; i++) {
 616                 if (devc->transfers[i] == transfer) {
 617                         devc->transfers[i] = NULL;
 618                         break;
 619                 }
 620         }
 621
 622         devc->submitted_transfers--;
 623         if (devc->submitted_transfers == 0)
 624                 finish_acquisition(devc);
 625 }
 626
 627 static void resubmit_transfer(struct libusb_transfer *transfer)
 628 {
 629         int ret;
 630
 631         if ((ret = libusb_submit_transfer(transfer)) == LIBUSB_SUCCESS)
 632                 return;
 633
 634         free_transfer(transfer);
 635         /* TODO: Stop session? */
 636
 637         sr_err("%s: %s", __func__, libusb_error_name(ret));
 638 }
 639
 640 static size_t convert_sample_data(struct dev_context *devc,
 641                                   uint8_t *dest, size_t destcnt,
 642                                   const uint8_t *src, size_t srccnt)
 643 {
 644         uint16_t *channel_data;
 645         int i, cur_channel;
 646         size_t ret = 0;
 647
 648         srccnt /= 2;
 649
 650         channel_data = devc->channel_data;
 651         cur_channel = devc->cur_channel;
 652
 653         while(srccnt--) {
 654                 uint16_t sample, channel_mask;
 655
 656                 sample = src[0] | (src[1] << 8);
 657                 src += 2;
 658
 659                 channel_mask = devc->channel_masks[cur_channel];
 660
 661                 for (i=15; i>=0; --i, sample >>= 1)
 662                         if (sample & 1)
 663                                 channel_data[i] |= channel_mask;
 664
 665                 if (++cur_channel == devc->num_channels) {
 666                         cur_channel = 0;
 667                         if (destcnt < 16*2) {
 668                                 sr_err("Conversion buffer too small!");
 669                                 break;
 670                         }
 671                         memcpy(dest, channel_data, 16*2);
 672                         memset(channel_data, 0, 16*2);
 673                         dest += 16*2;
 674                         ret += 16*2;
 675                         destcnt -= 16*2;
 676                 }
 677         }
 678
 679         devc->cur_channel = cur_channel;
 680
 681         return ret;
 682 }
 683
 684 SR_PRIV void saleae_logic16_receive_transfer(struct libusb_transfer *transfer)
 685 {
 686         gboolean packet_has_error = FALSE;
 687         struct sr_datafeed_packet packet;
 688         struct sr_datafeed_logic logic;
 689         struct dev_context *devc;
 690         size_t converted_length;
 691
 692         devc = transfer->user_data;
 693
 694         /*
 695          * If acquisition has already ended, just free any queued up
 696          * transfer that come in.
 697          */
 698         if (devc->num_samples < 0) {
 699                 free_transfer(transfer);
 700                 return;
 701         }
 702
 703         sr_info("receive_transfer(): status %d received %d bytes.",
 704                 transfer->status, transfer->actual_length);
 705
 706         switch (transfer->status) {
 707         case LIBUSB_TRANSFER_NO_DEVICE:
 708                 devc->num_samples = -2;
 709                 free_transfer(transfer);
 710                 return;
 711         case LIBUSB_TRANSFER_COMPLETED:
 712         case LIBUSB_TRANSFER_TIMED_OUT: /* We may have received some data though. */
 713                 break;
 714         default:
 715                 packet_has_error = TRUE;
 716                 break;
 717         }
 718
 719         if (transfer->actual_length & 1) {
 720                 sr_err("Got an odd number of bytes from the device.  This should not happen.");
 721                 /* Bail out right away */
 722                 packet_has_error = TRUE;
 723                 devc->empty_transfer_count = MAX_EMPTY_TRANSFERS;
 724         }
 725
 726         if (transfer->actual_length == 0 || packet_has_error) {
 727                 devc->empty_transfer_count++;
 728                 if (devc->empty_transfer_count > MAX_EMPTY_TRANSFERS) {
 729                         /*
 730                          * The FX2 gave up. End the acquisition, the frontend
 731                          * will work out that the samplecount is short.
 732                          */
 733                         devc->num_samples = -2;
 734                         free_transfer(transfer);
 735                 } else {
 736                         resubmit_transfer(transfer);
 737                 }
 738                 return;
 739         } else {
 740                 devc->empty_transfer_count = 0;
 741         }
 742
 743         converted_length =
 744                 convert_sample_data(devc,
 745                                     devc->convbuffer, devc->convbuffer_size,
 746                                     transfer->buffer, transfer->actual_length);
 747
 748         if (converted_length > 0) {
 749                 /* Send the incoming transfer to the session bus. */
 750                 packet.type = SR_DF_LOGIC;
 751                 packet.payload = &logic;
 752                 logic.length = converted_length;
 753                 logic.unitsize = 2;
 754                 logic.data = devc->convbuffer;
 755                 sr_session_send(devc->cb_data, &packet);
 756
 757                 devc->num_samples += converted_length / 2;
 758                 if (devc->limit_samples &&
 759                     (uint64_t)devc->num_samples > devc->limit_samples) {
 760                         devc->num_samples = -2;
 761                         free_transfer(transfer);
 762                         return;
 763                 }
 764         }
 765
 766         resubmit_transfer(transfer);
 767 }