2 * This file is part of the libsigrok project.
4 * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se>
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
25 #include <glib/gstdio.h>
29 #include "libsigrok.h"
30 #include "libsigrok-internal.h"
32 #define FPGA_FIRMWARE_18 FIRMWARE_DIR"/saleae-logic16-fpga-18.bitstream"
33 #define FPGA_FIRMWARE_33 FIRMWARE_DIR"/saleae-logic16-fpga-33.bitstream"
35 #define MAX_SAMPLE_RATE SR_MHZ(100)
36 #define MAX_4CH_SAMPLE_RATE SR_MHZ(50)
37 #define MAX_7CH_SAMPLE_RATE SR_MHZ(40)
38 #define MAX_8CH_SAMPLE_RATE SR_MHZ(32)
39 #define MAX_10CH_SAMPLE_RATE SR_MHZ(25)
40 #define MAX_13CH_SAMPLE_RATE SR_MHZ(16)
42 #define BASE_CLOCK_0_FREQ SR_MHZ(100)
43 #define BASE_CLOCK_1_FREQ SR_MHZ(160)
45 #define COMMAND_START_ACQUISITION 1
46 #define COMMAND_ABORT_ACQUISITION_ASYNC 2
47 #define COMMAND_WRITE_EEPROM 6
48 #define COMMAND_READ_EEPROM 7
49 #define COMMAND_WRITE_LED_TABLE 0x7a
50 #define COMMAND_SET_LED_MODE 0x7b
51 #define COMMAND_RETURN_TO_BOOTLOADER 0x7c
52 #define COMMAND_ABORT_ACQUISITION_SYNC 0x7d
53 #define COMMAND_FPGA_UPLOAD_INIT 0x7e
54 #define COMMAND_FPGA_UPLOAD_SEND_DATA 0x7f
55 #define COMMAND_FPGA_WRITE_REGISTER 0x80
56 #define COMMAND_FPGA_READ_REGISTER 0x81
57 #define COMMAND_GET_REVID 0x82
59 #define WRITE_EEPROM_COOKIE1 0x42
60 #define WRITE_EEPROM_COOKIE2 0x55
61 #define READ_EEPROM_COOKIE1 0x33
62 #define READ_EEPROM_COOKIE2 0x81
63 #define ABORT_ACQUISITION_SYNC_PATTERN 0x55
65 #define MAX_EMPTY_TRANSFERS 64
68 static void encrypt(uint8_t *dest, const uint8_t *src, uint8_t cnt)
70 uint8_t state1 = 0x9b, state2 = 0x54;
73 for (i=0; i<cnt; i++) {
74 uint8_t t, v = src[i];
75 t = (((v ^ state2 ^ 0x2b) - 0x05) ^ 0x35) - 0x39;
76 t = (((t ^ state1 ^ 0x5a) - 0xb0) ^ 0x38) - 0x45;
82 static void decrypt(uint8_t *dest, const uint8_t *src, uint8_t cnt)
84 uint8_t state1 = 0x9b, state2 = 0x54;
86 for (i=0; i<cnt; i++) {
87 uint8_t t, v = src[i];
88 t = (((v + 0x45) ^ 0x38) + 0xb0) ^ 0x5a ^ state1;
89 t = (((t + 0x39) ^ 0x35) + 0x05) ^ 0x2b ^ state2;
95 static int do_ep1_command(const struct sr_dev_inst *sdi,
96 const uint8_t *command, uint8_t cmd_len,
97 uint8_t *reply, uint8_t reply_len)
100 struct sr_usb_dev_inst *usb;
105 if (cmd_len < 1 || cmd_len > 64 || reply_len > 64 ||
106 command == NULL || (reply_len > 0 && reply == NULL))
109 encrypt(buf, command, cmd_len);
111 ret = libusb_bulk_transfer(usb->devhdl, 1, buf, cmd_len, &xfer, 1000);
113 sr_dbg("Failed to send EP1 command 0x%02x: %s",
114 command[0], libusb_error_name(ret));
117 if (xfer != cmd_len) {
118 sr_dbg("Failed to send EP1 command 0x%02x: incorrect length %d != %d",
126 ret = libusb_bulk_transfer(usb->devhdl, 0x80 | 1, buf, reply_len, &xfer, 1000);
128 sr_dbg("Failed to receive reply to EP1 command 0x%02x: %s",
129 command[0], libusb_error_name(ret));
132 if (xfer != reply_len) {
133 sr_dbg("Failed to receive reply to EP1 command 0x%02x: incorrect length %d != %d",
138 decrypt(reply, buf, reply_len);
143 static int read_eeprom(const struct sr_dev_inst *sdi,
144 uint8_t address, uint8_t length, uint8_t *buf)
146 uint8_t command[5] = {
154 return do_ep1_command(sdi, command, 5, buf, length);
157 static int upload_led_table(const struct sr_dev_inst *sdi,
158 const uint8_t *table, uint8_t offset, uint8_t cnt)
163 if (cnt < 1 || cnt+offset > 64 || table == NULL)
167 uint8_t chunk = (cnt > 32? 32 : cnt);
169 command[0] = COMMAND_WRITE_LED_TABLE;
172 memcpy(command+3, table, chunk);
174 if ((ret = do_ep1_command(sdi, command, 3+chunk, NULL, 0)) != SR_OK)
185 static int set_led_mode(const struct sr_dev_inst *sdi,
186 uint8_t animate, uint16_t t2reload, uint8_t div,
189 uint8_t command[6] = {
190 COMMAND_SET_LED_MODE,
198 return do_ep1_command(sdi, command, 6, NULL, 0);
201 static int read_fpga_register(const struct sr_dev_inst *sdi,
202 uint8_t address, uint8_t *value)
204 uint8_t command[3] = {
205 COMMAND_FPGA_READ_REGISTER,
210 return do_ep1_command(sdi, command, 3, value, 1);
213 static int write_fpga_registers(const struct sr_dev_inst *sdi,
214 uint8_t (*regs)[2], uint8_t cnt)
219 if (cnt < 1 || cnt > 31)
222 command[0] = COMMAND_FPGA_WRITE_REGISTER;
224 for (i=0; i<cnt; i++) {
225 command[2+2*i] = regs[i][0];
226 command[3+2*i] = regs[i][1];
229 return do_ep1_command(sdi, command, 2*(cnt+1), NULL, 0);
232 static int write_fpga_register(const struct sr_dev_inst *sdi,
233 uint8_t address, uint8_t value)
235 uint8_t regs[2] = { address, value };
236 return write_fpga_registers(sdi, ®s, 1);
240 static uint8_t map_eeprom_data(uint8_t v)
244 case 0x00: return 0x7a;
245 case 0x01: return 0x79;
246 case 0x05: return 0x85;
247 case 0x10: return 0x6a;
248 case 0x11: return 0x69;
249 case 0x14: return 0x76;
250 case 0x15: return 0x75;
251 case 0x41: return 0x39;
252 case 0x50: return 0x2a;
253 case 0x51: return 0x29;
254 case 0x55: return 0x35;
256 sr_err("No mapping of 0x%02x defined", v);
261 static int prime_fpga(const struct sr_dev_inst *sdi)
263 uint8_t eeprom_data[16];
264 uint8_t old_reg_10, status;
265 uint8_t regs[8][2] = {
277 if ((ret = read_eeprom(sdi, 16, 16, eeprom_data)) != SR_OK)
280 if ((ret = read_fpga_register(sdi, 10, &old_reg_10)) != SR_OK)
283 for (i=0; i<16; i++) {
284 regs[2][1] = eeprom_data[i];
285 regs[5][1] = map_eeprom_data(eeprom_data[i]);
287 ret = write_fpga_registers(sdi, ®s[2], 6);
289 ret = write_fpga_registers(sdi, ®s[0], 8);
294 if ((ret = write_fpga_register(sdi, 10, old_reg_10)) != SR_OK)
297 if ((ret = read_fpga_register(sdi, 0, &status)) != SR_OK)
300 if (status != 0x10) {
301 sr_err("Invalid FPGA status: 0x%02x != 0x10", status);
308 static void make_heartbeat(uint8_t *table, int len)
312 memset(table, 0, len);
315 for (j=0; j<len; j++)
316 *table++ = sin(j*M_PI/len)*255;
319 static int configure_led(const struct sr_dev_inst *sdi)
324 make_heartbeat(table, 64);
325 if ((ret = upload_led_table(sdi, table, 0, 64)) != SR_OK)
328 return set_led_mode(sdi, 1, 6250, 0, 1);
331 static int upload_fpga_bitstream(const struct sr_dev_inst *sdi,
332 enum voltage_range vrange)
334 struct dev_context *devc;
335 int offset, chunksize, ret;
336 const char *filename;
338 unsigned char buf[256*62];
342 if (devc->cur_voltage_range == vrange)
346 case VOLTAGE_RANGE_18_33_V:
347 filename = FPGA_FIRMWARE_18;
349 case VOLTAGE_RANGE_5_V:
350 filename = FPGA_FIRMWARE_33;
353 sr_err("Unsupported voltage range");
357 sr_info("Uploading FPGA bitstream at %s", filename);
358 if ((fw = g_fopen(filename, "rb")) == NULL) {
359 sr_err("Unable to open bitstream file %s for reading: %s",
360 filename, strerror(errno));
364 buf[0] = COMMAND_FPGA_UPLOAD_INIT;
365 if ((ret = do_ep1_command(sdi, buf, 1, NULL, 0)) != SR_OK) {
371 chunksize = fread(buf, 1, sizeof(buf), fw);
375 for (offset = 0; offset < chunksize; offset += 62) {
377 uint8_t len = (offset + 62 > chunksize?
378 chunksize - offset : 62);
379 command[0] = COMMAND_FPGA_UPLOAD_SEND_DATA;
381 memcpy(command+2, buf+offset, len);
382 if ((ret = do_ep1_command(sdi, command, len+2, NULL, 0)) != SR_OK) {
388 sr_info("Uploaded %d bytes", chunksize);
391 sr_info("FPGA bitstream upload done");
393 if ((ret = prime_fpga(sdi)) != SR_OK)
396 if ((ret = configure_led(sdi)) != SR_OK)
399 devc->cur_voltage_range = vrange;
403 static int abort_acquisition_sync(const struct sr_dev_inst *sdi)
405 static const uint8_t command[2] = {
406 COMMAND_ABORT_ACQUISITION_SYNC,
407 ABORT_ACQUISITION_SYNC_PATTERN,
409 uint8_t reply, expected_reply;
412 if ((ret = do_ep1_command(sdi, command, 2, &reply, 1)) != SR_OK)
415 expected_reply = ~command[1];
416 if (reply != expected_reply) {
417 sr_err("Invalid response for abort acquisition command: "
418 "0x%02x != 0x%02x", reply, expected_reply);
425 SR_PRIV int saleae_logic16_setup_acquisition(const struct sr_dev_inst *sdi,
429 uint8_t clock_select, reg1, reg10;
431 int i, ret, nchan = 0;
433 if (samplerate == 0 || samplerate > MAX_SAMPLE_RATE) {
434 sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate);
438 if (BASE_CLOCK_0_FREQ % samplerate == 0 &&
439 (div = BASE_CLOCK_0_FREQ / samplerate) <= 256) {
441 } else if (BASE_CLOCK_1_FREQ % samplerate == 0 &&
442 (div = BASE_CLOCK_1_FREQ / samplerate) <= 256) {
445 sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate);
450 if (channels & (1U<<i))
453 if ((nchan >= 13 && samplerate > MAX_13CH_SAMPLE_RATE) ||
454 (nchan >= 10 && samplerate > MAX_10CH_SAMPLE_RATE) ||
455 (nchan >= 8 && samplerate > MAX_8CH_SAMPLE_RATE) ||
456 (nchan >= 7 && samplerate > MAX_7CH_SAMPLE_RATE) ||
457 (nchan >= 4 && samplerate > MAX_4CH_SAMPLE_RATE)) {
458 sr_err("Unable to sample at %" PRIu64 "Hz "
459 "with this many channels.", samplerate);
463 if ((ret = read_fpga_register(sdi, 1, ®1)) != SR_OK)
467 sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x08", reg1);
471 if ((ret = write_fpga_register(sdi, 1, 0x40)) != SR_OK)
474 if ((ret = write_fpga_register(sdi, 10, clock_select)) != SR_OK)
477 if ((ret = write_fpga_register(sdi, 4, (uint8_t)(div-1))) != SR_OK)
480 if ((ret = write_fpga_register(sdi, 2, (uint8_t)(channels & 0xff))) != SR_OK)
483 if ((ret = write_fpga_register(sdi, 3, (uint8_t)(channels >> 8))) != SR_OK)
486 if ((ret = write_fpga_register(sdi, 1, 0x42)) != SR_OK)
489 if ((ret = write_fpga_register(sdi, 1, 0x40)) != SR_OK)
492 if ((ret = read_fpga_register(sdi, 1, ®1)) != SR_OK)
496 sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x48", reg1);
500 if ((ret = read_fpga_register(sdi, 10, ®10)) != SR_OK)
503 if (reg10 != clock_select) {
504 sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x%02x",
505 reg10, (unsigned)clock_select);
512 SR_PRIV int saleae_logic16_start_acquisition(const struct sr_dev_inst *sdi)
514 static const uint8_t command[1] = {
515 COMMAND_START_ACQUISITION,
519 if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK)
522 return write_fpga_register(sdi, 1, 0x41);
525 SR_PRIV int saleae_logic16_abort_acquisition(const struct sr_dev_inst *sdi)
527 static const uint8_t command[1] = {
528 COMMAND_ABORT_ACQUISITION_ASYNC,
531 uint8_t reg1, reg8, reg9;
533 if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK)
536 if ((ret = write_fpga_register(sdi, 1, 0x00)) != SR_OK)
539 if ((ret = read_fpga_register(sdi, 1, ®1)) != SR_OK)
543 sr_dbg("Invalid state at acquisition stop: 0x%02x != 0x08", reg1);
547 if ((ret = read_fpga_register(sdi, 8, ®8)) != SR_OK)
550 if ((ret = read_fpga_register(sdi, 9, ®9)) != SR_OK)
556 SR_PRIV int saleae_logic16_init_device(const struct sr_dev_inst *sdi)
558 struct dev_context *devc;
563 devc->cur_voltage_range = VOLTAGE_RANGE_UNKNOWN;
565 if ((ret = abort_acquisition_sync(sdi)) != SR_OK)
568 if ((ret = read_eeprom(sdi, 8, 8, devc->eeprom_data)) != SR_OK)
571 if ((ret = upload_fpga_bitstream(sdi, VOLTAGE_RANGE_18_33_V)) != SR_OK)
577 static void finish_acquisition(struct dev_context *devc)
579 struct sr_datafeed_packet packet;
582 /* Terminate session. */
583 packet.type = SR_DF_END;
584 sr_session_send(devc->cb_data, &packet);
586 /* Remove fds from polling. */
587 if (devc->usbfd != NULL) {
588 for (i = 0; devc->usbfd[i] != -1; i++)
589 sr_source_remove(devc->usbfd[i]);
593 devc->num_transfers = 0;
594 g_free(devc->transfers);
595 g_free(devc->convbuffer);
598 static void free_transfer(struct libusb_transfer *transfer)
600 struct dev_context *devc;
603 devc = transfer->user_data;
605 g_free(transfer->buffer);
606 transfer->buffer = NULL;
607 libusb_free_transfer(transfer);
609 for (i = 0; i < devc->num_transfers; i++) {
610 if (devc->transfers[i] == transfer) {
611 devc->transfers[i] = NULL;
616 devc->submitted_transfers--;
617 if (devc->submitted_transfers == 0)
618 finish_acquisition(devc);
621 static void resubmit_transfer(struct libusb_transfer *transfer)
625 if ((ret = libusb_submit_transfer(transfer)) == LIBUSB_SUCCESS)
628 free_transfer(transfer);
629 /* TODO: Stop session? */
631 sr_err("%s: %s", __func__, libusb_error_name(ret));
634 static size_t convert_sample_data(struct dev_context *devc,
635 uint8_t *dest, size_t destcnt,
636 const uint8_t *src, size_t srccnt)
638 uint16_t *channel_data;
644 channel_data = devc->channel_data;
645 cur_channel = devc->cur_channel;
648 uint16_t sample, channel_mask;
650 sample = src[0] | (src[1] << 8);
653 channel_mask = devc->channel_masks[cur_channel];
655 for (i=15; i>=0; --i, sample >>= 1)
657 channel_data[i] |= channel_mask;
659 if (++cur_channel == devc->num_channels) {
661 if (destcnt < 16*2) {
662 sr_err("Conversion buffer too small!");
665 memcpy(dest, channel_data, 16*2);
666 memset(channel_data, 0, 16*2);
673 devc->cur_channel = cur_channel;
678 SR_PRIV void saleae_logic16_receive_transfer(struct libusb_transfer *transfer)
680 gboolean packet_has_error = FALSE;
681 struct sr_datafeed_packet packet;
682 struct sr_datafeed_logic logic;
683 struct dev_context *devc;
684 size_t converted_length;
686 devc = transfer->user_data;
689 * If acquisition has already ended, just free any queued up
690 * transfer that come in.
692 if (devc->num_samples < 0) {
693 free_transfer(transfer);
697 sr_info("receive_transfer(): status %d received %d bytes.",
698 transfer->status, transfer->actual_length);
700 switch (transfer->status) {
701 case LIBUSB_TRANSFER_NO_DEVICE:
702 devc->num_samples = -2;
703 free_transfer(transfer);
705 case LIBUSB_TRANSFER_COMPLETED:
706 case LIBUSB_TRANSFER_TIMED_OUT: /* We may have received some data though. */
709 packet_has_error = TRUE;
713 if (transfer->actual_length & 1) {
714 sr_err("Got an odd number of bytes from the device. This should not happen.");
715 /* Bail out right away */
716 packet_has_error = TRUE;
717 devc->empty_transfer_count = MAX_EMPTY_TRANSFERS;
720 if (transfer->actual_length == 0 || packet_has_error) {
721 devc->empty_transfer_count++;
722 if (devc->empty_transfer_count > MAX_EMPTY_TRANSFERS) {
724 * The FX2 gave up. End the acquisition, the frontend
725 * will work out that the samplecount is short.
727 devc->num_samples = -2;
728 free_transfer(transfer);
730 resubmit_transfer(transfer);
734 devc->empty_transfer_count = 0;
738 convert_sample_data(devc,
739 devc->convbuffer, devc->convbuffer_size,
740 transfer->buffer, transfer->actual_length);
742 if (converted_length > 0) {
743 /* Send the incoming transfer to the session bus. */
744 packet.type = SR_DF_LOGIC;
745 packet.payload = &logic;
746 logic.length = converted_length;
748 logic.data = devc->convbuffer;
749 sr_session_send(devc->cb_data, &packet);
751 devc->num_samples += converted_length / 2;
752 if (devc->limit_samples &&
753 (uint64_t)devc->num_samples > devc->limit_samples) {
754 devc->num_samples = -2;
755 free_transfer(transfer);
760 resubmit_transfer(transfer);