hardware/rigol-ds/protocol.c

   1 /*
   2  * This file is part of the libsigrok project.
   3  *
   4  * Copyright (C) 2012 Martin Ling <martin-git@earth.li>
   5  * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
   6  * Copyright (C) 2013 Mathias Grimmberger <mgri@zaphod.sax.de>
   7  *
   8  * This program is free software: you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation, either version 3 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <stdlib.h>
  23 #include <stdarg.h>
  24 #include <unistd.h>
  25 #include <errno.h>
  26 #include <string.h>
  27 #include <math.h>
  28 #include <ctype.h>
  29 #include <time.h>
  30 #include <glib.h>
  31 #include "libsigrok.h"
  32 #include "libsigrok-internal.h"
  33 #include "protocol.h"
  34
  35 /*
  36  * This is a unified protocol driver for the DS1000 and DS2000 series.
  37  *
  38  * DS1000 support tested with a Rigol DS1102D.
  39  *
  40  * DS2000 support tested with a Rigol DS2072 using firmware version 01.01.00.02.
  41  *
  42  * The Rigol DS2000 series scopes try to adhere to the IEEE 488.2 (I think)
  43  * standard. If you want to read it - it costs real money...
  44  *
  45  * Every response from the scope has a linefeed appended because the
  46  * standard says so. In principle this could be ignored because sending the
  47  * next command clears the output queue of the scope. This driver tries to
  48  * avoid doing that because it may cause an error being generated inside the
  49  * scope and who knows what bugs the firmware has WRT this.
  50  *
  51  * Waveform data is transferred in a format called "arbitrary block program
  52  * data" specified in IEEE 488.2. See Agilents programming manuals for their
  53  * 2000/3000 series scopes for a nice description.
  54  *
  55  * Each data block from the scope has a header, e.g. "#900000001400".
  56  * The '#' marks the start of a block.
  57  * Next is one ASCII decimal digit between 1 and 9, this gives the number of
  58  * ASCII decimal digits following.
  59  * Last are the ASCII decimal digits giving the number of bytes (not
  60  * samples!) in the block.
  61  *
  62  * After this header as many data bytes as indicated follow.
  63  *
  64  * Each data block has a trailing linefeed too.
  65  */
  66
  67 static int parse_int(const char *str, int *ret)
  68 {
  69         char *e;
  70         long tmp;
  71
  72         errno = 0;
  73         tmp = strtol(str, &e, 10);
  74         if (e == str || *e != '\0') {
  75                 sr_dbg("Failed to parse integer: '%s'", str);
  76                 return SR_ERR;
  77         }
  78         if (errno) {
  79                 sr_dbg("Failed to parse integer: '%s', numerical overflow", str);
  80                 return SR_ERR;
  81         }
  82         if (tmp > INT_MAX || tmp < INT_MIN) {
  83                 sr_dbg("Failed to parse integer: '%s', value to large/small", str);
  84                 return SR_ERR;
  85         }
  86
  87         *ret = (int)tmp;
  88         return SR_OK;
  89 }
  90
  91 /* Set the next event to wait for in rigol_ds_receive */
  92 static void rigol_ds_set_wait_event(struct dev_context *devc, enum wait_events event)
  93 {
  94         if (event == WAIT_STOP)
  95                 devc->wait_status = 2;
  96         else
  97                 devc->wait_status = 1;
  98         devc->wait_event = event;
  99 }
 100
 101 /*
 102  * Waiting for a event will return a timeout after 2 to 3 seconds in order
 103  * to not block the application.
 104  */
 105 static int rigol_ds_event_wait(const struct sr_dev_inst *sdi, char status1, char status2)
 106 {
 107         char *buf;
 108         struct dev_context *devc;
 109         time_t start;
 110
 111         if (!(devc = sdi->priv))
 112                 return SR_ERR;
 113
 114         start = time(NULL);
 115
 116         /*
 117          * Trigger status may return:
 118          * "TD" or "T'D" - triggered
 119          * "AUTO"        - autotriggered
 120          * "RUN"         - running
 121          * "WAIT"        - waiting for trigger
 122          * "STOP"        - stopped
 123          */
 124
 125         if (devc->wait_status == 1) {
 126                 do {
 127                         if (time(NULL) - start >= 3) {
 128                                 sr_dbg("Timeout waiting for trigger");
 129                                 return SR_ERR_TIMEOUT;
 130                         }
 131
 132                         if (sr_scpi_get_string(sdi->conn, ":TRIG:STAT?", &buf) != SR_OK)
 133                                 return SR_ERR;
 134                 } while (buf[0] == status1 || buf[0] == status2);
 135
 136                 devc->wait_status = 2;
 137         }
 138         if (devc->wait_status == 2) {
 139                 do {
 140                         if (time(NULL) - start >= 3) {
 141                                 sr_dbg("Timeout waiting for trigger");
 142                                 return SR_ERR_TIMEOUT;
 143                         }
 144
 145                         if (sr_scpi_get_string(sdi->conn, ":TRIG:STAT?", &buf) != SR_OK)
 146                                 return SR_ERR;
 147                 } while (buf[0] != status1 && buf[0] != status2);
 148
 149                 rigol_ds_set_wait_event(devc, WAIT_NONE);
 150         }
 151
 152         return SR_OK;
 153 }
 154
 155 /*
 156  * For live capture we need to wait for a new trigger event to ensure that
 157  * sample data is not returned twice.
 158  *
 159  * Unfortunately this will never really work because for sufficiently fast
 160  * timebases and trigger rates it just can't catch the status changes.
 161  *
 162  * What would be needed is a trigger event register with autoreset like the
 163  * Agilents have. The Rigols don't seem to have anything like this.
 164  *
 165  * The workaround is to only wait for the trigger when the timebase is slow
 166  * enough. Of course this means that for faster timebases sample data can be
 167  * returned multiple times, this effect is mitigated somewhat by sleeping
 168  * for about one sweep time in that case.
 169  */
 170 static int rigol_ds_trigger_wait(const struct sr_dev_inst *sdi)
 171 {
 172         struct dev_context *devc;
 173         long s;
 174
 175         if (!(devc = sdi->priv))
 176                 return SR_ERR;
 177
 178         /*
 179          * If timebase < 50 msecs/DIV just sleep about one sweep time except
 180          * for really fast sweeps.
 181          */
 182         if (devc->timebase < 0.0499) {
 183                 if (devc->timebase > 0.99e-6) {
 184                         /*
 185                          * Timebase * num hor. divs * 85(%) * 1e6(usecs) / 100
 186                          * -> 85 percent of sweep time
 187                          */
 188                         s = (devc->timebase * devc->model->num_horizontal_divs
 189                              * 85e6) / 100L;
 190                         sr_spew("Sleeping for %ld usecs instead of trigger-wait", s);
 191                         g_usleep(s);
 192                 }
 193                 rigol_ds_set_wait_event(devc, WAIT_NONE);
 194                 return SR_OK;
 195         } else {
 196                 return rigol_ds_event_wait(sdi, 'T', 'A');
 197         }
 198 }
 199
 200 /* Wait for scope to got to "Stop" in single shot mode */
 201 static int rigol_ds_stop_wait(const struct sr_dev_inst *sdi)
 202 {
 203         return rigol_ds_event_wait(sdi, 'S', 'S');
 204 }
 205
 206 /* Check that a single shot acquisition actually succeeded on the DS2000 */
 207 static int rigol_ds_check_stop(const struct sr_dev_inst *sdi)
 208 {
 209         struct dev_context *devc;
 210         struct sr_probe *probe;
 211         int tmp;
 212
 213         if (!(devc = sdi->priv))
 214                 return SR_ERR;
 215
 216         probe = devc->channel_entry->data;
 217
 218         if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d",
 219                           probe->index + 1) != SR_OK)
 220                 return SR_ERR;
 221         /* Check that the number of samples will be accepted */
 222         if (rigol_ds_config_set(sdi, ":WAV:POIN %d", devc->analog_frame_size) != SR_OK)
 223                 return SR_ERR;
 224         if (sr_scpi_get_int(sdi->conn, "*ESR?", &tmp) != SR_OK)
 225                 return SR_ERR;
 226         /*
 227          * If we get an "Execution error" the scope went from "Single" to
 228          * "Stop" without actually triggering. There is no waveform
 229          * displayed and trying to download one will fail - the scope thinks
 230          * it has 1400 samples (like display memory) and the driver thinks
 231          * it has a different number of samples.
 232          *
 233          * In that case just try to capture something again. Might still
 234          * fail in interesting ways.
 235          *
 236          * Ain't firmware fun?
 237          */
 238         if (tmp & 0x10) {
 239                 sr_warn("Single shot acquisition failed, retrying...");
 240                 /* Sleep a bit, otherwise the single shot will often fail */
 241                 g_usleep(500000);
 242                 rigol_ds_config_set(sdi, ":SING");
 243                 rigol_ds_set_wait_event(devc, WAIT_STOP);
 244                 return SR_ERR;
 245         }
 246
 247         return SR_OK;
 248 }
 249
 250 /* Wait for enough data becoming available in scope output buffer */
 251 static int rigol_ds_block_wait(const struct sr_dev_inst *sdi)
 252 {
 253         char *buf;
 254         struct dev_context *devc;
 255         time_t start;
 256         int len;
 257
 258         if (!(devc = sdi->priv))
 259                 return SR_ERR;
 260
 261         start = time(NULL);
 262
 263         do {
 264                 if (time(NULL) - start >= 3) {
 265                         sr_dbg("Timeout waiting for data block");
 266                         return SR_ERR_TIMEOUT;
 267                 }
 268
 269                 /*
 270                  * The scope copies data really slowly from sample
 271                  * memory to its output buffer, so try not to bother
 272                  * it too much with SCPI requests but don't wait too
 273                  * long for short sample frame sizes.
 274                  */
 275                 g_usleep(devc->analog_frame_size < 15000 ? 100000 : 1000000);
 276
 277                 /* "READ,nnnn" (still working) or "IDLE,nnnn" (finished) */
 278                 if (sr_scpi_get_string(sdi->conn, ":WAV:STAT?", &buf) != SR_OK)
 279                         return SR_ERR;
 280
 281                 if (parse_int(buf + 5, &len) != SR_OK)
 282                         return SR_ERR;
 283         } while (buf[0] == 'R' && len < 1000000);
 284
 285         rigol_ds_set_wait_event(devc, WAIT_NONE);
 286
 287         return SR_OK;
 288 }
 289
 290 /* Send a configuration setting. */
 291 SR_PRIV int rigol_ds_config_set(const struct sr_dev_inst *sdi, const char *format, ...)
 292 {
 293         struct dev_context *devc = sdi->priv;
 294         va_list args;
 295         int ret;
 296
 297         va_start(args, format);
 298         ret = sr_scpi_send_variadic(sdi->conn, format, args);
 299         va_end(args);
 300
 301         if (ret != SR_OK)
 302                 return SR_ERR;
 303
 304         if (devc->model->series == RIGOL_DS1000) {
 305                 /* The DS1000 series needs this stupid delay, *OPC? doesn't work. */
 306                 sr_spew("delay %dms", 100);
 307                 g_usleep(100000);
 308                 return SR_OK;
 309         } else {
 310                 return sr_scpi_get_opc(sdi->conn);
 311         }
 312 }
 313
 314 /* Start capturing a new frameset */
 315 SR_PRIV int rigol_ds_capture_start(const struct sr_dev_inst *sdi)
 316 {
 317         struct dev_context *devc;
 318
 319         if (!(devc = sdi->priv))
 320                 return SR_ERR;
 321
 322         sr_dbg("Starting data capture for frameset %lu of %lu",
 323                devc->num_frames + 1, devc->limit_frames);
 324
 325         if (rigol_ds_config_set(sdi, ":WAV:FORM BYTE") != SR_OK)
 326                 return SR_ERR;
 327         if (devc->data_source == DATA_SOURCE_LIVE) {
 328                 if (rigol_ds_config_set(sdi, ":WAV:MODE NORM") != SR_OK)
 329                         return SR_ERR;
 330                 rigol_ds_set_wait_event(devc, WAIT_TRIGGER);
 331         } else {
 332                 if (rigol_ds_config_set(sdi, ":WAV:MODE RAW") != SR_OK)
 333                         return SR_ERR;
 334                 if (rigol_ds_config_set(sdi, ":SING", devc->analog_frame_size) != SR_OK)
 335                         return SR_ERR;
 336                 rigol_ds_set_wait_event(devc, WAIT_STOP);
 337         }
 338
 339         return SR_OK;
 340 }
 341
 342 /* Start reading data from the current channel */
 343 SR_PRIV int rigol_ds_channel_start(const struct sr_dev_inst *sdi)
 344 {
 345         struct dev_context *devc;
 346         struct sr_probe *probe;
 347
 348         if (!(devc = sdi->priv))
 349                 return SR_ERR;
 350
 351         probe = devc->channel_entry->data;
 352
 353         sr_dbg("Starting reading data from channel %d", probe->index + 1);
 354
 355         if (devc->model->series < RIGOL_DS1000Z) {
 356                 if (probe->type == SR_PROBE_LOGIC) {
 357                         if (sr_scpi_send(sdi->conn, ":WAV:DATA? DIG") != SR_OK)
 358                                 return SR_ERR;
 359                 } else {
 360                         if (sr_scpi_send(sdi->conn, ":WAV:DATA? CHAN%d",
 361                                         probe->index + 1) != SR_OK)
 362                                 return SR_ERR;
 363                 }
 364         } else {
 365                 if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d",
 366                                   probe->index + 1) != SR_OK)
 367                         return SR_ERR;
 368                 if (devc->data_source != DATA_SOURCE_LIVE) {
 369                         if (rigol_ds_config_set(sdi, ":WAV:RES") != SR_OK)
 370                                 return SR_ERR;
 371                         if (rigol_ds_config_set(sdi, ":WAV:BEG") != SR_OK)
 372                                 return SR_ERR;
 373                         rigol_ds_set_wait_event(devc, WAIT_BLOCK);
 374                 } else
 375                         rigol_ds_set_wait_event(devc, WAIT_NONE);
 376         }
 377
 378         devc->num_channel_bytes = 0;
 379         devc->num_block_bytes = 0;
 380
 381         return SR_OK;
 382 }
 383
 384 /* Read the header of a data block */
 385 static int rigol_ds_read_header(struct sr_scpi_dev_inst *scpi)
 386 {
 387         char start[3], length[10];
 388         int len, tmp;
 389
 390         /* Read the hashsign and length digit. */
 391         tmp = sr_scpi_read_data(scpi, start, 2);
 392         start[2] = '\0';
 393         if (tmp != 2) {
 394                 sr_err("Failed to read first two bytes of data block header.");
 395                 return -1;
 396         }
 397         if (start[0] != '#' || !isdigit(start[1]) || start[1] == '0') {
 398                 sr_err("Received invalid data block header start '%s'.", start);
 399                 return -1;
 400         }
 401         len = atoi(start + 1);
 402
 403         /* Read the data length. */
 404         tmp = sr_scpi_read_data(scpi, length, len);
 405         length[len] = '\0';
 406         if (tmp != len) {
 407                 sr_err("Failed to read %d bytes of data block length.", len);
 408                 return -1;
 409         }
 410         if (parse_int(length, &len) != SR_OK) {
 411                 sr_err("Received invalid data block length '%s'.", length);
 412                 return -1;
 413         }
 414
 415         sr_dbg("Received data block header: %s%s -> block length %d", start, length, len);
 416
 417         return len;
 418 }
 419
 420 SR_PRIV int rigol_ds_receive(int fd, int revents, void *cb_data)
 421 {
 422         struct sr_dev_inst *sdi;
 423         struct sr_scpi_dev_inst *scpi;
 424         struct dev_context *devc;
 425         struct sr_datafeed_packet packet;
 426         struct sr_datafeed_analog analog;
 427         struct sr_datafeed_logic logic;
 428         double vdiv, offset;
 429         int len, i, vref;
 430         struct sr_probe *probe;
 431         gsize expected_data_bytes;
 432
 433         (void)fd;
 434
 435         if (!(sdi = cb_data))
 436                 return TRUE;
 437
 438         if (!(devc = sdi->priv))
 439                 return TRUE;
 440
 441         scpi = sdi->conn;
 442
 443         if (revents == G_IO_IN || revents == 0) {
 444                 if (devc->model->series >= RIGOL_DS1000Z) {
 445                         switch(devc->wait_event) {
 446                         case WAIT_NONE:
 447                                 break;
 448                         case WAIT_TRIGGER:
 449                                 if (rigol_ds_trigger_wait(sdi) != SR_OK)
 450                                         return TRUE;
 451                                 if (rigol_ds_channel_start(sdi) != SR_OK)
 452                                         return TRUE;
 453                                 break;
 454                         case WAIT_BLOCK:
 455                                 if (rigol_ds_block_wait(sdi) != SR_OK)
 456                                         return TRUE;
 457                                 break;
 458                         case WAIT_STOP:
 459                                 if (rigol_ds_stop_wait(sdi) != SR_OK)
 460                                         return TRUE;
 461                                 if (rigol_ds_check_stop(sdi) != SR_OK)
 462                                         return TRUE;
 463                                 if (rigol_ds_channel_start(sdi) != SR_OK)
 464                                         return TRUE;
 465                                 return TRUE;
 466                         default:
 467                                 sr_err("BUG: Unknown event target encountered");
 468                         }
 469                 }
 470
 471                 probe = devc->channel_entry->data;
 472
 473                 expected_data_bytes = probe->type == SR_PROBE_ANALOG ?
 474                                 devc->analog_frame_size : devc->digital_frame_size;
 475
 476                 if (devc->num_block_bytes == 0 &&
 477                     devc->model->series >= RIGOL_DS1000Z) {
 478                                 if (sr_scpi_send(sdi->conn, ":WAV:DATA?") != SR_OK)
 479                                         return TRUE;
 480                 }
 481
 482                 if (devc->num_block_bytes == 0) {
 483
 484                         if (sr_scpi_read_begin(scpi) != SR_OK)
 485                                 return TRUE;
 486
 487                         if (devc->protocol == PROTOCOL_IEEE488_2) {
 488                                 sr_dbg("New block header expected");
 489                                 len = rigol_ds_read_header(scpi);
 490                                 if (len == -1)
 491                                         return TRUE;
 492                                 /* At slow timebases in live capture the DS2072
 493                                  * sometimes returns "short" data blocks, with
 494                                  * apparently no way to get the rest of the data.
 495                                  * Discard these, the complete data block will
 496                                  * appear eventually.
 497                                  */
 498                                 if (devc->data_source == DATA_SOURCE_LIVE
 499                                                 && (unsigned)len < expected_data_bytes) {
 500                                         sr_dbg("Discarding short data block");
 501                                         sr_scpi_read_data(scpi, (char *)devc->buffer, len + 1);
 502                                         return TRUE;
 503                                 }
 504                                 devc->num_block_bytes = len;
 505                         } else {
 506                                 devc->num_block_bytes = expected_data_bytes;
 507                         }
 508                         devc->num_block_read = 0;
 509                 }
 510
 511                 len = devc->num_block_bytes - devc->num_block_read;
 512                 len = sr_scpi_read_data(scpi, (char *)devc->buffer,
 513                                 len < ACQ_BUFFER_SIZE ? len : ACQ_BUFFER_SIZE);
 514
 515                 sr_dbg("Received %d bytes.", len);
 516                 if (len == -1)
 517                         return TRUE;
 518
 519                 devc->num_block_read += len;
 520
 521                 if (probe->type == SR_PROBE_ANALOG) {
 522                         vref = devc->vert_reference[probe->index];
 523                         vdiv = devc->vdiv[probe->index] / 25.6;
 524                         offset = devc->vert_offset[probe->index];
 525                         if (devc->model->series >= RIGOL_DS1000Z)
 526                                 for (i = 0; i < len; i++)
 527                                         devc->data[i] = ((int)devc->buffer[i] - vref) * vdiv - offset;
 528                         else
 529                                 for (i = 0; i < len; i++)
 530                                         devc->data[i] = (128 - devc->buffer[i]) * vdiv - offset;
 531                         analog.probes = g_slist_append(NULL, probe);
 532                         analog.num_samples = len;
 533                         analog.data = devc->data;
 534                         analog.mq = SR_MQ_VOLTAGE;
 535                         analog.unit = SR_UNIT_VOLT;
 536                         analog.mqflags = 0;
 537                         packet.type = SR_DF_ANALOG;
 538                         packet.payload = &analog;
 539                         sr_session_send(cb_data, &packet);
 540                         g_slist_free(analog.probes);
 541                 } else {
 542                         logic.length = len;
 543                         logic.unitsize = 2;
 544                         logic.data = devc->buffer;
 545                         packet.type = SR_DF_LOGIC;
 546                         packet.payload = &logic;
 547                         sr_session_send(cb_data, &packet);
 548                 }
 549
 550                 if (devc->num_block_read == devc->num_block_bytes) {
 551                         sr_dbg("Block has been completed");
 552                         if (devc->model->series >= RIGOL_DS1000Z) {
 553                                 /* Discard the terminating linefeed */
 554                                 sr_scpi_read_data(scpi, (char *)devc->buffer, 1);
 555                         }
 556                         if (devc->protocol == PROTOCOL_IEEE488_2) {
 557                                 /* Prepare for possible next block */
 558                                 devc->num_block_bytes = 0;
 559                                 if (devc->data_source != DATA_SOURCE_LIVE)
 560                                         rigol_ds_set_wait_event(devc, WAIT_BLOCK);
 561                         }
 562                         if (!sr_scpi_read_complete(scpi)) {
 563                                 sr_err("Read should have been completed");
 564                                 sdi->driver->dev_acquisition_stop(sdi, cb_data);
 565                                 return TRUE;
 566                         }
 567                         devc->num_block_read = 0;
 568                 } else {
 569                         sr_dbg("%d of %d block bytes read", devc->num_block_read, devc->num_block_bytes);
 570                 }
 571
 572                 devc->num_channel_bytes += len;
 573
 574                 if (devc->num_channel_bytes < expected_data_bytes)
 575                         /* Don't have the full data for this channel yet, re-run. */
 576                         return TRUE;
 577
 578                 /* End of data for this channel. */
 579                 if (devc->model->series >= RIGOL_DS1000Z) {
 580                         /* Signal end of data download to scope */
 581                         if (devc->data_source != DATA_SOURCE_LIVE)
 582                                 /*
 583                                  * This causes a query error, without it switching
 584                                  * to the next channel causes an error. Fun with
 585                                  * firmware...
 586                                  */
 587                                 rigol_ds_config_set(sdi, ":WAV:END");
 588                 }
 589
 590                 if (probe->type == SR_PROBE_ANALOG
 591                                 && devc->channel_entry->next != NULL) {
 592                         /* We got the frame for this analog channel, but
 593                          * there's another analog channel. */
 594                         devc->channel_entry = devc->channel_entry->next;
 595                         rigol_ds_channel_start(sdi);
 596                 } else {
 597                         /* Done with all analog channels in this frame. */
 598                         if (devc->enabled_digital_probes
 599                                         && devc->channel_entry != devc->enabled_digital_probes) {
 600                                 /* Now we need to get the digital data. */
 601                                 devc->channel_entry = devc->enabled_digital_probes;
 602                                 rigol_ds_channel_start(sdi);
 603                         } else {
 604                                 /* Done with this frame. */
 605                                 packet.type = SR_DF_FRAME_END;
 606                                 sr_session_send(cb_data, &packet);
 607
 608                                 if (++devc->num_frames == devc->limit_frames) {
 609                                         /* Last frame, stop capture. */
 610                                         sdi->driver->dev_acquisition_stop(sdi, cb_data);
 611                                 } else {
 612                                         /* Get the next frame, starting with the first analog channel. */
 613                                         if (devc->enabled_analog_probes)
 614                                                 devc->channel_entry = devc->enabled_analog_probes;
 615                                         else
 616                                                 devc->channel_entry = devc->enabled_digital_probes;
 617
 618                                         if (devc->model->series < RIGOL_DS1000Z)
 619                                                 rigol_ds_channel_start(sdi);
 620                                         else
 621                                                 rigol_ds_capture_start(sdi);
 622
 623                                         /* Start of next frame. */
 624                                         packet.type = SR_DF_FRAME_BEGIN;
 625                                         sr_session_send(cb_data, &packet);
 626                                 }
 627                         }
 628                 }
 629         }
 630
 631         return TRUE;
 632 }
 633
 634 SR_PRIV int rigol_ds_get_dev_cfg(const struct sr_dev_inst *sdi)
 635 {
 636         struct dev_context *devc;
 637         char *t_s, *cmd;
 638         unsigned int i;
 639         int res;
 640
 641         devc = sdi->priv;
 642
 643         /* Analog channel state. */
 644         for (i = 0; i < devc->model->analog_channels; i++) {
 645                 cmd = g_strdup_printf(":CHAN%d:DISP?", i + 1);
 646                 res = sr_scpi_get_string(sdi->conn, cmd, &t_s);
 647                 g_free(cmd);
 648                 if (res != SR_OK)
 649                         return SR_ERR;
 650                 devc->analog_channels[i] = !strcmp(t_s, "ON") || !strcmp(t_s, "1");
 651         }
 652         sr_dbg("Current analog channel state:");
 653         for (i = 0; i < devc->model->analog_channels; i++)
 654                 sr_dbg("CH%d %s", i + 1, devc->analog_channels[i] ? "on" : "off");
 655
 656         /* Digital channel state. */
 657         if (devc->model->has_digital) {
 658                 if (sr_scpi_get_string(sdi->conn, ":LA:DISP?", &t_s) != SR_OK)
 659                         return SR_ERR;
 660                 devc->la_enabled = !strcmp(t_s, "ON") ? TRUE : FALSE;
 661                 sr_dbg("Logic analyzer %s, current digital channel state:",
 662                                 devc->la_enabled ? "enabled" : "disabled");
 663                 for (i = 0; i < 16; i++) {
 664                         cmd = g_strdup_printf(":DIG%d:TURN?", i);
 665                         res = sr_scpi_get_string(sdi->conn, cmd, &t_s);
 666                         g_free(cmd);
 667                         if (res != SR_OK)
 668                                 return SR_ERR;
 669                         devc->digital_channels[i] = !strcmp(t_s, "ON") ? TRUE : FALSE;
 670                         g_free(t_s);
 671                         sr_dbg("D%d: %s", i, devc->digital_channels[i] ? "on" : "off");
 672                 }
 673         }
 674
 675         /* Timebase. */
 676         if (sr_scpi_get_float(sdi->conn, ":TIM:SCAL?", &devc->timebase) != SR_OK)
 677                 return SR_ERR;
 678         sr_dbg("Current timebase %g", devc->timebase);
 679
 680         /* Vertical gain. */
 681         for (i = 0; i < devc->model->analog_channels; i++) {
 682                 cmd = g_strdup_printf(":CHAN%d:SCAL?", i + 1);
 683                 res = sr_scpi_get_float(sdi->conn, cmd, &devc->vdiv[i]);
 684                 g_free(cmd);
 685                 if (res != SR_OK)
 686                         return SR_ERR;
 687         }
 688         sr_dbg("Current vertical gain:");
 689         for (i = 0; i < devc->model->analog_channels; i++)
 690                 sr_dbg("CH%d %g", i + 1, devc->vdiv[i]);
 691
 692         sr_dbg("Current vertical reference:");
 693         if (devc->model->series >= RIGOL_DS1000Z) {
 694                 /* Vertical reference - not certain if this is the place to read it. */
 695                 for (i = 0; i < devc->model->analog_channels; i++) {
 696                         if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d", i + 1) != SR_OK)
 697                                 return SR_ERR;
 698                         if (sr_scpi_get_int(sdi->conn, ":WAV:YREF?", &devc->vert_reference[i]) != SR_OK)
 699                                 return SR_ERR;
 700                         sr_dbg("CH%d %d", i + 1, devc->vert_reference[i]);
 701                 }
 702         }
 703
 704         /* Vertical offset. */
 705         for (i = 0; i < devc->model->analog_channels; i++) {
 706                 cmd = g_strdup_printf(":CHAN%d:OFFS?", i + 1);
 707                 res = sr_scpi_get_float(sdi->conn, cmd, &devc->vert_offset[i]);
 708                 g_free(cmd);
 709                 if (res != SR_OK)
 710                         return SR_ERR;
 711         }
 712         sr_dbg("Current vertical offset:");
 713         for (i = 0; i < devc->model->analog_channels; i++)
 714                 sr_dbg("CH%d %g", i + 1, devc->vert_offset[i]);
 715
 716         /* Coupling. */
 717         for (i = 0; i < devc->model->analog_channels; i++) {
 718                 cmd = g_strdup_printf(":CHAN%d:COUP?", i + 1);
 719                 res = sr_scpi_get_string(sdi->conn, cmd, &devc->coupling[i]);
 720                 g_free(cmd);
 721                 if (res != SR_OK)
 722                         return SR_ERR;
 723         }
 724         sr_dbg("Current coupling:");
 725         for (i = 0; i < devc->model->analog_channels; i++)
 726                 sr_dbg("CH%d %s", i + 1, devc->coupling[i]);
 727
 728         /* Trigger source. */
 729         if (sr_scpi_get_string(sdi->conn, ":TRIG:EDGE:SOUR?", &devc->trigger_source) != SR_OK)
 730                 return SR_ERR;
 731         sr_dbg("Current trigger source %s", devc->trigger_source);
 732
 733         /* Horizontal trigger position. */
 734         if (sr_scpi_get_float(sdi->conn, ":TIM:OFFS?", &devc->horiz_triggerpos) != SR_OK)
 735                 return SR_ERR;
 736         sr_dbg("Current horizontal trigger position %g", devc->horiz_triggerpos);
 737
 738         /* Trigger slope. */
 739         if (sr_scpi_get_string(sdi->conn, ":TRIG:EDGE:SLOP?", &devc->trigger_slope) != SR_OK)
 740                 return SR_ERR;
 741         sr_dbg("Current trigger slope %s", devc->trigger_slope);
 742
 743         return SR_OK;
 744 }