2 * This file is part of the sigrok project.
4 * Copyright (C) 2011 Daniel Ribeiro <drwyrm@gmail.com>
5 * Copyright (C) 2012 Renato Caldas <rmsc@fe.up.pt>
6 * Copyright (C) 2013 Lior Elazary <lelazary@yahoo.com>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #ifndef LIBSIGROK_HARDWARE_LINK_MSO19_PROTOCOL_H
23 #define LIBSIGROK_HARDWARE_LINK_MSO19_PROTOCOL_H
25 #define USB_VENDOR "3195"
26 #define USB_PRODUCT "f190"
31 #include "libsigrok.h"
32 #include "libsigrok-internal.h"
34 /* Message logging helpers with driver-specific prefix string. */
35 #define DRIVER_LOG_DOMAIN "mso19: "
36 #define sr_log(l, s, args...) sr_log(l, DRIVER_LOG_DOMAIN s, ## args)
37 #define sr_spew(s, args...) sr_spew(DRIVER_LOG_DOMAIN s, ## args)
38 #define sr_dbg(s, args...) sr_dbg(DRIVER_LOG_DOMAIN s, ## args)
39 #define sr_info(s, args...) sr_info(DRIVER_LOG_DOMAIN s, ## args)
40 #define sr_warn(s, args...) sr_warn(DRIVER_LOG_DOMAIN s, ## args)
41 #define sr_err(s, args...) sr_err(DRIVER_LOG_DOMAIN s, ## args)
44 #define NUM_TRIGGER_STAGES 4
45 #define TRIGGER_TYPES "01" //the first r/f is used for the whole group
46 #define SERIALCOMM "460800/8n1/flow=2"
47 #define SERIALCONN "/dev/ttyUSB0"
48 #define CLOCK_RATE SR_MHZ(100)
49 #define MIN_NUM_SAMPLES 4
51 #define MSO_TRIGGER_UNKNOWN '!'
52 #define MSO_TRIGGER_UNKNOWN1 '1'
53 #define MSO_TRIGGER_UNKNOWN2 '2'
54 #define MSO_TRIGGER_UNKNOWN3 '3'
55 #define MSO_TRIGGER_WAIT '4'
56 #define MSO_TRIGGER_FIRED '5'
57 #define MSO_TRIGGER_DATAREADY '6'
64 /* Structure for the pattern generator state */
66 /* Pattern generator clock config */
68 /* Buffer start address */
70 /* Buffer end address */
72 /* Pattern generator config */
76 /* Input/output configuration for the samples buffer (?)*/
78 /* Number of loops for the pattern generator */
80 /* Bit enable mask for the I/O lines */
84 /* Data structure for the protocol trigger state */
85 struct mso_prototrig {
86 /* Word match buffer */
88 /* Masks for the wordmatch buffer */
90 /* SPI mode 0, 1, 2, 3. Set to 0 for I2C */
94 /* Private, per-device-instance driver context. */
99 struct sr_serial_dev_inst *serial;
100 // uint8_t num_sample_rates;
104 uint16_t offset_range;
105 uint64_t limit_samples;
106 uint64_t num_samples;
111 uint8_t la_threshold;
113 uint8_t dso_probe_attn;
115 uint8_t trigger_chan;
116 uint8_t trigger_slope;
117 uint8_t trigger_outsrc;
118 uint8_t trigger_state;
119 uint8_t trigger_holdoff[2];
121 uint8_t la_trigger_mask;
122 double dso_trigger_voltage;
123 uint16_t dso_trigger_width;
124 struct mso_prototrig protocol_trigger;
125 void *session_dev_id;
130 SR_PRIV int mso_parse_serial(const char *iSerial, const char *iProduct,
131 struct dev_context *ctx);
132 SR_PRIV int mso_check_trigger(struct sr_serial_dev_inst *serial, uint8_t *info);
133 SR_PRIV int mso_reset_adc(struct sr_dev_inst *sdi);
134 SR_PRIV int mso_clkrate_out(struct sr_serial_dev_inst *serial, uint16_t val);
135 SR_PRIV int mso_configure_rate(struct sr_dev_inst *sdi, uint32_t rate);
136 SR_PRIV int mso_receive_data(int fd, int revents, void *cb_data);
137 SR_PRIV int mso_configure_trigger(struct sr_dev_inst *sdi);
138 SR_PRIV int mso_configure_threshold_level(struct sr_dev_inst *sdi);
139 SR_PRIV int mso_read_buffer(struct sr_dev_inst *sdi);
140 SR_PRIV int mso_arm(struct sr_dev_inst *sdi);
141 SR_PRIV int mso_force_capture(struct sr_dev_inst *sdi);
142 SR_PRIV int mso_dac_out(struct sr_dev_inst *sdi, uint16_t val);
143 SR_PRIV inline uint16_t mso_calc_raw_from_mv(struct dev_context *devc);
144 SR_PRIV int mso_reset_fsm(struct sr_dev_inst *sdi);
145 SR_PRIV int mso_toggle_led(struct sr_dev_inst *sdi, int state);
147 SR_PRIV int mso_configure_probes(const struct sr_dev_inst *sdi);
148 SR_PRIV void stop_acquisition(const struct sr_dev_inst *sdi);
150 ///////////////////////
153 /* serial protocol */
154 #define mso_trans(a, v) \
155 (((v) & 0x3f) | (((v) & 0xc0) << 6) | (((a) & 0xf) << 8) | \
156 ((~(v) & 0x20) << 1) | ((~(v) & 0x80) << 7))
158 SR_PRIV static const char mso_head[] = { 0x40, 0x4c, 0x44, 0x53, 0x7e };
159 SR_PRIV static const char mso_foot[] = { 0x7e };
161 /* bank agnostic registers */
164 /* bank 0 registers */
166 #define REG_TRIGGER 2
167 #define REG_CLKRATE1 9
168 #define REG_CLKRATE2 10
171 /* possibly bank agnostic: */
174 /* bank 2 registers (SPI/I2C protocol trigger) */
175 #define REG_PT_WORD(x) (x)
176 #define REG_PT_MASK(x) (x+4)
177 #define REG_PT_SPIMODE 8
179 /* bits - REG_CTL1 */
180 #define BIT_CTL1_RESETFSM (1 << 0)
181 #define BIT_CTL1_ARM (1 << 1)
182 #define BIT_CTL1_ADC_UNKNOWN4 (1 << 4) /* adc enable? */
183 #define BIT_CTL1_RESETADC (1 << 6)
184 #define BIT_CTL1_LED (1 << 7)
186 /* bits - REG_CTL2 */
187 #define BITS_CTL2_BANK(x) (x & 0x3)
188 #define BIT_CTL2_SLOWMODE (1 << 5)
196 static struct rate_map rate_map[] = {
197 { SR_MHZ(200), 0x0205, 0 },
198 { SR_MHZ(100), 0x0105, 0 },
199 { SR_MHZ(50), 0x0005, 0 },
200 { SR_MHZ(20), 0x0303, 0 },
201 { SR_MHZ(10), 0x0308, 0 },
202 { SR_MHZ(5), 0x030c, 0 },
203 { SR_MHZ(2), 0x0330, 0 },
204 { SR_MHZ(1), 0x0362, 0 },
205 { SR_KHZ(500), 0x03c6, 0 },
206 { SR_KHZ(200), 0x07f2, 0 },
207 { SR_KHZ(100), 0x0fe6, 0 },
208 { SR_KHZ(50), 0x1fce, 0 },
209 { SR_KHZ(20), 0x4f86, 0 },
210 { SR_KHZ(10), 0x9f0e, 0 },
211 { SR_KHZ(5), 0x03c7, 0x20 },
212 { SR_KHZ(2), 0x07f3, 0x20 },
213 { SR_KHZ(1), 0x0fe7, 0x20 },
214 { 500, 0x1fcf, 0x20 },
215 { 200, 0x4f87, 0x20 },
216 { 100, 0x9f0f, 0x20 },
219 /* FIXME: Determine corresponding voltages */
220 static uint16_t la_threshold_map[] = {