2 * This file is part of the sigrok project.
4 * Copyright (C) 2010-2012 Bert Vermeulen <bert@biot.com>
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #ifndef LIBSIGROK_HARDWARE_LINK_MSO19_PROTOCOL_H
21 #define LIBSIGROK_HARDWARE_LINK_MSO19_PROTOCOL_H
23 #define USB_VENDOR "3195"
24 #define USB_PRODUCT "f190"
29 #include "libsigrok.h"
30 #include "libsigrok-internal.h"
32 /* Message logging helpers with driver-specific prefix string. */
33 #define DRIVER_LOG_DOMAIN "mso19: "
34 #define sr_log(l, s, args...) sr_log(l, DRIVER_LOG_DOMAIN s, ## args)
35 #define sr_spew(s, args...) sr_spew(DRIVER_LOG_DOMAIN s, ## args)
36 #define sr_dbg(s, args...) sr_dbg(DRIVER_LOG_DOMAIN s, ## args)
37 #define sr_info(s, args...) sr_info(DRIVER_LOG_DOMAIN s, ## args)
38 #define sr_warn(s, args...) sr_warn(DRIVER_LOG_DOMAIN s, ## args)
39 #define sr_err(s, args...) sr_err(DRIVER_LOG_DOMAIN s, ## args)
42 #define NUM_TRIGGER_STAGES 4
43 #define TRIGGER_TYPES "01"
44 #define SERIAL_SPEED B115200
45 #define CLOCK_RATE SR_MHZ(100)
46 #define MIN_NUM_SAMPLES 4
49 ///* Bitmasks for CMD_FLAGS */
50 //#define FLAG_DEMUX 0x01
51 //#define FLAG_FILTER 0x02
52 //#define FLAG_CHANNELGROUP_1 0x04
53 //#define FLAG_CHANNELGROUP_2 0x08
54 //#define FLAG_CHANNELGROUP_3 0x10
55 //#define FLAG_CHANNELGROUP_4 0x20
56 //#define FLAG_CLOCK_EXTERNAL 0x40
57 //#define FLAG_CLOCK_INVERTED 0x80
58 //#define FLAG_RLE 0x0100
60 #define MSO_TRIGGER_UNKNOWN '!'
61 #define MSO_TRIGGER_UNKNOWN1 '1'
62 #define MSO_TRIGGER_UNKNOWN2 '2'
63 #define MSO_TRIGGER_UNKNOWN3 '3'
64 #define MSO_TRIGGER_WAIT '4'
65 #define MSO_TRIGGER_FIRED '5'
66 #define MSO_TRIGGER_DATAREADY '6'
68 /* Structure for the pattern generator state */
70 /* Pattern generator clock config */
72 /* Buffer start address */
74 /* Buffer end address */
76 /* Pattern generator config */
80 /* Input/output configuration for the samples buffer (?)*/
82 /* Number of loops for the pattern generator */
84 /* Bit enable mask for the I/O lines */
88 /* Data structure for the protocol trigger state */
89 struct mso_prototrig {
90 /* Word match buffer */
92 /* Masks for the wordmatch buffer */
94 /* SPI mode 0, 1, 2, 3. Set to 0 for I2C */
98 /* Private, per-device-instance driver context. */
103 struct sr_serial_dev_inst *serial;
104 // uint8_t num_sample_rates;
108 uint16_t offset_range;
113 uint8_t la_threshold;
115 uint8_t dso_probe_attn;
116 uint8_t trigger_chan;
117 uint8_t trigger_slope;
118 uint8_t trigger_outsrc;
119 uint8_t trigger_state;
121 uint8_t la_trigger_mask;
122 double dso_trigger_voltage;
123 uint16_t dso_trigger_width;
124 struct mso_prototrig protocol_trigger;
125 void *session_dev_id;
130 SR_PRIV int mso_parse_serial(const char *iSerial, const char *iProduct,
131 struct dev_context *ctx);
132 SR_PRIV int mso_check_trigger(struct sr_serial_dev_inst *serial, uint8_t *info);
133 SR_PRIV int mso_reset_adc(struct sr_dev_inst *sdi);
134 SR_PRIV int mso_clkrate_out(struct sr_serial_dev_inst *serial, uint16_t val);
135 SR_PRIV int mso_configure_rate(struct sr_dev_inst *sdi, uint32_t rate);
136 SR_PRIV int mso_receive_data(int fd, int revents, void *cb_data);
137 SR_PRIV void stop_acquisition(const struct sr_dev_inst *sdi);
139 ///////////////////////
142 /* serial protocol */
143 #define mso_trans(a, v) \
144 (((v) & 0x3f) | (((v) & 0xc0) << 6) | (((a) & 0xf) << 8) | \
145 ((~(v) & 0x20) << 1) | ((~(v) & 0x80) << 7))
147 SR_PRIV static const char mso_head[] = { 0x40, 0x4c, 0x44, 0x53, 0x7e };
148 SR_PRIV static const char mso_foot[] = { 0x7e };
150 /* bank agnostic registers */
153 /* bank 0 registers */
155 #define REG_TRIGGER 2
156 #define REG_CLKRATE1 9
157 #define REG_CLKRATE2 10
160 /* possibly bank agnostic: */
163 /* bank 2 registers (SPI/I2C protocol trigger) */
164 #define REG_PT_WORD(x) (x)
165 #define REG_PT_MASK(x) (x+4)
166 #define REG_PT_SPIMODE 8
168 /* bits - REG_CTL1 */
169 #define BIT_CTL1_RESETFSM (1 << 0)
170 #define BIT_CTL1_ARM (1 << 1)
171 #define BIT_CTL1_ADC_UNKNOWN4 (1 << 4) /* adc enable? */
172 #define BIT_CTL1_RESETADC (1 << 6)
173 #define BIT_CTL1_LED (1 << 7)
175 /* bits - REG_CTL2 */
176 #define BITS_CTL2_BANK(x) (x & 0x3)
177 #define BIT_CTL2_SLOWMODE (1 << 5)
185 static struct rate_map rate_map[] = {
186 { SR_MHZ(200), 0x0205, 0 },
187 { SR_MHZ(100), 0x0105, 0 },
188 { SR_MHZ(50), 0x0005, 0 },
189 { SR_MHZ(20), 0x0303, 0 },
190 { SR_MHZ(10), 0x0308, 0 },
191 { SR_MHZ(5), 0x030c, 0 },
192 { SR_MHZ(2), 0x0330, 0 },
193 { SR_MHZ(1), 0x0362, 0 },
194 { SR_KHZ(500), 0x03c6, 0 },
195 { SR_KHZ(200), 0x07f2, 0 },
196 { SR_KHZ(100), 0x0fe6, 0 },
197 { SR_KHZ(50), 0x1fce, 0 },
198 { SR_KHZ(20), 0x4f86, 0 },
199 { SR_KHZ(10), 0x9f0e, 0 },
200 { SR_KHZ(5), 0x03c7, 0x20 },
201 { SR_KHZ(2), 0x07f3, 0x20 },
202 { SR_KHZ(1), 0x0fe7, 0x20 },
203 { 500, 0x1fcf, 0x20 },
204 { 200, 0x4f87, 0x20 },
205 { 100, 0x9f0f, 0x20 },
208 /* FIXME: Determine corresponding voltages */
209 static uint16_t la_threshold_map[] = {
219 //SR_PRIV extern const char *ols_probe_names[NUM_PROBES + 1];
221 //SR_PRIV int send_shortcommand(struct sr_serial_dev_inst *serial,
223 //SR_PRIV int send_longcommand(struct sr_serial_dev_inst *serial,
224 // uint8_t command, uint32_t data);
225 //SR_PRIV int ols_configure_probes(const struct sr_dev_inst *sdi);
226 //SR_PRIV uint32_t reverse16(uint32_t in);
227 //SR_PRIV uint32_t reverse32(uint32_t in);
228 //SR_PRIV struct dev_context *ols_dev_new(void);
229 //SR_PRIV struct sr_dev_inst *get_metadata(struct sr_serial_dev_inst *serial);
230 //SR_PRIV int ols_set_samplerate(const struct sr_dev_inst *sdi,
231 // uint64_t samplerate,
232 // const struct sr_samplerates *samplerates);
233 //SR_PRIV int ols_receive_data(int fd, int revents, void *cb_data);