2 * This file is part of the sigrok project.
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
27 #include <glib/gstdio.h>
30 #include "libsigrok.h"
31 #include "libsigrok-internal.h"
32 #include "asix-sigma.h"
34 #define USB_VENDOR 0xa600
35 #define USB_PRODUCT 0xa000
36 #define USB_DESCRIPTION "ASIX SIGMA"
37 #define USB_VENDOR_NAME "ASIX"
38 #define USB_MODEL_NAME "SIGMA"
39 #define USB_MODEL_VERSION ""
40 #define TRIGGER_TYPES "rf10"
43 SR_PRIV struct sr_dev_driver asix_sigma_driver_info;
44 static struct sr_dev_driver *adi = &asix_sigma_driver_info;
46 static const uint64_t supported_samplerates[] = {
61 * Probe numbers seem to go from 1-16, according to this image:
62 * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
63 * (the cable has two additional GND pins, and a TI and TO pin)
65 static const char *probe_names[NUM_PROBES + 1] = {
85 static const struct sr_samplerates samplerates = {
89 supported_samplerates,
92 static const int hwcaps[] = {
93 SR_HWCAP_LOGIC_ANALYZER,
95 SR_HWCAP_CAPTURE_RATIO,
102 /* Force the FPGA to reboot. */
103 static uint8_t suicide[] = {
104 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
107 /* Prepare to upload firmware (FPGA specific). */
108 static uint8_t init[] = {
109 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
112 /* Initialize the logic analyzer mode. */
113 static uint8_t logic_mode_start[] = {
114 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
115 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
118 static const char *firmware_files[] = {
119 "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */
120 "asix-sigma-100.fw", /* 100 MHz */
121 "asix-sigma-200.fw", /* 200 MHz */
122 "asix-sigma-50sync.fw", /* Synchronous clock from pin */
123 "asix-sigma-phasor.fw", /* Frequency counter */
126 static int hw_dev_acquisition_stop(int dev_index, void *cb_data);
128 static int sigma_read(void *buf, size_t size, struct context *ctx)
132 ret = ftdi_read_data(&ctx->ftdic, (unsigned char *)buf, size);
134 sr_err("sigma: ftdi_read_data failed: %s",
135 ftdi_get_error_string(&ctx->ftdic));
141 static int sigma_write(void *buf, size_t size, struct context *ctx)
145 ret = ftdi_write_data(&ctx->ftdic, (unsigned char *)buf, size);
147 sr_err("sigma: ftdi_write_data failed: %s",
148 ftdi_get_error_string(&ctx->ftdic));
149 } else if ((size_t) ret != size) {
150 sr_err("sigma: ftdi_write_data did not complete write.");
156 static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
160 uint8_t buf[len + 2];
163 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
164 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
166 for (i = 0; i < len; ++i) {
167 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
168 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
171 return sigma_write(buf, idx, ctx);
174 static int sigma_set_register(uint8_t reg, uint8_t value, struct context *ctx)
176 return sigma_write_register(reg, &value, 1, ctx);
179 static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
184 buf[0] = REG_ADDR_LOW | (reg & 0xf);
185 buf[1] = REG_ADDR_HIGH | (reg >> 4);
186 buf[2] = REG_READ_ADDR;
188 sigma_write(buf, sizeof(buf), ctx);
190 return sigma_read(data, len, ctx);
193 static uint8_t sigma_get_register(uint8_t reg, struct context *ctx)
197 if (1 != sigma_read_register(reg, &value, 1, ctx)) {
198 sr_err("sigma: sigma_get_register: 1 byte expected");
205 static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
209 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
211 REG_READ_ADDR | NEXT_REG,
212 REG_READ_ADDR | NEXT_REG,
213 REG_READ_ADDR | NEXT_REG,
214 REG_READ_ADDR | NEXT_REG,
215 REG_READ_ADDR | NEXT_REG,
216 REG_READ_ADDR | NEXT_REG,
220 sigma_write(buf, sizeof(buf), ctx);
222 sigma_read(result, sizeof(result), ctx);
224 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
225 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
227 /* Not really sure why this must be done, but according to spec. */
228 if ((--*stoppos & 0x1ff) == 0x1ff)
231 if ((*--triggerpos & 0x1ff) == 0x1ff)
237 static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
238 uint8_t *data, struct context *ctx)
244 /* Send the startchunk. Index start with 1. */
245 buf[0] = startchunk >> 8;
246 buf[1] = startchunk & 0xff;
247 sigma_write_register(WRITE_MEMROW, buf, 2, ctx);
250 buf[idx++] = REG_DRAM_BLOCK;
251 buf[idx++] = REG_DRAM_WAIT_ACK;
253 for (i = 0; i < numchunks; ++i) {
254 /* Alternate bit to copy from DRAM to cache. */
255 if (i != (numchunks - 1))
256 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
258 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
260 if (i != (numchunks - 1))
261 buf[idx++] = REG_DRAM_WAIT_ACK;
264 sigma_write(buf, idx, ctx);
266 return sigma_read(data, numchunks * CHUNK_SIZE, ctx);
269 /* Upload trigger look-up tables to Sigma. */
270 static int sigma_write_trigger_lut(struct triggerlut *lut, struct context *ctx)
276 /* Transpose the table and send to Sigma. */
277 for (i = 0; i < 16; ++i) {
282 if (lut->m2d[0] & bit)
284 if (lut->m2d[1] & bit)
286 if (lut->m2d[2] & bit)
288 if (lut->m2d[3] & bit)
298 if (lut->m0d[0] & bit)
300 if (lut->m0d[1] & bit)
302 if (lut->m0d[2] & bit)
304 if (lut->m0d[3] & bit)
307 if (lut->m1d[0] & bit)
309 if (lut->m1d[1] & bit)
311 if (lut->m1d[2] & bit)
313 if (lut->m1d[3] & bit)
316 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
318 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, ctx);
321 /* Send the parameters */
322 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
323 sizeof(lut->params), ctx);
328 /* Generate the bitbang stream for programming the FPGA. */
329 static int bin2bitbang(const char *filename,
330 unsigned char **buf, size_t *buf_size)
333 unsigned long file_size;
334 unsigned long offset = 0;
337 unsigned long fwsize = 0;
338 const int buffer_size = 65536;
341 uint32_t imm = 0x3f6df2ab;
343 f = g_fopen(filename, "rb");
345 sr_err("sigma: g_fopen(\"%s\", \"rb\")", filename);
349 if (-1 == fseek(f, 0, SEEK_END)) {
350 sr_err("sigma: fseek on %s failed", filename);
355 file_size = ftell(f);
357 fseek(f, 0, SEEK_SET);
359 if (!(firmware = g_try_malloc(buffer_size))) {
360 sr_err("sigma: %s: firmware malloc failed", __func__);
362 return SR_ERR_MALLOC;
365 while ((c = getc(f)) != EOF) {
366 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
367 firmware[fwsize++] = c ^ imm;
371 if(fwsize != file_size) {
372 sr_err("sigma: %s: Error reading firmware", filename);
378 *buf_size = fwsize * 2 * 8;
380 *buf = p = (unsigned char *)g_try_malloc(*buf_size);
382 sr_err("sigma: %s: buf/p malloc failed", __func__);
384 return SR_ERR_MALLOC;
387 for (i = 0; i < fwsize; ++i) {
388 for (bit = 7; bit >= 0; --bit) {
389 v = firmware[i] & 1 << bit ? 0x40 : 0x00;
390 p[offset++] = v | 0x01;
397 if (offset != *buf_size) {
399 sr_err("sigma: Error reading firmware %s "
400 "offset=%ld, file_size=%ld, buf_size=%zd.",
401 filename, offset, file_size, *buf_size);
409 static void clear_instances(void)
412 struct sr_dev_inst *sdi;
415 /* Properly close all devices. */
416 for (l = adi->instances; l; l = l->next) {
417 if (!(sdi = l->data)) {
418 /* Log error, but continue cleaning up the rest. */
419 sr_err("sigma: %s: sdi was NULL, continuing", __func__);
424 ftdi_free(&ctx->ftdic);
427 sr_dev_inst_free(sdi);
429 g_slist_free(adi->instances);
430 adi->instances = NULL;
434 static int hw_init(void)
442 static GSList *hw_scan(GSList *options)
444 struct sr_dev_inst *sdi;
447 struct ftdi_device_list *devlist;
456 if (!(ctx = g_try_malloc(sizeof(struct context)))) {
457 sr_err("sigma: %s: ctx malloc failed", __func__);
461 ftdi_init(&ctx->ftdic);
463 /* Look for SIGMAs. */
465 if ((ret = ftdi_usb_find_all(&ctx->ftdic, &devlist,
466 USB_VENDOR, USB_PRODUCT)) <= 0) {
468 sr_err("ftdi_usb_find_all(): %d", ret);
472 /* Make sure it's a version 1 or 2 SIGMA. */
473 ftdi_usb_get_strings(&ctx->ftdic, devlist->dev, NULL, 0, NULL, 0,
474 serial_txt, sizeof(serial_txt));
475 sscanf(serial_txt, "%x", &serial);
477 if (serial < 0xa6010000 || serial > 0xa602ffff) {
478 sr_err("sigma: Only SIGMA and SIGMA2 are supported "
479 "in this version of sigrok.");
483 sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
485 ctx->cur_samplerate = 0;
488 ctx->cur_firmware = -1;
490 ctx->samples_per_event = 0;
491 ctx->capture_ratio = 50;
492 ctx->use_triggers = 0;
494 /* Register SIGMA device. */
495 if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME,
496 USB_MODEL_NAME, USB_MODEL_VERSION))) {
497 sr_err("sigma: %s: sdi was NULL", __func__);
500 devices = g_slist_append(devices, sdi);
501 adi->instances = g_slist_append(adi->instances, sdi);
504 /* We will open the device again when we need it. */
505 ftdi_list_free(&devlist);
510 ftdi_deinit(&ctx->ftdic);
515 static int upload_firmware(int firmware_idx, struct context *ctx)
521 unsigned char result[32];
522 char firmware_path[128];
524 /* Make sure it's an ASIX SIGMA. */
525 if ((ret = ftdi_usb_open_desc(&ctx->ftdic,
526 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
527 sr_err("sigma: ftdi_usb_open failed: %s",
528 ftdi_get_error_string(&ctx->ftdic));
532 if ((ret = ftdi_set_bitmode(&ctx->ftdic, 0xdf, BITMODE_BITBANG)) < 0) {
533 sr_err("sigma: ftdi_set_bitmode failed: %s",
534 ftdi_get_error_string(&ctx->ftdic));
538 /* Four times the speed of sigmalogan - Works well. */
539 if ((ret = ftdi_set_baudrate(&ctx->ftdic, 750000)) < 0) {
540 sr_err("sigma: ftdi_set_baudrate failed: %s",
541 ftdi_get_error_string(&ctx->ftdic));
545 /* Force the FPGA to reboot. */
546 sigma_write(suicide, sizeof(suicide), ctx);
547 sigma_write(suicide, sizeof(suicide), ctx);
548 sigma_write(suicide, sizeof(suicide), ctx);
549 sigma_write(suicide, sizeof(suicide), ctx);
551 /* Prepare to upload firmware (FPGA specific). */
552 sigma_write(init, sizeof(init), ctx);
554 ftdi_usb_purge_buffers(&ctx->ftdic);
556 /* Wait until the FPGA asserts INIT_B. */
558 ret = sigma_read(result, 1, ctx);
559 if (result[0] & 0x20)
563 /* Prepare firmware. */
564 snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR,
565 firmware_files[firmware_idx]);
567 if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) {
568 sr_err("sigma: An error occured while reading the firmware: %s",
573 /* Upload firmare. */
574 sr_info("sigma: Uploading firmware %s", firmware_files[firmware_idx]);
575 sigma_write(buf, buf_size, ctx);
579 if ((ret = ftdi_set_bitmode(&ctx->ftdic, 0x00, BITMODE_RESET)) < 0) {
580 sr_err("sigma: ftdi_set_bitmode failed: %s",
581 ftdi_get_error_string(&ctx->ftdic));
585 ftdi_usb_purge_buffers(&ctx->ftdic);
587 /* Discard garbage. */
588 while (1 == sigma_read(&pins, 1, ctx))
591 /* Initialize the logic analyzer mode. */
592 sigma_write(logic_mode_start, sizeof(logic_mode_start), ctx);
594 /* Expect a 3 byte reply. */
595 ret = sigma_read(result, 3, ctx);
597 result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
598 sr_err("sigma: Configuration failed. Invalid reply received.");
602 ctx->cur_firmware = firmware_idx;
604 sr_info("sigma: Firmware uploaded");
609 static int hw_dev_open(int dev_index)
611 struct sr_dev_inst *sdi;
615 if (!(sdi = sr_dev_inst_get(adi->instances, dev_index)))
620 /* Make sure it's an ASIX SIGMA. */
621 if ((ret = ftdi_usb_open_desc(&ctx->ftdic,
622 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
624 sr_err("sigma: ftdi_usb_open failed: %s",
625 ftdi_get_error_string(&ctx->ftdic));
630 sdi->status = SR_ST_ACTIVE;
635 static int set_samplerate(struct sr_dev_inst *sdi, uint64_t samplerate)
638 struct context *ctx = sdi->priv;
640 for (i = 0; supported_samplerates[i]; i++) {
641 if (supported_samplerates[i] == samplerate)
644 if (supported_samplerates[i] == 0)
645 return SR_ERR_SAMPLERATE;
647 if (samplerate <= SR_MHZ(50)) {
648 ret = upload_firmware(0, ctx);
649 ctx->num_probes = 16;
651 if (samplerate == SR_MHZ(100)) {
652 ret = upload_firmware(1, ctx);
655 else if (samplerate == SR_MHZ(200)) {
656 ret = upload_firmware(2, ctx);
660 ctx->cur_samplerate = samplerate;
661 ctx->period_ps = 1000000000000 / samplerate;
662 ctx->samples_per_event = 16 / ctx->num_probes;
663 ctx->state.state = SIGMA_IDLE;
669 * In 100 and 200 MHz mode, only a single pin rising/falling can be
670 * set as trigger. In other modes, two rising/falling triggers can be set,
671 * in addition to value/mask trigger for any number of probes.
673 * The Sigma supports complex triggers using boolean expressions, but this
674 * has not been implemented yet.
676 static int configure_probes(struct sr_dev_inst *sdi, const GSList *probes)
678 struct context *ctx = sdi->priv;
679 const struct sr_probe *probe;
684 memset(&ctx->trigger, 0, sizeof(struct sigma_trigger));
686 for (l = probes; l; l = l->next) {
687 probe = (struct sr_probe *)l->data;
688 probebit = 1 << (probe->index - 1);
690 if (!probe->enabled || !probe->trigger)
693 if (ctx->cur_samplerate >= SR_MHZ(100)) {
694 /* Fast trigger support. */
696 sr_err("sigma: ASIX SIGMA only supports a single "
697 "pin trigger in 100 and 200MHz mode.");
700 if (probe->trigger[0] == 'f')
701 ctx->trigger.fallingmask |= probebit;
702 else if (probe->trigger[0] == 'r')
703 ctx->trigger.risingmask |= probebit;
705 sr_err("sigma: ASIX SIGMA only supports "
706 "rising/falling trigger in 100 "
713 /* Simple trigger support (event). */
714 if (probe->trigger[0] == '1') {
715 ctx->trigger.simplevalue |= probebit;
716 ctx->trigger.simplemask |= probebit;
718 else if (probe->trigger[0] == '0') {
719 ctx->trigger.simplevalue &= ~probebit;
720 ctx->trigger.simplemask |= probebit;
722 else if (probe->trigger[0] == 'f') {
723 ctx->trigger.fallingmask |= probebit;
726 else if (probe->trigger[0] == 'r') {
727 ctx->trigger.risingmask |= probebit;
732 * Actually, Sigma supports 2 rising/falling triggers,
733 * but they are ORed and the current trigger syntax
734 * does not permit ORed triggers.
736 if (trigger_set > 1) {
737 sr_err("sigma: ASIX SIGMA only supports 1 "
738 "rising/falling triggers.");
744 ctx->use_triggers = 1;
750 static int hw_dev_close(int dev_index)
752 struct sr_dev_inst *sdi;
755 if (!(sdi = sr_dev_inst_get(adi->instances, dev_index))) {
756 sr_err("sigma: %s: sdi was NULL", __func__);
760 if (!(ctx = sdi->priv)) {
761 sr_err("sigma: %s: sdi->priv was NULL", __func__);
766 if (sdi->status == SR_ST_ACTIVE)
767 ftdi_usb_close(&ctx->ftdic);
769 sdi->status = SR_ST_INACTIVE;
774 static int hw_cleanup(void)
782 static const void *hw_dev_info_get(int dev_index, int dev_info_id)
784 struct sr_dev_inst *sdi;
786 const void *info = NULL;
788 if (!(sdi = sr_dev_inst_get(adi->instances, dev_index))) {
789 sr_err("sigma: %s: sdi was NULL", __func__);
795 switch (dev_info_id) {
799 case SR_DI_NUM_PROBES:
800 info = GINT_TO_POINTER(NUM_PROBES);
802 case SR_DI_PROBE_NAMES:
805 case SR_DI_SAMPLERATES:
808 case SR_DI_TRIGGER_TYPES:
809 info = (char *)TRIGGER_TYPES;
811 case SR_DI_CUR_SAMPLERATE:
812 info = &ctx->cur_samplerate;
819 static int hw_dev_status_get(int dev_index)
821 struct sr_dev_inst *sdi;
823 sdi = sr_dev_inst_get(adi->instances, dev_index);
827 return SR_ST_NOT_FOUND;
830 static const int *hw_hwcap_get_all(void)
835 static int hw_dev_config_set(int dev_index, int hwcap, const void *value)
837 struct sr_dev_inst *sdi;
841 if (!(sdi = sr_dev_inst_get(adi->instances, dev_index)))
846 if (hwcap == SR_HWCAP_SAMPLERATE) {
847 ret = set_samplerate(sdi, *(const uint64_t *)value);
848 } else if (hwcap == SR_HWCAP_PROBECONFIG) {
849 ret = configure_probes(sdi, value);
850 } else if (hwcap == SR_HWCAP_LIMIT_MSEC) {
851 ctx->limit_msec = *(const uint64_t *)value;
852 if (ctx->limit_msec > 0)
856 } else if (hwcap == SR_HWCAP_CAPTURE_RATIO) {
857 ctx->capture_ratio = *(const uint64_t *)value;
858 if (ctx->capture_ratio < 0 || ctx->capture_ratio > 100)
869 /* Software trigger to determine exact trigger position. */
870 static int get_trigger_offset(uint16_t *samples, uint16_t last_sample,
871 struct sigma_trigger *t)
875 for (i = 0; i < 8; ++i) {
877 last_sample = samples[i-1];
879 /* Simple triggers. */
880 if ((samples[i] & t->simplemask) != t->simplevalue)
884 if ((last_sample & t->risingmask) != 0 || (samples[i] &
885 t->risingmask) != t->risingmask)
889 if ((last_sample & t->fallingmask) != t->fallingmask ||
890 (samples[i] & t->fallingmask) != 0)
896 /* If we did not match, return original trigger pos. */
901 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
902 * Each event is 20ns apart, and can contain multiple samples.
904 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
905 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
906 * For 50 MHz and below, events contain one sample for each channel,
907 * spread 20 ns apart.
909 static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
910 uint16_t *lastsample, int triggerpos,
911 uint16_t limit_chunk, void *cb_data)
913 struct sr_dev_inst *sdi = cb_data;
914 struct context *ctx = sdi->priv;
916 uint16_t samples[65536 * ctx->samples_per_event];
917 struct sr_datafeed_packet packet;
918 struct sr_datafeed_logic logic;
919 int i, j, k, l, numpad, tosend;
920 size_t n = 0, sent = 0;
921 int clustersize = EVENTS_PER_CLUSTER * ctx->samples_per_event;
926 /* Check if trigger is in this chunk. */
927 if (triggerpos != -1) {
928 if (ctx->cur_samplerate <= SR_MHZ(50))
929 triggerpos -= EVENTS_PER_CLUSTER - 1;
934 /* Find in which cluster the trigger occured. */
935 triggerts = triggerpos / 7;
939 for (i = 0; i < 64; ++i) {
940 ts = *(uint16_t *) &buf[i * 16];
941 tsdiff = ts - *lastts;
944 /* Decode partial chunk. */
945 if (limit_chunk && ts > limit_chunk)
948 /* Pad last sample up to current point. */
949 numpad = tsdiff * ctx->samples_per_event - clustersize;
951 for (j = 0; j < numpad; ++j)
952 samples[j] = *lastsample;
957 /* Send samples between previous and this timestamp to sigrok. */
960 tosend = MIN(2048, n - sent);
962 packet.type = SR_DF_LOGIC;
963 packet.payload = &logic;
964 logic.length = tosend * sizeof(uint16_t);
966 logic.data = samples + sent;
967 sr_session_send(ctx->session_dev_id, &packet);
973 event = (uint16_t *) &buf[i * 16 + 2];
976 /* For each event in cluster. */
977 for (j = 0; j < 7; ++j) {
979 /* For each sample in event. */
980 for (k = 0; k < ctx->samples_per_event; ++k) {
983 /* For each probe. */
984 for (l = 0; l < ctx->num_probes; ++l)
985 cur_sample |= (!!(event[j] & (1 << (l *
986 ctx->samples_per_event + k)))) << l;
988 samples[n++] = cur_sample;
992 /* Send data up to trigger point (if triggered). */
994 if (i == triggerts) {
996 * Trigger is not always accurate to sample because of
997 * pipeline delay. However, it always triggers before
998 * the actual event. We therefore look at the next
999 * samples to pinpoint the exact position of the trigger.
1001 tosend = get_trigger_offset(samples, *lastsample,
1005 packet.type = SR_DF_LOGIC;
1006 packet.payload = &logic;
1007 logic.length = tosend * sizeof(uint16_t);
1009 logic.data = samples;
1010 sr_session_send(ctx->session_dev_id, &packet);
1015 /* Only send trigger if explicitly enabled. */
1016 if (ctx->use_triggers) {
1017 packet.type = SR_DF_TRIGGER;
1018 sr_session_send(ctx->session_dev_id, &packet);
1022 /* Send rest of the chunk to sigrok. */
1026 packet.type = SR_DF_LOGIC;
1027 packet.payload = &logic;
1028 logic.length = tosend * sizeof(uint16_t);
1030 logic.data = samples + sent;
1031 sr_session_send(ctx->session_dev_id, &packet);
1034 *lastsample = samples[n - 1];
1040 static int receive_data(int fd, int revents, void *cb_data)
1042 struct sr_dev_inst *sdi = cb_data;
1043 struct context *ctx = sdi->priv;
1044 struct sr_datafeed_packet packet;
1045 const int chunks_per_read = 32;
1046 unsigned char buf[chunks_per_read * CHUNK_SIZE];
1047 int bufsz, numchunks, i, newchunks;
1048 uint64_t running_msec;
1051 /* Avoid compiler warnings. */
1055 /* Get the current position. */
1056 sigma_read_pos(&ctx->state.stoppos, &ctx->state.triggerpos, ctx);
1058 numchunks = (ctx->state.stoppos + 511) / 512;
1060 if (ctx->state.state == SIGMA_IDLE)
1063 if (ctx->state.state == SIGMA_CAPTURE) {
1064 /* Check if the timer has expired, or memory is full. */
1065 gettimeofday(&tv, 0);
1066 running_msec = (tv.tv_sec - ctx->start_tv.tv_sec) * 1000 +
1067 (tv.tv_usec - ctx->start_tv.tv_usec) / 1000;
1069 if (running_msec < ctx->limit_msec && numchunks < 32767)
1070 return TRUE; /* While capturing... */
1072 hw_dev_acquisition_stop(sdi->index, sdi);
1074 } else if (ctx->state.state == SIGMA_DOWNLOAD) {
1075 if (ctx->state.chunks_downloaded >= numchunks) {
1076 /* End of samples. */
1077 packet.type = SR_DF_END;
1078 sr_session_send(ctx->session_dev_id, &packet);
1080 ctx->state.state = SIGMA_IDLE;
1085 newchunks = MIN(chunks_per_read,
1086 numchunks - ctx->state.chunks_downloaded);
1088 sr_info("sigma: Downloading sample data: %.0f %%",
1089 100.0 * ctx->state.chunks_downloaded / numchunks);
1091 bufsz = sigma_read_dram(ctx->state.chunks_downloaded,
1092 newchunks, buf, ctx);
1093 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1096 /* Find first ts. */
1097 if (ctx->state.chunks_downloaded == 0) {
1098 ctx->state.lastts = *(uint16_t *) buf - 1;
1099 ctx->state.lastsample = 0;
1102 /* Decode chunks and send them to sigrok. */
1103 for (i = 0; i < newchunks; ++i) {
1104 int limit_chunk = 0;
1106 /* The last chunk may potentially be only in part. */
1107 if (ctx->state.chunks_downloaded == numchunks - 1) {
1108 /* Find the last valid timestamp */
1109 limit_chunk = ctx->state.stoppos % 512 + ctx->state.lastts;
1112 if (ctx->state.chunks_downloaded + i == ctx->state.triggerchunk)
1113 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1115 &ctx->state.lastsample,
1116 ctx->state.triggerpos & 0x1ff,
1119 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1121 &ctx->state.lastsample,
1122 -1, limit_chunk, sdi);
1124 ++ctx->state.chunks_downloaded;
1131 /* Build a LUT entry used by the trigger functions. */
1132 static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1136 /* For each quad probe. */
1137 for (i = 0; i < 4; ++i) {
1140 /* For each bit in LUT. */
1141 for (j = 0; j < 16; ++j)
1143 /* For each probe in quad. */
1144 for (k = 0; k < 4; ++k) {
1145 bit = 1 << (i * 4 + k);
1147 /* Set bit in entry */
1149 ((!(value & bit)) !=
1151 entry[i] &= ~(1 << j);
1156 /* Add a logical function to LUT mask. */
1157 static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1158 int index, int neg, uint16_t *mask)
1161 int x[2][2], tmp, a, b, aset, bset, rset;
1163 memset(x, 0, 4 * sizeof(int));
1165 /* Trigger detect condition. */
1195 case OP_NOTRISEFALL:
1201 /* Transpose if neg is set. */
1203 for (i = 0; i < 2; ++i) {
1204 for (j = 0; j < 2; ++j) {
1206 x[i][j] = x[1-i][1-j];
1212 /* Update mask with function. */
1213 for (i = 0; i < 16; ++i) {
1214 a = (i >> (2 * index + 0)) & 1;
1215 b = (i >> (2 * index + 1)) & 1;
1217 aset = (*mask >> i) & 1;
1220 if (func == FUNC_AND || func == FUNC_NAND)
1222 else if (func == FUNC_OR || func == FUNC_NOR)
1224 else if (func == FUNC_XOR || func == FUNC_NXOR)
1227 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1238 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1239 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1240 * set at any time, but a full mask and value can be set (0/1).
1242 static int build_basic_trigger(struct triggerlut *lut, struct context *ctx)
1245 uint16_t masks[2] = { 0, 0 };
1247 memset(lut, 0, sizeof(struct triggerlut));
1249 /* Contant for simple triggers. */
1252 /* Value/mask trigger support. */
1253 build_lut_entry(ctx->trigger.simplevalue, ctx->trigger.simplemask,
1256 /* Rise/fall trigger support. */
1257 for (i = 0, j = 0; i < 16; ++i) {
1258 if (ctx->trigger.risingmask & (1 << i) ||
1259 ctx->trigger.fallingmask & (1 << i))
1260 masks[j++] = 1 << i;
1263 build_lut_entry(masks[0], masks[0], lut->m0d);
1264 build_lut_entry(masks[1], masks[1], lut->m1d);
1266 /* Add glue logic */
1267 if (masks[0] || masks[1]) {
1268 /* Transition trigger. */
1269 if (masks[0] & ctx->trigger.risingmask)
1270 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1271 if (masks[0] & ctx->trigger.fallingmask)
1272 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1273 if (masks[1] & ctx->trigger.risingmask)
1274 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1275 if (masks[1] & ctx->trigger.fallingmask)
1276 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1278 /* Only value/mask trigger. */
1282 /* Triggertype: event. */
1283 lut->params.selres = 3;
1288 static int hw_dev_acquisition_start(int dev_index, void *cb_data)
1290 struct sr_dev_inst *sdi;
1291 struct context *ctx;
1292 struct sr_datafeed_packet *packet;
1293 struct sr_datafeed_header *header;
1294 struct sr_datafeed_meta_logic meta;
1295 struct clockselect_50 clockselect;
1296 int frac, triggerpin, ret;
1297 uint8_t triggerselect;
1298 struct triggerinout triggerinout_conf;
1299 struct triggerlut lut;
1301 if (!(sdi = sr_dev_inst_get(adi->instances, dev_index)))
1306 /* If the samplerate has not been set, default to 200 kHz. */
1307 if (ctx->cur_firmware == -1) {
1308 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1312 /* Enter trigger programming mode. */
1313 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, ctx);
1315 /* 100 and 200 MHz mode. */
1316 if (ctx->cur_samplerate >= SR_MHZ(100)) {
1317 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, ctx);
1319 /* Find which pin to trigger on from mask. */
1320 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1321 if ((ctx->trigger.risingmask | ctx->trigger.fallingmask) &
1325 /* Set trigger pin and light LED on trigger. */
1326 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1328 /* Default rising edge. */
1329 if (ctx->trigger.fallingmask)
1330 triggerselect |= 1 << 3;
1332 /* All other modes. */
1333 } else if (ctx->cur_samplerate <= SR_MHZ(50)) {
1334 build_basic_trigger(&lut, ctx);
1336 sigma_write_trigger_lut(&lut, ctx);
1338 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1341 /* Setup trigger in and out pins to default values. */
1342 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1343 triggerinout_conf.trgout_bytrigger = 1;
1344 triggerinout_conf.trgout_enable = 1;
1346 sigma_write_register(WRITE_TRIGGER_OPTION,
1347 (uint8_t *) &triggerinout_conf,
1348 sizeof(struct triggerinout), ctx);
1350 /* Go back to normal mode. */
1351 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, ctx);
1353 /* Set clock select register. */
1354 if (ctx->cur_samplerate == SR_MHZ(200))
1355 /* Enable 4 probes. */
1356 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, ctx);
1357 else if (ctx->cur_samplerate == SR_MHZ(100))
1358 /* Enable 8 probes. */
1359 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, ctx);
1362 * 50 MHz mode (or fraction thereof). Any fraction down to
1363 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1365 frac = SR_MHZ(50) / ctx->cur_samplerate - 1;
1367 clockselect.async = 0;
1368 clockselect.fraction = frac;
1369 clockselect.disabled_probes = 0;
1371 sigma_write_register(WRITE_CLOCK_SELECT,
1372 (uint8_t *) &clockselect,
1373 sizeof(clockselect), ctx);
1376 /* Setup maximum post trigger time. */
1377 sigma_set_register(WRITE_POST_TRIGGER,
1378 (ctx->capture_ratio * 255) / 100, ctx);
1380 /* Start acqusition. */
1381 gettimeofday(&ctx->start_tv, 0);
1382 sigma_set_register(WRITE_MODE, 0x0d, ctx);
1384 ctx->session_dev_id = cb_data;
1386 if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) {
1387 sr_err("sigma: %s: packet malloc failed.", __func__);
1388 return SR_ERR_MALLOC;
1391 if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) {
1392 sr_err("sigma: %s: header malloc failed.", __func__);
1393 return SR_ERR_MALLOC;
1396 /* Send header packet to the session bus. */
1397 packet->type = SR_DF_HEADER;
1398 packet->payload = header;
1399 header->feed_version = 1;
1400 gettimeofday(&header->starttime, NULL);
1401 sr_session_send(ctx->session_dev_id, packet);
1403 /* Send metadata about the SR_DF_LOGIC packets to come. */
1404 packet->type = SR_DF_META_LOGIC;
1405 packet->payload = &meta;
1406 meta.samplerate = ctx->cur_samplerate;
1407 meta.num_probes = ctx->num_probes;
1408 sr_session_send(ctx->session_dev_id, packet);
1410 /* Add capture source. */
1411 sr_source_add(0, G_IO_IN, 10, receive_data, sdi);
1416 ctx->state.state = SIGMA_CAPTURE;
1421 static int hw_dev_acquisition_stop(int dev_index, void *cb_data)
1423 struct sr_dev_inst *sdi;
1424 struct context *ctx;
1427 /* Avoid compiler warnings. */
1430 if (!(sdi = sr_dev_inst_get(adi->instances, dev_index))) {
1431 sr_err("sigma: %s: sdi was NULL", __func__);
1435 if (!(ctx = sdi->priv)) {
1436 sr_err("sigma: %s: sdi->priv was NULL", __func__);
1440 /* Stop acquisition. */
1441 sigma_set_register(WRITE_MODE, 0x11, ctx);
1443 /* Set SDRAM Read Enable. */
1444 sigma_set_register(WRITE_MODE, 0x02, ctx);
1446 /* Get the current position. */
1447 sigma_read_pos(&ctx->state.stoppos, &ctx->state.triggerpos, ctx);
1449 /* Check if trigger has fired. */
1450 modestatus = sigma_get_register(READ_MODE, ctx);
1451 if (modestatus & 0x20)
1452 ctx->state.triggerchunk = ctx->state.triggerpos / 512;
1454 ctx->state.triggerchunk = -1;
1456 ctx->state.chunks_downloaded = 0;
1458 ctx->state.state = SIGMA_DOWNLOAD;
1463 SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
1464 .name = "asix-sigma",
1465 .longname = "ASIX SIGMA/SIGMA2",
1468 .cleanup = hw_cleanup,
1470 .dev_open = hw_dev_open,
1471 .dev_close = hw_dev_close,
1472 .dev_info_get = hw_dev_info_get,
1473 .dev_status_get = hw_dev_status_get,
1474 // .hwcap_get_all = hw_hwcap_get_all,
1475 .dev_config_set = hw_dev_config_set,
1476 .dev_acquisition_start = hw_dev_acquisition_start,
1477 .dev_acquisition_stop = hw_dev_acquisition_stop,