2 * This file is part of the sigrok project.
4 * Copyright (C) 2010 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 * ASIX Sigma Logic Analyzer Driver
30 #include "asix-sigma.h"
32 #define USB_VENDOR 0xa600
33 #define USB_PRODUCT 0xa000
34 #define USB_DESCRIPTION "ASIX SIGMA"
35 #define USB_VENDOR_NAME "ASIX"
36 #define USB_MODEL_NAME "SIGMA"
37 #define USB_MODEL_VERSION ""
38 #define TRIGGER_TYPES "rf10"
40 static GSList *device_instances = NULL;
42 // XXX These should be per device
43 static struct ftdi_context ftdic;
44 static uint64_t cur_samplerate = 0;
45 static uint32_t limit_msec = 0;
46 static struct timeval start_tv;
47 static int cur_firmware = -1;
48 static int num_probes = 0;
49 static int samples_per_event = 0;
50 static int capture_ratio = 50;
52 /* Single-pin trigger support (100 and 200 MHz).*/
53 static uint8_t triggerpin = 1;
54 static uint8_t triggerfall = 0;
56 /* Simple trigger support (<= 50 MHz). */
57 static uint16_t triggermask = 1;
58 static uint16_t triggervalue = 1;
60 static uint64_t supported_samplerates[] = {
74 static struct samplerates samplerates = {
78 supported_samplerates,
81 static int capabilities[] = {
91 /* Force the FPGA to reboot. */
92 static uint8_t suicide[] = {
93 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
96 /* Prepare to upload firmware (FPGA specific). */
97 static uint8_t init[] = {
98 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
101 /* Initialize the logic analyzer mode. */
102 static uint8_t logic_mode_start[] = {
103 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
104 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
107 static const char *firmware_files[] = {
108 "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */
109 "asix-sigma-100.fw", /* 100 MHz */
110 "asix-sigma-200.fw", /* 200 MHz */
111 "asix-sigma-50sync.fw", /* Synchronous clock from pin */
112 "asix-sigma-phasor.fw", /* Frequency counter */
115 static int sigma_read(void *buf, size_t size)
119 ret = ftdi_read_data(&ftdic, (unsigned char *)buf, size);
121 g_warning("ftdi_read_data failed: %s",
122 ftdi_get_error_string(&ftdic));
128 static int sigma_write(void *buf, size_t size)
132 ret = ftdi_write_data(&ftdic, (unsigned char *)buf, size);
134 g_warning("ftdi_write_data failed: %s",
135 ftdi_get_error_string(&ftdic));
136 } else if ((size_t) ret != size) {
137 g_warning("ftdi_write_data did not complete write\n");
143 static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len)
146 uint8_t buf[len + 2];
149 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
150 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
152 for (i = 0; i < len; ++i) {
153 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
154 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
157 return sigma_write(buf, idx);
160 static int sigma_set_register(uint8_t reg, uint8_t value)
162 return sigma_write_register(reg, &value, 1);
165 static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len)
169 buf[0] = REG_ADDR_LOW | (reg & 0xf);
170 buf[1] = REG_ADDR_HIGH | (reg >> 4);
171 buf[2] = REG_READ_ADDR;
173 sigma_write(buf, sizeof(buf));
175 return sigma_read(data, len);
178 static uint8_t sigma_get_register(uint8_t reg)
182 if (1 != sigma_read_register(reg, &value, 1)) {
183 g_warning("Sigma_get_register: 1 byte expected");
190 static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos)
193 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
195 REG_READ_ADDR | NEXT_REG,
196 REG_READ_ADDR | NEXT_REG,
197 REG_READ_ADDR | NEXT_REG,
198 REG_READ_ADDR | NEXT_REG,
199 REG_READ_ADDR | NEXT_REG,
200 REG_READ_ADDR | NEXT_REG,
204 sigma_write(buf, sizeof(buf));
206 sigma_read(result, sizeof(result));
208 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
209 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
211 /* Not really sure why this must be done, but according to spec. */
212 if ((--*stoppos & 0x1ff) == 0x1ff)
215 if ((*--triggerpos & 0x1ff) == 0x1ff)
221 static int sigma_read_dram(uint16_t startchunk, size_t numchunks, uint8_t *data)
227 /* Send the startchunk. Index start with 1. */
228 buf[0] = startchunk >> 8;
229 buf[1] = startchunk & 0xff;
230 sigma_write_register(WRITE_MEMROW, buf, 2);
233 buf[idx++] = REG_DRAM_BLOCK;
234 buf[idx++] = REG_DRAM_WAIT_ACK;
236 for (i = 0; i < numchunks; ++i) {
237 /* Alternate bit to copy from DRAM to cache. */
238 if (i != (numchunks - 1))
239 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
241 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
243 if (i != (numchunks - 1))
244 buf[idx++] = REG_DRAM_WAIT_ACK;
247 sigma_write(buf, idx);
249 return sigma_read(data, numchunks * CHUNK_SIZE);
252 /* Upload trigger look-up tables to Sigma */
253 static int sigma_write_trigger_lut(struct triggerlut *lut)
259 /* Transpose the table and send to Sigma. */
260 for (i = 0; i < 16; ++i) {
265 if (lut->m2d[0] & bit)
267 if (lut->m2d[1] & bit)
269 if (lut->m2d[2] & bit)
271 if (lut->m2d[3] & bit)
281 if (lut->m0d[0] & bit)
283 if (lut->m0d[1] & bit)
285 if (lut->m0d[2] & bit)
287 if (lut->m0d[3] & bit)
290 if (lut->m1d[0] & bit)
292 if (lut->m1d[1] & bit)
294 if (lut->m1d[2] & bit)
296 if (lut->m1d[3] & bit)
299 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp));
300 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i);
303 /* Send the parameters */
304 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
305 sizeof(lut->params));
310 /* Generate the bitbang stream for programming the FPGA. */
311 static int bin2bitbang(const char *filename,
312 unsigned char **buf, size_t *buf_size)
316 unsigned long offset = 0;
318 uint8_t *compressed_buf, *firmware;
319 uLongf csize, fwsize;
320 const int buffer_size = 65536;
323 uint32_t imm = 0x3f6df2ab;
325 f = fopen(filename, "r");
327 g_warning("fopen(\"%s\", \"r\")", filename);
331 if (-1 == fseek(f, 0, SEEK_END)) {
332 g_warning("fseek on %s failed", filename);
337 file_size = ftell(f);
339 fseek(f, 0, SEEK_SET);
341 compressed_buf = g_malloc(file_size);
342 firmware = g_malloc(buffer_size);
344 if (!compressed_buf || !firmware) {
345 g_warning("Error allocating buffers");
350 while ((c = getc(f)) != EOF) {
351 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
352 compressed_buf[csize++] = c ^ imm;
356 fwsize = buffer_size;
357 ret = uncompress(firmware, &fwsize, compressed_buf, csize);
359 g_free(compressed_buf);
361 g_warning("Could not unpack Sigma firmware. (Error %d)\n", ret);
365 g_free(compressed_buf);
367 *buf_size = fwsize * 2 * 8;
369 *buf = p = (unsigned char *)g_malloc(*buf_size);
372 g_warning("Error allocating buffers");
376 for (i = 0; i < fwsize; ++i) {
377 for (bit = 7; bit >= 0; --bit) {
378 v = firmware[i] & 1 << bit ? 0x40 : 0x00;
379 p[offset++] = v | 0x01;
386 if (offset != *buf_size) {
388 g_warning("Error reading firmware %s "
389 "offset=%ld, file_size=%ld, buf_size=%zd\n",
390 filename, offset, file_size, *buf_size);
398 static int hw_init(char *deviceinfo)
400 struct sigrok_device_instance *sdi;
402 deviceinfo = deviceinfo;
406 /* Look for SIGMAs. */
407 if (ftdi_usb_open_desc(&ftdic, USB_VENDOR, USB_PRODUCT,
408 USB_DESCRIPTION, NULL) < 0)
411 /* Register SIGMA device. */
412 sdi = sigrok_device_instance_new(0, ST_INITIALIZING,
413 USB_VENDOR_NAME, USB_MODEL_NAME, USB_MODEL_VERSION);
417 device_instances = g_slist_append(device_instances, sdi);
419 /* We will open the device again when we need it. */
420 ftdi_usb_close(&ftdic);
425 static int upload_firmware(int firmware_idx)
431 unsigned char result[32];
432 char firmware_path[128];
434 /* Make sure it's an ASIX SIGMA. */
435 if ((ret = ftdi_usb_open_desc(&ftdic,
436 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
437 g_warning("ftdi_usb_open failed: %s",
438 ftdi_get_error_string(&ftdic));
442 if ((ret = ftdi_set_bitmode(&ftdic, 0xdf, BITMODE_BITBANG)) < 0) {
443 g_warning("ftdi_set_bitmode failed: %s",
444 ftdi_get_error_string(&ftdic));
448 /* Four times the speed of sigmalogan - Works well. */
449 if ((ret = ftdi_set_baudrate(&ftdic, 750000)) < 0) {
450 g_warning("ftdi_set_baudrate failed: %s",
451 ftdi_get_error_string(&ftdic));
455 /* Force the FPGA to reboot. */
456 sigma_write(suicide, sizeof(suicide));
457 sigma_write(suicide, sizeof(suicide));
458 sigma_write(suicide, sizeof(suicide));
459 sigma_write(suicide, sizeof(suicide));
461 /* Prepare to upload firmware (FPGA specific). */
462 sigma_write(init, sizeof(init));
464 ftdi_usb_purge_buffers(&ftdic);
466 /* Wait until the FPGA asserts INIT_B. */
468 ret = sigma_read(result, 1);
469 if (result[0] & 0x20)
473 /* Prepare firmware. */
474 snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR,
475 firmware_files[firmware_idx]);
477 if (-1 == bin2bitbang(firmware_path, &buf, &buf_size)) {
478 g_warning("An error occured while reading the firmware: %s",
483 /* Upload firmare. */
484 sigma_write(buf, buf_size);
488 if ((ret = ftdi_set_bitmode(&ftdic, 0x00, BITMODE_RESET)) < 0) {
489 g_warning("ftdi_set_bitmode failed: %s",
490 ftdi_get_error_string(&ftdic));
494 ftdi_usb_purge_buffers(&ftdic);
496 /* Discard garbage. */
497 while (1 == sigma_read(&pins, 1))
500 /* Initialize the logic analyzer mode. */
501 sigma_write(logic_mode_start, sizeof(logic_mode_start));
503 /* Expect a 3 byte reply. */
504 ret = sigma_read(result, 3);
506 result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
507 g_warning("Configuration failed. Invalid reply received.");
511 cur_firmware = firmware_idx;
516 static int hw_opendev(int device_index)
518 struct sigrok_device_instance *sdi;
521 /* Make sure it's an ASIX SIGMA. */
522 if ((ret = ftdi_usb_open_desc(&ftdic,
523 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
525 g_warning("ftdi_usb_open failed: %s",
526 ftdi_get_error_string(&ftdic));
531 if (!(sdi = get_sigrok_device_instance(device_instances, device_index)))
534 sdi->status = ST_ACTIVE;
539 static int set_samplerate(struct sigrok_device_instance *sdi, uint64_t samplerate)
545 for (i = 0; supported_samplerates[i]; i++) {
546 if (supported_samplerates[i] == samplerate)
549 if (supported_samplerates[i] == 0)
550 return SIGROK_ERR_SAMPLERATE;
552 if (samplerate <= MHZ(50)) {
553 ret = upload_firmware(0);
556 if (samplerate == MHZ(100)) {
557 ret = upload_firmware(1);
560 else if (samplerate == MHZ(200)) {
561 ret = upload_firmware(2);
565 cur_samplerate = samplerate;
566 samples_per_event = 16 / num_probes;
568 g_message("Firmware uploaded");
573 /* Only trigger on single pin supported (in 100-200 MHz modes). */
574 static int configure_probes(GSList *probes)
583 for (l = probes; l; l = l->next) {
584 probe = (struct probe *)l->data;
586 if (!probe->enabled || !probe->trigger)
589 if (cur_samplerate >= MHZ(100)) {
590 /* Fast trigger support */
592 g_warning("Asix Sigma only supports a single pin trigger "
593 "in 100 and 200 MHz mode.");
596 if (probe->trigger[0] == 'f')
598 else if (probe->trigger[0] == 'r')
601 g_warning("Asix Sigma only supports "
602 "rising/falling trigger in 100 "
603 "and 200 MHz mode.");
607 triggerpin = probe->index - 1;
609 /* Normal trigger support */
610 triggermask |= 1 << (probe->index - 1);
612 if (probe->trigger[0] == '1')
613 triggervalue |= 1 << (probe->index - 1);
614 else if (probe->trigger[0] == '0')
615 triggervalue |= 0 << (probe->index - 1);
617 g_warning("Asix Sigma only supports "
618 "trigger values in <= 50"
631 static void hw_closedev(int device_index)
633 device_index = device_index;
635 ftdi_usb_close(&ftdic);
638 static void hw_cleanup(void)
642 static void *hw_get_device_info(int device_index, int device_info_id)
644 struct sigrok_device_instance *sdi;
647 if (!(sdi = get_sigrok_device_instance(device_instances, device_index))) {
648 fprintf(stderr, "It's NULL.\n");
652 switch (device_info_id) {
657 info = GINT_TO_POINTER(16);
662 case DI_TRIGGER_TYPES:
663 info = (char *)TRIGGER_TYPES;
665 case DI_CUR_SAMPLERATE:
666 info = &cur_samplerate;
673 static int hw_get_status(int device_index)
675 struct sigrok_device_instance *sdi;
677 sdi = get_sigrok_device_instance(device_instances, device_index);
684 static int *hw_get_capabilities(void)
689 static int hw_set_configuration(int device_index, int capability, void *value)
691 struct sigrok_device_instance *sdi;
694 if (!(sdi = get_sigrok_device_instance(device_instances, device_index)))
697 if (capability == HWCAP_SAMPLERATE) {
698 ret = set_samplerate(sdi, *(uint64_t*) value);
699 } else if (capability == HWCAP_PROBECONFIG) {
700 ret = configure_probes(value);
701 } else if (capability == HWCAP_LIMIT_MSEC) {
702 limit_msec = strtoull(value, NULL, 10);
704 } else if (capability == HWCAP_CAPTURE_RATIO) {
705 capture_ratio = strtoull(value, NULL, 10);
707 } else if (capability == HWCAP_PROBECONFIG) {
708 ret = configure_probes((GSList *) value);
717 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
718 * Each event is 20ns apart, and can contain multiple samples.
720 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
721 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
722 * For 50 MHz and below, events contain one sample for each channel,
723 * spread 20 ns apart.
725 static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
726 uint16_t *lastsample, int triggerpos, void *user_data)
729 uint16_t samples[65536 * samples_per_event];
730 struct datafeed_packet packet;
731 int i, j, k, l, numpad, tosend;
732 size_t n = 0, sent = 0;
733 int clustersize = EVENTS_PER_CLUSTER * samples_per_event;
739 if (triggerpos != -1) {
740 if (cur_samplerate <= MHZ(50))
741 triggerpos -= EVENTS_PER_CLUSTER;
748 /* Find in which cluster the trigger occured. */
749 triggerts = triggerpos / 7;
753 for (i = 0; i < 64; ++i) {
754 ts = *(uint16_t *) &buf[i * 16];
755 tsdiff = ts - *lastts;
758 /* Pad last sample up to current point. */
759 numpad = tsdiff * samples_per_event - clustersize;
761 for (j = 0; j < numpad; ++j)
762 samples[j] = *lastsample;
767 /* Send samples between previous and this timestamp to sigrok. */
770 tosend = MIN(2048, n - sent);
772 packet.type = DF_LOGIC16;
773 packet.length = tosend * sizeof(uint16_t);
774 packet.payload = samples + sent;
775 session_bus(user_data, &packet);
781 event = (uint16_t *) &buf[i * 16 + 2];
784 /* For each event in cluster. */
785 for (j = 0; j < 7; ++j) {
787 /* For each sample in event. */
788 for (k = 0; k < samples_per_event; ++k) {
791 /* For each probe. */
792 for (l = 0; l < num_probes; ++l)
793 cur_sample |= (!!(event[j] & (1 << (l *
794 samples_per_event + k))))
797 samples[n++] = cur_sample;
801 /* Send data up to trigger point (if triggered). */
803 if (i == triggerts) {
805 * Trigger is presumptively only accurate to event, i.e.
806 * for 100 and 200 MHz, where multiple samples are coded
807 * in a single event, the trigger does not match the
810 tosend = (triggerpos % 7) - triggeroff;
813 packet.type = DF_LOGIC16;
814 packet.length = tosend * sizeof(uint16_t);
815 packet.payload = samples;
816 session_bus(user_data, &packet);
821 packet.type = DF_TRIGGER;
824 session_bus(user_data, &packet);
827 /* Send rest of the chunk to sigrok. */
830 packet.type = DF_LOGIC16;
831 packet.length = tosend * sizeof(uint16_t);
832 packet.payload = samples + sent;
833 session_bus(user_data, &packet);
835 *lastsample = samples[n - 1];
841 static int receive_data(int fd, int revents, void *user_data)
843 struct datafeed_packet packet;
844 const int chunks_per_read = 32;
845 unsigned char buf[chunks_per_read * CHUNK_SIZE];
846 int bufsz, numchunks, curchunk, i, newchunks;
847 uint32_t triggerpos, stoppos, running_msec;
850 uint16_t lastsample = 0;
852 int triggerchunk = -1;
857 /* Get the current position. */
858 sigma_read_pos(&stoppos, &triggerpos);
859 numchunks = stoppos / 512;
861 /* Check if the has expired, or memory is full. */
862 gettimeofday(&tv, 0);
863 running_msec = (tv.tv_sec - start_tv.tv_sec) * 1000 +
864 (tv.tv_usec - start_tv.tv_usec) / 1000;
866 if (running_msec < limit_msec && numchunks < 32767)
869 /* Stop acqusition. */
870 sigma_set_register(WRITE_MODE, 0x11);
872 /* Set SDRAM Read Enable. */
873 sigma_set_register(WRITE_MODE, 0x02);
875 /* Get the current position. */
876 sigma_read_pos(&stoppos, &triggerpos);
878 /* Check if trigger has fired. */
879 modestatus = sigma_get_register(READ_MODE);
880 if (modestatus & 0x20) {
881 triggerchunk = triggerpos / 512;
884 /* Download sample data. */
885 for (curchunk = 0; curchunk < numchunks;) {
886 newchunks = MIN(chunks_per_read, numchunks - curchunk);
888 g_message("Downloading sample data: %.0f %%",
889 100.0 * curchunk / numchunks);
891 bufsz = sigma_read_dram(curchunk, newchunks, buf);
895 lastts = *(uint16_t *) buf - 1;
897 /* Decode chunks and send them to sigrok. */
898 for (i = 0; i < newchunks; ++i) {
899 if (curchunk + i == triggerchunk)
900 decode_chunk_ts(buf + (i * CHUNK_SIZE),
901 &lastts, &lastsample,
902 triggerpos & 0x1ff, user_data);
904 decode_chunk_ts(buf + (i * CHUNK_SIZE),
905 &lastts, &lastsample,
909 curchunk += newchunks;
913 packet.type = DF_END;
915 session_bus(user_data, &packet);
921 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
922 * simple pin change and state triggers. Only two transitions (rise/fall) can be
923 * set at any time, but a full mask and value can be set (0/1).
925 static int build_basic_trigger(struct triggerlut *lut)
929 memset(lut, 0, sizeof(struct triggerlut));
934 /* Set the LUT for controlling value/maske trigger */
935 for (i = 0; i < 4; ++i) {
936 lut->m2d[i] = 0xffff;
938 for (j = 0; j < 16; ++j)
940 for (k = 0; k < 4; ++k) {
941 bit = 1 << (i * 4 + k);
943 if ((triggermask & bit) &&
944 (triggervalue & bit) != (j & (1 << k))) {
945 lut->m2d[i] &= ~(1 << j);
951 /* Unused when not triggering on transitions */
954 /* Triggertype: event */
955 lut->params.selres = 3;
960 static int hw_start_acquisition(int device_index, gpointer session_device_id)
962 struct sigrok_device_instance *sdi;
963 struct datafeed_packet packet;
964 struct datafeed_header header;
965 struct clockselect_50 clockselect;
967 uint8_t triggerselect;
968 struct triggerinout triggerinout_conf;
969 struct triggerlut lut;
971 session_device_id = session_device_id;
973 if (!(sdi = get_sigrok_device_instance(device_instances, device_index)))
976 device_index = device_index;
978 /* If the samplerate has not been set, default to 50 MHz. */
979 if (cur_firmware == -1)
980 set_samplerate(sdi, MHZ(50));
982 /* Enter trigger programming mode. */
983 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20);
985 /* 100 and 200 MHz mode. */
986 if (cur_samplerate >= MHZ(100)) {
987 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81);
989 triggerselect = (1 << LEDSEL1) | (triggerfall << 3) |
992 /* All other modes. */
993 } else if (cur_samplerate <= MHZ(50)) {
994 build_basic_trigger(&lut);
996 sigma_write_trigger_lut(&lut);
998 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1001 /* Setup trigger in and out pins to default values. */
1002 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1003 triggerinout_conf.trgout_bytrigger = 1;
1004 triggerinout_conf.trgout_enable = 1;
1006 sigma_write_register(WRITE_TRIGGER_OPTION,
1007 (uint8_t *) &triggerinout_conf,
1008 sizeof(struct triggerinout));
1010 /* Go back to normal mode. */
1011 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect);
1013 /* Set clock select register. */
1014 if (cur_samplerate == MHZ(200))
1015 /* Enable 4 probes. */
1016 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0);
1017 else if (cur_samplerate == MHZ(100))
1018 /* Enable 8 probes. */
1019 sigma_set_register(WRITE_CLOCK_SELECT, 0x00);
1022 * 50 MHz mode (or fraction thereof). Any fraction down to
1023 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1025 frac = MHZ(50) / cur_samplerate - 1;
1027 clockselect.async = 0;
1028 clockselect.fraction = frac;
1029 clockselect.disabled_probes = 0;
1031 sigma_write_register(WRITE_CLOCK_SELECT,
1032 (uint8_t *) &clockselect,
1033 sizeof(clockselect));
1036 /* Setup maximum post trigger time. */
1037 sigma_set_register(WRITE_POST_TRIGGER, (capture_ratio * 256) / 100);
1039 /* Start acqusition. */
1040 gettimeofday(&start_tv, 0);
1041 sigma_set_register(WRITE_MODE, 0x0d);
1043 /* Send header packet to the session bus. */
1044 packet.type = DF_HEADER;
1045 packet.length = sizeof(struct datafeed_header);
1046 packet.payload = &header;
1047 header.feed_version = 1;
1048 gettimeofday(&header.starttime, NULL);
1049 header.samplerate = cur_samplerate;
1050 header.protocol_id = PROTO_RAW;
1051 header.num_probes = num_probes;
1052 session_bus(session_device_id, &packet);
1054 /* Add capture source. */
1055 source_add(0, G_IO_IN, 10, receive_data, session_device_id);
1060 static void hw_stop_acquisition(int device_index, gpointer session_device_id)
1062 device_index = device_index;
1063 session_device_id = session_device_id;
1065 /* Stop acquisition. */
1066 sigma_set_register(WRITE_MODE, 0x11);
1068 // XXX Set some state to indicate that data should be sent to sigrok
1069 // Now, we just wait for timeout
1072 struct device_plugin asix_sigma_plugin_info = {
1081 hw_get_capabilities,
1082 hw_set_configuration,
1083 hw_start_acquisition,
1084 hw_stop_acquisition,