2 * This file is part of the sigrok project.
4 * Copyright (C) 2010 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 * ASIX Sigma Logic Analyzer Driver
30 #include "asix-sigma.h"
32 #define USB_VENDOR 0xa600
33 #define USB_PRODUCT 0xa000
34 #define USB_DESCRIPTION "ASIX SIGMA"
35 #define USB_VENDOR_NAME "ASIX"
36 #define USB_MODEL_NAME "SIGMA"
37 #define USB_MODEL_VERSION ""
38 #define TRIGGER_TYPES "rf"
40 static GSList *device_instances = NULL;
42 // XXX These should be per device
43 static struct ftdi_context ftdic;
44 static uint64_t cur_samplerate = 0;
45 static uint32_t limit_msec = 0;
46 static struct timeval start_tv;
47 static int cur_firmware = -1;
48 static int num_probes = 0;
49 static int samples_per_event = 0;
50 static int capture_ratio = 50;
52 /* Single-pin trigger support */
53 static uint8_t triggerpin = 1;
54 static uint8_t triggerfall = 0;
56 static uint64_t supported_samplerates[] = {
70 static struct samplerates samplerates = {
74 supported_samplerates,
77 static int capabilities[] = {
83 /* These are really implemented in the driver, not the hardware. */
88 /* Force the FPGA to reboot. */
89 static uint8_t suicide[] = {
90 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
93 /* Prepare to upload firmware (FPGA specific). */
94 static uint8_t init[] = {
95 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
98 /* Initialize the logic analyzer mode. */
99 static uint8_t logic_mode_start[] = {
100 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
101 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
104 static const char *firmware_files[] =
106 "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */
107 "asix-sigma-100.fw", /* 100 MHz */
108 "asix-sigma-200.fw", /* 200 MHz */
109 "asix-sigma-50sync.fw", /* Synchronous clock from pin */
110 "asix-sigma-phasor.fw", /* Frequency counter */
113 static int sigma_read(void *buf, size_t size)
117 ret = ftdi_read_data(&ftdic, (unsigned char *)buf, size);
119 g_warning("ftdi_read_data failed: %s",
120 ftdi_get_error_string(&ftdic));
126 static int sigma_write(void *buf, size_t size)
130 ret = ftdi_write_data(&ftdic, (unsigned char *)buf, size);
132 g_warning("ftdi_write_data failed: %s",
133 ftdi_get_error_string(&ftdic));
134 } else if ((size_t) ret != size) {
135 g_warning("ftdi_write_data did not complete write\n");
141 static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len)
144 uint8_t buf[len + 2];
147 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
148 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
150 for (i = 0; i < len; ++i) {
151 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
152 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
155 return sigma_write(buf, idx);
158 static int sigma_set_register(uint8_t reg, uint8_t value)
160 return sigma_write_register(reg, &value, 1);
163 static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len)
167 buf[0] = REG_ADDR_LOW | (reg & 0xf);
168 buf[1] = REG_ADDR_HIGH | (reg >> 4);
169 buf[2] = REG_READ_ADDR;
171 sigma_write(buf, sizeof(buf));
173 return sigma_read(data, len);
176 static uint8_t sigma_get_register(uint8_t reg)
180 if (1 != sigma_read_register(reg, &value, 1)) {
181 g_warning("Sigma_get_register: 1 byte expected");
188 static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos)
191 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
193 REG_READ_ADDR | NEXT_REG,
194 REG_READ_ADDR | NEXT_REG,
195 REG_READ_ADDR | NEXT_REG,
196 REG_READ_ADDR | NEXT_REG,
197 REG_READ_ADDR | NEXT_REG,
198 REG_READ_ADDR | NEXT_REG,
202 sigma_write(buf, sizeof(buf));
204 sigma_read(result, sizeof(result));
206 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
207 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
209 /* Not really sure why this must be done, but according to spec. */
210 if ((--*stoppos & 0x1ff) == 0x1ff)
213 if ((*--triggerpos & 0x1ff) == 0x1ff)
219 static int sigma_read_dram(uint16_t startchunk, size_t numchunks, uint8_t *data)
225 /* Send the startchunk. Index start with 1. */
226 buf[0] = startchunk >> 8;
227 buf[1] = startchunk & 0xff;
228 sigma_write_register(WRITE_MEMROW, buf, 2);
231 buf[idx++] = REG_DRAM_BLOCK;
232 buf[idx++] = REG_DRAM_WAIT_ACK;
234 for (i = 0; i < numchunks; ++i) {
235 /* Alternate bit to copy from DRAM to cache. */
236 if (i != (numchunks - 1))
237 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
239 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
241 if (i != (numchunks - 1))
242 buf[idx++] = REG_DRAM_WAIT_ACK;
245 sigma_write(buf, idx);
247 return sigma_read(data, numchunks * CHUNK_SIZE);
250 /* Generate the bitbang stream for programming the FPGA. */
251 static int bin2bitbang(const char *filename,
252 unsigned char **buf, size_t *buf_size)
256 unsigned long offset = 0;
258 uint8_t *compressed_buf, *firmware;
259 uLongf csize, fwsize;
260 const int buffer_size = 65536;
263 uint32_t imm = 0x3f6df2ab;
265 f = fopen(filename, "r");
267 g_warning("fopen(\"%s\", \"r\")", filename);
271 if (-1 == fseek(f, 0, SEEK_END)) {
272 g_warning("fseek on %s failed", filename);
277 file_size = ftell(f);
279 fseek(f, 0, SEEK_SET);
281 compressed_buf = g_malloc(file_size);
282 firmware = g_malloc(buffer_size);
284 if (!compressed_buf || !firmware) {
285 g_warning("Error allocating buffers");
290 while ((c = getc(f)) != EOF) {
291 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
292 compressed_buf[csize++] = c ^ imm;
296 fwsize = buffer_size;
297 ret = uncompress(firmware, &fwsize, compressed_buf, csize);
299 g_free(compressed_buf);
301 g_warning("Could not unpack Sigma firmware. (Error %d)\n", ret);
305 g_free(compressed_buf);
307 *buf_size = fwsize * 2 * 8;
309 *buf = p = (unsigned char *)g_malloc(*buf_size);
312 g_warning("Error allocating buffers");
316 for (i = 0; i < fwsize; ++i) {
317 for (bit = 7; bit >= 0; --bit) {
318 v = firmware[i] & 1 << bit ? 0x40 : 0x00;
319 p[offset++] = v | 0x01;
326 if (offset != *buf_size) {
328 g_warning("Error reading firmware %s "
329 "offset=%ld, file_size=%ld, buf_size=%zd\n",
330 filename, offset, file_size, *buf_size);
338 static int hw_init(char *deviceinfo)
340 struct sigrok_device_instance *sdi;
342 deviceinfo = deviceinfo;
346 /* Look for SIGMAs. */
347 if (ftdi_usb_open_desc(&ftdic, USB_VENDOR, USB_PRODUCT,
348 USB_DESCRIPTION, NULL) < 0)
351 /* Register SIGMA device. */
352 sdi = sigrok_device_instance_new(0, ST_INITIALIZING,
353 USB_VENDOR_NAME, USB_MODEL_NAME, USB_MODEL_VERSION);
357 device_instances = g_slist_append(device_instances, sdi);
359 /* We will open the device again when we need it. */
360 ftdi_usb_close(&ftdic);
365 static int upload_firmware(int firmware_idx)
371 unsigned char result[32];
372 char firmware_path[128];
374 /* Make sure it's an ASIX SIGMA. */
375 if ((ret = ftdi_usb_open_desc(&ftdic,
376 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
377 g_warning("ftdi_usb_open failed: %s",
378 ftdi_get_error_string(&ftdic));
382 if ((ret = ftdi_set_bitmode(&ftdic, 0xdf, BITMODE_BITBANG)) < 0) {
383 g_warning("ftdi_set_bitmode failed: %s",
384 ftdi_get_error_string(&ftdic));
388 /* Four times the speed of sigmalogan - Works well. */
389 if ((ret = ftdi_set_baudrate(&ftdic, 750000)) < 0) {
390 g_warning("ftdi_set_baudrate failed: %s",
391 ftdi_get_error_string(&ftdic));
395 /* Force the FPGA to reboot. */
396 sigma_write(suicide, sizeof(suicide));
397 sigma_write(suicide, sizeof(suicide));
398 sigma_write(suicide, sizeof(suicide));
399 sigma_write(suicide, sizeof(suicide));
401 /* Prepare to upload firmware (FPGA specific). */
402 sigma_write(init, sizeof(init));
404 ftdi_usb_purge_buffers(&ftdic);
406 /* Wait until the FPGA asserts INIT_B. */
408 ret = sigma_read(result, 1);
409 if (result[0] & 0x20)
413 /* Prepare firmware. */
414 snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR,
415 firmware_files[firmware_idx]);
417 if (-1 == bin2bitbang(firmware_path, &buf, &buf_size)) {
418 g_warning("An error occured while reading the firmware: %s",
423 /* Upload firmare. */
424 sigma_write(buf, buf_size);
428 if ((ret = ftdi_set_bitmode(&ftdic, 0x00, BITMODE_RESET)) < 0) {
429 g_warning("ftdi_set_bitmode failed: %s",
430 ftdi_get_error_string(&ftdic));
434 ftdi_usb_purge_buffers(&ftdic);
436 /* Discard garbage. */
437 while (1 == sigma_read(&pins, 1))
440 /* Initialize the logic analyzer mode. */
441 sigma_write(logic_mode_start, sizeof(logic_mode_start));
443 /* Expect a 3 byte reply. */
444 ret = sigma_read(result, 3);
446 result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
447 g_warning("Configuration failed. Invalid reply received.");
451 cur_firmware = firmware_idx;
456 static int hw_opendev(int device_index)
458 struct sigrok_device_instance *sdi;
461 /* Make sure it's an ASIX SIGMA. */
462 if ((ret = ftdi_usb_open_desc(&ftdic,
463 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
465 g_warning("ftdi_usb_open failed: %s",
466 ftdi_get_error_string(&ftdic));
471 if (!(sdi = get_sigrok_device_instance(device_instances, device_index)))
474 sdi->status = ST_ACTIVE;
479 static int set_samplerate(struct sigrok_device_instance *sdi, uint64_t samplerate)
485 for (i = 0; supported_samplerates[i]; i++) {
486 if (supported_samplerates[i] == samplerate)
489 if (supported_samplerates[i] == 0)
490 return SIGROK_ERR_SAMPLERATE;
492 if (samplerate <= MHZ(50)) {
493 ret = upload_firmware(0);
496 if (samplerate == MHZ(100)) {
497 ret = upload_firmware(1);
500 else if (samplerate == MHZ(200)) {
501 ret = upload_firmware(2);
505 cur_samplerate = samplerate;
506 samples_per_event = 16 / num_probes;
508 g_message("Firmware uploaded");
513 /* Only trigger on single pin supported (in 100-200 MHz modes) */
514 static int configure_probes(GSList *probes)
520 for (l = probes; l; l = l->next) {
521 probe = (struct probe *)l->data;
523 if (!probe->enabled || !probe->trigger)
527 g_warning("Asix Sigma only supports a single pin trigger"
528 " in 100 and 200 MHz mode.");
534 if (probe->trigger[0] == 'f')
539 triggerpin = probe->index - 1;
546 static void hw_closedev(int device_index)
548 device_index = device_index;
550 ftdi_usb_close(&ftdic);
553 static void hw_cleanup(void)
557 static void *hw_get_device_info(int device_index, int device_info_id)
559 struct sigrok_device_instance *sdi;
562 if (!(sdi = get_sigrok_device_instance(device_instances, device_index))) {
563 fprintf(stderr, "It's NULL.\n");
567 switch (device_info_id) {
572 info = GINT_TO_POINTER(16);
577 case DI_TRIGGER_TYPES:
578 info = (char *)TRIGGER_TYPES;
580 case DI_CUR_SAMPLERATE:
581 info = &cur_samplerate;
588 static int hw_get_status(int device_index)
590 struct sigrok_device_instance *sdi;
592 sdi = get_sigrok_device_instance(device_instances, device_index);
599 static int *hw_get_capabilities(void)
604 static int hw_set_configuration(int device_index, int capability, void *value)
606 struct sigrok_device_instance *sdi;
609 if (!(sdi = get_sigrok_device_instance(device_instances, device_index)))
612 if (capability == HWCAP_SAMPLERATE) {
613 ret = set_samplerate(sdi, *(uint64_t*) value);
614 } else if (capability == HWCAP_PROBECONFIG) {
615 ret = configure_probes(value);
616 } else if (capability == HWCAP_LIMIT_MSEC) {
617 limit_msec = strtoull(value, NULL, 10);
619 } else if (capability == HWCAP_CAPTURE_RATIO) {
620 capture_ratio = strtoull(value, NULL, 10);
622 } else if (capability == HWCAP_PROBECONFIG) {
623 ret = configure_probes((GSList *) value);
632 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
633 * Each event is 20ns apart, and can contain multiple samples.
635 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
636 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
637 * For 50 MHz and below, events contain one sample for each channel,
638 * spread 20 ns apart.
640 static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
641 uint16_t *lastsample, int triggerpos, void *user_data)
644 uint16_t samples[65536 * samples_per_event];
645 struct datafeed_packet packet;
646 int i, j, k, l, numpad, tosend;
647 size_t n = 0, sent = 0;
648 int clustersize = EVENTS_PER_CLUSTER * samples_per_event;
653 /* Find in which cluster the trigger occured */
654 if (triggerpos != -1)
655 triggerts = (triggerpos / 7);
658 for (i = 0; i < 64; ++i) {
659 ts = *(uint16_t *) &buf[i * 16];
660 tsdiff = ts - *lastts;
663 /* Pad last sample up to current point. */
664 numpad = tsdiff * samples_per_event - clustersize;
666 for (j = 0; j < numpad; ++j)
667 samples[j] = *lastsample;
672 /* Send samples between previous and this timestamp to sigrok. */
675 tosend = MIN(2048, n - sent);
677 packet.type = DF_LOGIC16;
678 packet.length = tosend * sizeof(uint16_t);
679 packet.payload = samples + sent;
680 session_bus(user_data, &packet);
686 event = (uint16_t *) &buf[i * 16 + 2];
689 /* For each event in cluster. */
690 for (j = 0; j < 7; ++j) {
692 /* For each sample in event. */
693 for (k = 0; k < samples_per_event; ++k) {
696 /* For each probe. */
697 for (l = 0; l < num_probes; ++l)
698 cur_sample |= (!!(event[j] & (1 << (l *
699 samples_per_event + k))))
702 samples[n++] = cur_sample;
706 *lastsample = samples[n - 1];
708 /* Send data up to trigger point (if triggered) */
710 if (i == triggerts) {
712 * Trigger is presumptively only accurate to event, i.e.
713 * for 100 and 200 MHz, where multiple samples are coded
714 * in a single event, the trigger does not match the
717 tosend = (triggerpos % 7) - 3;
720 packet.type = DF_LOGIC16;
721 packet.length = tosend * sizeof(uint16_t);
722 packet.payload = samples;
723 session_bus(user_data, &packet);
728 packet.type = DF_TRIGGER;
731 session_bus(user_data, &packet);
734 /* Send rest of the chunk to sigrok */
737 packet.type = DF_LOGIC16;
738 packet.length = tosend * sizeof(uint16_t);
739 packet.payload = samples + sent;
740 session_bus(user_data, &packet);
746 static int receive_data(int fd, int revents, void *user_data)
748 struct datafeed_packet packet;
749 const int chunks_per_read = 32;
750 unsigned char buf[chunks_per_read * CHUNK_SIZE];
751 int bufsz, numchunks, curchunk, i, newchunks;
752 uint32_t triggerpos, stoppos, running_msec;
755 uint16_t lastsample = 0;
757 int triggerchunk = -1;
762 /* Get the current position. */
763 sigma_read_pos(&stoppos, &triggerpos);
764 numchunks = stoppos / 512;
766 /* Check if the has expired, or memory is full. */
767 gettimeofday(&tv, 0);
768 running_msec = (tv.tv_sec - start_tv.tv_sec) * 1000 +
769 (tv.tv_usec - start_tv.tv_usec) / 1000;
771 if (running_msec < limit_msec && numchunks < 32767)
774 /* Stop acqusition. */
775 sigma_set_register(WRITE_MODE, 0x11);
777 /* Set SDRAM Read Enable. */
778 sigma_set_register(WRITE_MODE, 0x02);
780 /* Get the current position. */
781 sigma_read_pos(&stoppos, &triggerpos);
783 /* Check if trigger has fired */
784 modestatus = sigma_get_register(READ_MODE);
785 if (modestatus & 0x20) {
786 triggerchunk = triggerpos / 512;
789 /* Download sample data. */
790 for (curchunk = 0; curchunk < numchunks;) {
791 newchunks = MIN(chunks_per_read, numchunks - curchunk);
793 g_message("Downloading sample data: %.0f %%",
794 100.0 * curchunk / numchunks);
796 bufsz = sigma_read_dram(curchunk, newchunks, buf);
800 lastts = *(uint16_t *) buf - 1;
802 /* Decode chunks and send them to sigrok. */
803 for (i = 0; i < newchunks; ++i) {
804 if (curchunk + i == triggerchunk)
805 decode_chunk_ts(buf + (i * CHUNK_SIZE),
806 &lastts, &lastsample,
807 triggerpos & 0x1ff, user_data);
809 decode_chunk_ts(buf + (i * CHUNK_SIZE),
810 &lastts, &lastsample,
814 curchunk += newchunks;
818 packet.type = DF_END;
820 session_bus(user_data, &packet);
825 static int hw_start_acquisition(int device_index, gpointer session_device_id)
827 struct sigrok_device_instance *sdi;
828 struct datafeed_packet packet;
829 struct datafeed_header header;
830 struct clockselect_50 clockselect;
832 uint8_t triggerselect;
833 struct triggerinout triggerinout_conf;
835 session_device_id = session_device_id;
837 if (!(sdi = get_sigrok_device_instance(device_instances, device_index)))
840 device_index = device_index;
842 /* If the samplerate has not been set, default to 50 MHz. */
843 if (cur_firmware == -1)
844 set_samplerate(sdi, MHZ(50));
846 /* Enter trigger programming mode */
847 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20);
849 /* 100 and 200 MHz mode */
850 if (cur_samplerate >= MHZ(100)) {
851 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81);
853 triggerselect = (1 << LEDSEL1) | (triggerfall << 3) |
856 /* All other modes */
857 } else if (cur_samplerate <= MHZ(50)) {
858 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20);
860 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
863 /* Setup trigger in and out pins to default values */
864 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
865 triggerinout_conf.trgout_bytrigger = 1;
866 triggerinout_conf.trgout_enable = 1;
868 sigma_write_register(WRITE_TRIGGER_OPTION,
869 (uint8_t *) &triggerinout_conf,
870 sizeof(struct triggerinout));
872 /* Go back to normal mode */
873 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect);
875 /* Set clock select register. */
876 if (cur_samplerate == MHZ(200))
877 /* Enable 4 probes. */
878 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0);
879 else if (cur_samplerate == MHZ(100))
880 /* Enable 8 probes. */
881 sigma_set_register(WRITE_CLOCK_SELECT, 0x00);
884 * 50 MHz mode (or fraction thereof). Any fraction down to
885 * 50 MHz / 256 can be used, but is not suppoted by sigrok API.
887 frac = MHZ(50) / cur_samplerate - 1;
889 clockselect.async = 0;
890 clockselect.fraction = frac;
891 clockselect.disabled_probes = 0;
893 sigma_write_register(WRITE_CLOCK_SELECT,
894 (uint8_t *) &clockselect,
895 sizeof(clockselect));
898 /* Setup maximum post trigger time. */
899 sigma_set_register(WRITE_POST_TRIGGER, (capture_ratio * 256) / 100);
901 /* Start acqusition (software trigger start). */
902 gettimeofday(&start_tv, 0);
903 sigma_set_register(WRITE_MODE, 0x0d);
905 /* Send header packet to the session bus. */
906 packet.type = DF_HEADER;
907 packet.length = sizeof(struct datafeed_header);
908 packet.payload = &header;
909 header.feed_version = 1;
910 gettimeofday(&header.starttime, NULL);
911 header.samplerate = cur_samplerate;
912 header.protocol_id = PROTO_RAW;
913 header.num_probes = num_probes;
914 session_bus(session_device_id, &packet);
916 /* Add capture source. */
917 source_add(0, G_IO_IN, 10, receive_data, session_device_id);
922 static void hw_stop_acquisition(int device_index, gpointer session_device_id)
924 device_index = device_index;
925 session_device_id = session_device_id;
927 /* Stop acquisition. */
928 sigma_set_register(WRITE_MODE, 0x11);
930 // XXX Set some state to indicate that data should be sent to sigrok
931 // Now, we just wait for timeout
934 struct device_plugin asix_sigma_plugin_info = {
944 hw_set_configuration,
945 hw_start_acquisition,