2 * This file is part of the sigrok project.
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
27 #include <glib/gstdio.h>
30 #include "libsigrok.h"
31 #include "libsigrok-internal.h"
32 #include "asix-sigma.h"
34 #define USB_VENDOR 0xa600
35 #define USB_PRODUCT 0xa000
36 #define USB_DESCRIPTION "ASIX SIGMA"
37 #define USB_VENDOR_NAME "ASIX"
38 #define USB_MODEL_NAME "SIGMA"
39 #define USB_MODEL_VERSION ""
40 #define TRIGGER_TYPES "rf10"
43 SR_PRIV struct sr_dev_driver asix_sigma_driver_info;
44 static struct sr_dev_driver *adi = &asix_sigma_driver_info;
46 static const uint64_t supported_samplerates[] = {
61 * Probe numbers seem to go from 1-16, according to this image:
62 * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
63 * (the cable has two additional GND pins, and a TI and TO pin)
65 static const char *probe_names[NUM_PROBES + 1] = {
85 static const struct sr_samplerates samplerates = {
89 supported_samplerates,
92 static const int hwcaps[] = {
93 SR_HWCAP_LOGIC_ANALYZER,
95 SR_HWCAP_CAPTURE_RATIO,
102 /* Force the FPGA to reboot. */
103 static uint8_t suicide[] = {
104 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
107 /* Prepare to upload firmware (FPGA specific). */
108 static uint8_t init[] = {
109 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
112 /* Initialize the logic analyzer mode. */
113 static uint8_t logic_mode_start[] = {
114 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
115 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
118 static const char *firmware_files[] = {
119 "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */
120 "asix-sigma-100.fw", /* 100 MHz */
121 "asix-sigma-200.fw", /* 200 MHz */
122 "asix-sigma-50sync.fw", /* Synchronous clock from pin */
123 "asix-sigma-phasor.fw", /* Frequency counter */
126 static int hw_dev_acquisition_stop(int dev_index, void *cb_data);
128 static int sigma_read(void *buf, size_t size, struct context *ctx)
132 ret = ftdi_read_data(&ctx->ftdic, (unsigned char *)buf, size);
134 sr_err("sigma: ftdi_read_data failed: %s",
135 ftdi_get_error_string(&ctx->ftdic));
141 static int sigma_write(void *buf, size_t size, struct context *ctx)
145 ret = ftdi_write_data(&ctx->ftdic, (unsigned char *)buf, size);
147 sr_err("sigma: ftdi_write_data failed: %s",
148 ftdi_get_error_string(&ctx->ftdic));
149 } else if ((size_t) ret != size) {
150 sr_err("sigma: ftdi_write_data did not complete write.");
156 static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
160 uint8_t buf[len + 2];
163 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
164 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
166 for (i = 0; i < len; ++i) {
167 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
168 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
171 return sigma_write(buf, idx, ctx);
174 static int sigma_set_register(uint8_t reg, uint8_t value, struct context *ctx)
176 return sigma_write_register(reg, &value, 1, ctx);
179 static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
184 buf[0] = REG_ADDR_LOW | (reg & 0xf);
185 buf[1] = REG_ADDR_HIGH | (reg >> 4);
186 buf[2] = REG_READ_ADDR;
188 sigma_write(buf, sizeof(buf), ctx);
190 return sigma_read(data, len, ctx);
193 static uint8_t sigma_get_register(uint8_t reg, struct context *ctx)
197 if (1 != sigma_read_register(reg, &value, 1, ctx)) {
198 sr_err("sigma: sigma_get_register: 1 byte expected");
205 static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
209 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
211 REG_READ_ADDR | NEXT_REG,
212 REG_READ_ADDR | NEXT_REG,
213 REG_READ_ADDR | NEXT_REG,
214 REG_READ_ADDR | NEXT_REG,
215 REG_READ_ADDR | NEXT_REG,
216 REG_READ_ADDR | NEXT_REG,
220 sigma_write(buf, sizeof(buf), ctx);
222 sigma_read(result, sizeof(result), ctx);
224 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
225 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
227 /* Not really sure why this must be done, but according to spec. */
228 if ((--*stoppos & 0x1ff) == 0x1ff)
231 if ((*--triggerpos & 0x1ff) == 0x1ff)
237 static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
238 uint8_t *data, struct context *ctx)
244 /* Send the startchunk. Index start with 1. */
245 buf[0] = startchunk >> 8;
246 buf[1] = startchunk & 0xff;
247 sigma_write_register(WRITE_MEMROW, buf, 2, ctx);
250 buf[idx++] = REG_DRAM_BLOCK;
251 buf[idx++] = REG_DRAM_WAIT_ACK;
253 for (i = 0; i < numchunks; ++i) {
254 /* Alternate bit to copy from DRAM to cache. */
255 if (i != (numchunks - 1))
256 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
258 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
260 if (i != (numchunks - 1))
261 buf[idx++] = REG_DRAM_WAIT_ACK;
264 sigma_write(buf, idx, ctx);
266 return sigma_read(data, numchunks * CHUNK_SIZE, ctx);
269 /* Upload trigger look-up tables to Sigma. */
270 static int sigma_write_trigger_lut(struct triggerlut *lut, struct context *ctx)
276 /* Transpose the table and send to Sigma. */
277 for (i = 0; i < 16; ++i) {
282 if (lut->m2d[0] & bit)
284 if (lut->m2d[1] & bit)
286 if (lut->m2d[2] & bit)
288 if (lut->m2d[3] & bit)
298 if (lut->m0d[0] & bit)
300 if (lut->m0d[1] & bit)
302 if (lut->m0d[2] & bit)
304 if (lut->m0d[3] & bit)
307 if (lut->m1d[0] & bit)
309 if (lut->m1d[1] & bit)
311 if (lut->m1d[2] & bit)
313 if (lut->m1d[3] & bit)
316 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
318 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, ctx);
321 /* Send the parameters */
322 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
323 sizeof(lut->params), ctx);
328 /* Generate the bitbang stream for programming the FPGA. */
329 static int bin2bitbang(const char *filename,
330 unsigned char **buf, size_t *buf_size)
333 unsigned long file_size;
334 unsigned long offset = 0;
337 unsigned long fwsize = 0;
338 const int buffer_size = 65536;
341 uint32_t imm = 0x3f6df2ab;
343 f = g_fopen(filename, "rb");
345 sr_err("sigma: g_fopen(\"%s\", \"rb\")", filename);
349 if (-1 == fseek(f, 0, SEEK_END)) {
350 sr_err("sigma: fseek on %s failed", filename);
355 file_size = ftell(f);
357 fseek(f, 0, SEEK_SET);
359 if (!(firmware = g_try_malloc(buffer_size))) {
360 sr_err("sigma: %s: firmware malloc failed", __func__);
362 return SR_ERR_MALLOC;
365 while ((c = getc(f)) != EOF) {
366 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
367 firmware[fwsize++] = c ^ imm;
371 if(fwsize != file_size) {
372 sr_err("sigma: %s: Error reading firmware", filename);
378 *buf_size = fwsize * 2 * 8;
380 *buf = p = (unsigned char *)g_try_malloc(*buf_size);
382 sr_err("sigma: %s: buf/p malloc failed", __func__);
384 return SR_ERR_MALLOC;
387 for (i = 0; i < fwsize; ++i) {
388 for (bit = 7; bit >= 0; --bit) {
389 v = firmware[i] & 1 << bit ? 0x40 : 0x00;
390 p[offset++] = v | 0x01;
397 if (offset != *buf_size) {
399 sr_err("sigma: Error reading firmware %s "
400 "offset=%ld, file_size=%ld, buf_size=%zd.",
401 filename, offset, file_size, *buf_size);
409 static void clear_instances(void)
412 struct sr_dev_inst *sdi;
415 /* Properly close all devices. */
416 for (l = adi->instances; l; l = l->next) {
417 if (!(sdi = l->data)) {
418 /* Log error, but continue cleaning up the rest. */
419 sr_err("sigma: %s: sdi was NULL, continuing", __func__);
424 ftdi_free(&ctx->ftdic);
427 sr_dev_inst_free(sdi);
429 g_slist_free(adi->instances);
430 adi->instances = NULL;
434 static int hw_init(void)
442 static GSList *hw_scan(GSList *options)
444 struct sr_dev_inst *sdi;
447 struct ftdi_device_list *devlist;
455 if (!(ctx = g_try_malloc(sizeof(struct context)))) {
456 sr_err("sigma: %s: ctx malloc failed", __func__);
460 ftdi_init(&ctx->ftdic);
462 /* Look for SIGMAs. */
464 if (ftdi_usb_find_all(&ctx->ftdic, &devlist,
465 USB_VENDOR, USB_PRODUCT) <= 0)
468 /* Make sure it's a version 1 or 2 SIGMA. */
469 ftdi_usb_get_strings(&ctx->ftdic, devlist->dev, NULL, 0, NULL, 0,
470 serial_txt, sizeof(serial_txt));
471 sscanf(serial_txt, "%x", &serial);
473 if (serial < 0xa6010000 || serial > 0xa602ffff) {
474 sr_err("sigma: Only SIGMA and SIGMA2 are supported "
475 "in this version of sigrok.");
479 sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
481 ctx->cur_samplerate = 0;
484 ctx->cur_firmware = -1;
486 ctx->samples_per_event = 0;
487 ctx->capture_ratio = 50;
488 ctx->use_triggers = 0;
490 /* Register SIGMA device. */
491 if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME,
492 USB_MODEL_NAME, USB_MODEL_VERSION))) {
493 sr_err("sigma: %s: sdi was NULL", __func__);
496 devices = g_slist_append(devices, sdi);
497 adi->instances = g_slist_append(adi->instances, sdi);
500 /* We will open the device again when we need it. */
501 ftdi_list_free(&devlist);
506 ftdi_free(&ctx->ftdic);
511 static int upload_firmware(int firmware_idx, struct context *ctx)
517 unsigned char result[32];
518 char firmware_path[128];
520 /* Make sure it's an ASIX SIGMA. */
521 if ((ret = ftdi_usb_open_desc(&ctx->ftdic,
522 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
523 sr_err("sigma: ftdi_usb_open failed: %s",
524 ftdi_get_error_string(&ctx->ftdic));
528 if ((ret = ftdi_set_bitmode(&ctx->ftdic, 0xdf, BITMODE_BITBANG)) < 0) {
529 sr_err("sigma: ftdi_set_bitmode failed: %s",
530 ftdi_get_error_string(&ctx->ftdic));
534 /* Four times the speed of sigmalogan - Works well. */
535 if ((ret = ftdi_set_baudrate(&ctx->ftdic, 750000)) < 0) {
536 sr_err("sigma: ftdi_set_baudrate failed: %s",
537 ftdi_get_error_string(&ctx->ftdic));
541 /* Force the FPGA to reboot. */
542 sigma_write(suicide, sizeof(suicide), ctx);
543 sigma_write(suicide, sizeof(suicide), ctx);
544 sigma_write(suicide, sizeof(suicide), ctx);
545 sigma_write(suicide, sizeof(suicide), ctx);
547 /* Prepare to upload firmware (FPGA specific). */
548 sigma_write(init, sizeof(init), ctx);
550 ftdi_usb_purge_buffers(&ctx->ftdic);
552 /* Wait until the FPGA asserts INIT_B. */
554 ret = sigma_read(result, 1, ctx);
555 if (result[0] & 0x20)
559 /* Prepare firmware. */
560 snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR,
561 firmware_files[firmware_idx]);
563 if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) {
564 sr_err("sigma: An error occured while reading the firmware: %s",
569 /* Upload firmare. */
570 sr_info("sigma: Uploading firmware %s", firmware_files[firmware_idx]);
571 sigma_write(buf, buf_size, ctx);
575 if ((ret = ftdi_set_bitmode(&ctx->ftdic, 0x00, BITMODE_RESET)) < 0) {
576 sr_err("sigma: ftdi_set_bitmode failed: %s",
577 ftdi_get_error_string(&ctx->ftdic));
581 ftdi_usb_purge_buffers(&ctx->ftdic);
583 /* Discard garbage. */
584 while (1 == sigma_read(&pins, 1, ctx))
587 /* Initialize the logic analyzer mode. */
588 sigma_write(logic_mode_start, sizeof(logic_mode_start), ctx);
590 /* Expect a 3 byte reply. */
591 ret = sigma_read(result, 3, ctx);
593 result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
594 sr_err("sigma: Configuration failed. Invalid reply received.");
598 ctx->cur_firmware = firmware_idx;
600 sr_info("sigma: Firmware uploaded");
605 static int hw_dev_open(int dev_index)
607 struct sr_dev_inst *sdi;
611 if (!(sdi = sr_dev_inst_get(adi->instances, dev_index)))
616 /* Make sure it's an ASIX SIGMA. */
617 if ((ret = ftdi_usb_open_desc(&ctx->ftdic,
618 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
620 sr_err("sigma: ftdi_usb_open failed: %s",
621 ftdi_get_error_string(&ctx->ftdic));
626 sdi->status = SR_ST_ACTIVE;
631 static int set_samplerate(struct sr_dev_inst *sdi, uint64_t samplerate)
634 struct context *ctx = sdi->priv;
636 for (i = 0; supported_samplerates[i]; i++) {
637 if (supported_samplerates[i] == samplerate)
640 if (supported_samplerates[i] == 0)
641 return SR_ERR_SAMPLERATE;
643 if (samplerate <= SR_MHZ(50)) {
644 ret = upload_firmware(0, ctx);
645 ctx->num_probes = 16;
647 if (samplerate == SR_MHZ(100)) {
648 ret = upload_firmware(1, ctx);
651 else if (samplerate == SR_MHZ(200)) {
652 ret = upload_firmware(2, ctx);
656 ctx->cur_samplerate = samplerate;
657 ctx->period_ps = 1000000000000 / samplerate;
658 ctx->samples_per_event = 16 / ctx->num_probes;
659 ctx->state.state = SIGMA_IDLE;
665 * In 100 and 200 MHz mode, only a single pin rising/falling can be
666 * set as trigger. In other modes, two rising/falling triggers can be set,
667 * in addition to value/mask trigger for any number of probes.
669 * The Sigma supports complex triggers using boolean expressions, but this
670 * has not been implemented yet.
672 static int configure_probes(struct sr_dev_inst *sdi, const GSList *probes)
674 struct context *ctx = sdi->priv;
675 const struct sr_probe *probe;
680 memset(&ctx->trigger, 0, sizeof(struct sigma_trigger));
682 for (l = probes; l; l = l->next) {
683 probe = (struct sr_probe *)l->data;
684 probebit = 1 << (probe->index - 1);
686 if (!probe->enabled || !probe->trigger)
689 if (ctx->cur_samplerate >= SR_MHZ(100)) {
690 /* Fast trigger support. */
692 sr_err("sigma: ASIX SIGMA only supports a single "
693 "pin trigger in 100 and 200MHz mode.");
696 if (probe->trigger[0] == 'f')
697 ctx->trigger.fallingmask |= probebit;
698 else if (probe->trigger[0] == 'r')
699 ctx->trigger.risingmask |= probebit;
701 sr_err("sigma: ASIX SIGMA only supports "
702 "rising/falling trigger in 100 "
709 /* Simple trigger support (event). */
710 if (probe->trigger[0] == '1') {
711 ctx->trigger.simplevalue |= probebit;
712 ctx->trigger.simplemask |= probebit;
714 else if (probe->trigger[0] == '0') {
715 ctx->trigger.simplevalue &= ~probebit;
716 ctx->trigger.simplemask |= probebit;
718 else if (probe->trigger[0] == 'f') {
719 ctx->trigger.fallingmask |= probebit;
722 else if (probe->trigger[0] == 'r') {
723 ctx->trigger.risingmask |= probebit;
728 * Actually, Sigma supports 2 rising/falling triggers,
729 * but they are ORed and the current trigger syntax
730 * does not permit ORed triggers.
732 if (trigger_set > 1) {
733 sr_err("sigma: ASIX SIGMA only supports 1 "
734 "rising/falling triggers.");
740 ctx->use_triggers = 1;
746 static int hw_dev_close(int dev_index)
748 struct sr_dev_inst *sdi;
751 if (!(sdi = sr_dev_inst_get(adi->instances, dev_index))) {
752 sr_err("sigma: %s: sdi was NULL", __func__);
756 if (!(ctx = sdi->priv)) {
757 sr_err("sigma: %s: sdi->priv was NULL", __func__);
762 if (sdi->status == SR_ST_ACTIVE)
763 ftdi_usb_close(&ctx->ftdic);
765 sdi->status = SR_ST_INACTIVE;
770 static int hw_cleanup(void)
778 static const void *hw_dev_info_get(int dev_index, int dev_info_id)
780 struct sr_dev_inst *sdi;
782 const void *info = NULL;
784 if (!(sdi = sr_dev_inst_get(adi->instances, dev_index))) {
785 sr_err("sigma: %s: sdi was NULL", __func__);
791 switch (dev_info_id) {
795 case SR_DI_NUM_PROBES:
796 info = GINT_TO_POINTER(NUM_PROBES);
798 case SR_DI_PROBE_NAMES:
801 case SR_DI_SAMPLERATES:
804 case SR_DI_TRIGGER_TYPES:
805 info = (char *)TRIGGER_TYPES;
807 case SR_DI_CUR_SAMPLERATE:
808 info = &ctx->cur_samplerate;
815 static int hw_dev_status_get(int dev_index)
817 struct sr_dev_inst *sdi;
819 sdi = sr_dev_inst_get(adi->instances, dev_index);
823 return SR_ST_NOT_FOUND;
826 static const int *hw_hwcap_get_all(void)
831 static int hw_dev_config_set(int dev_index, int hwcap, const void *value)
833 struct sr_dev_inst *sdi;
837 if (!(sdi = sr_dev_inst_get(adi->instances, dev_index)))
842 if (hwcap == SR_HWCAP_SAMPLERATE) {
843 ret = set_samplerate(sdi, *(const uint64_t *)value);
844 } else if (hwcap == SR_HWCAP_PROBECONFIG) {
845 ret = configure_probes(sdi, value);
846 } else if (hwcap == SR_HWCAP_LIMIT_MSEC) {
847 ctx->limit_msec = *(const uint64_t *)value;
848 if (ctx->limit_msec > 0)
852 } else if (hwcap == SR_HWCAP_CAPTURE_RATIO) {
853 ctx->capture_ratio = *(const uint64_t *)value;
854 if (ctx->capture_ratio < 0 || ctx->capture_ratio > 100)
865 /* Software trigger to determine exact trigger position. */
866 static int get_trigger_offset(uint16_t *samples, uint16_t last_sample,
867 struct sigma_trigger *t)
871 for (i = 0; i < 8; ++i) {
873 last_sample = samples[i-1];
875 /* Simple triggers. */
876 if ((samples[i] & t->simplemask) != t->simplevalue)
880 if ((last_sample & t->risingmask) != 0 || (samples[i] &
881 t->risingmask) != t->risingmask)
885 if ((last_sample & t->fallingmask) != t->fallingmask ||
886 (samples[i] & t->fallingmask) != 0)
892 /* If we did not match, return original trigger pos. */
897 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
898 * Each event is 20ns apart, and can contain multiple samples.
900 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
901 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
902 * For 50 MHz and below, events contain one sample for each channel,
903 * spread 20 ns apart.
905 static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
906 uint16_t *lastsample, int triggerpos,
907 uint16_t limit_chunk, void *cb_data)
909 struct sr_dev_inst *sdi = cb_data;
910 struct context *ctx = sdi->priv;
912 uint16_t samples[65536 * ctx->samples_per_event];
913 struct sr_datafeed_packet packet;
914 struct sr_datafeed_logic logic;
915 int i, j, k, l, numpad, tosend;
916 size_t n = 0, sent = 0;
917 int clustersize = EVENTS_PER_CLUSTER * ctx->samples_per_event;
922 /* Check if trigger is in this chunk. */
923 if (triggerpos != -1) {
924 if (ctx->cur_samplerate <= SR_MHZ(50))
925 triggerpos -= EVENTS_PER_CLUSTER - 1;
930 /* Find in which cluster the trigger occured. */
931 triggerts = triggerpos / 7;
935 for (i = 0; i < 64; ++i) {
936 ts = *(uint16_t *) &buf[i * 16];
937 tsdiff = ts - *lastts;
940 /* Decode partial chunk. */
941 if (limit_chunk && ts > limit_chunk)
944 /* Pad last sample up to current point. */
945 numpad = tsdiff * ctx->samples_per_event - clustersize;
947 for (j = 0; j < numpad; ++j)
948 samples[j] = *lastsample;
953 /* Send samples between previous and this timestamp to sigrok. */
956 tosend = MIN(2048, n - sent);
958 packet.type = SR_DF_LOGIC;
959 packet.payload = &logic;
960 logic.length = tosend * sizeof(uint16_t);
962 logic.data = samples + sent;
963 sr_session_send(ctx->session_dev_id, &packet);
969 event = (uint16_t *) &buf[i * 16 + 2];
972 /* For each event in cluster. */
973 for (j = 0; j < 7; ++j) {
975 /* For each sample in event. */
976 for (k = 0; k < ctx->samples_per_event; ++k) {
979 /* For each probe. */
980 for (l = 0; l < ctx->num_probes; ++l)
981 cur_sample |= (!!(event[j] & (1 << (l *
982 ctx->samples_per_event + k)))) << l;
984 samples[n++] = cur_sample;
988 /* Send data up to trigger point (if triggered). */
990 if (i == triggerts) {
992 * Trigger is not always accurate to sample because of
993 * pipeline delay. However, it always triggers before
994 * the actual event. We therefore look at the next
995 * samples to pinpoint the exact position of the trigger.
997 tosend = get_trigger_offset(samples, *lastsample,
1001 packet.type = SR_DF_LOGIC;
1002 packet.payload = &logic;
1003 logic.length = tosend * sizeof(uint16_t);
1005 logic.data = samples;
1006 sr_session_send(ctx->session_dev_id, &packet);
1011 /* Only send trigger if explicitly enabled. */
1012 if (ctx->use_triggers) {
1013 packet.type = SR_DF_TRIGGER;
1014 sr_session_send(ctx->session_dev_id, &packet);
1018 /* Send rest of the chunk to sigrok. */
1022 packet.type = SR_DF_LOGIC;
1023 packet.payload = &logic;
1024 logic.length = tosend * sizeof(uint16_t);
1026 logic.data = samples + sent;
1027 sr_session_send(ctx->session_dev_id, &packet);
1030 *lastsample = samples[n - 1];
1036 static int receive_data(int fd, int revents, void *cb_data)
1038 struct sr_dev_inst *sdi = cb_data;
1039 struct context *ctx = sdi->priv;
1040 struct sr_datafeed_packet packet;
1041 const int chunks_per_read = 32;
1042 unsigned char buf[chunks_per_read * CHUNK_SIZE];
1043 int bufsz, numchunks, i, newchunks;
1044 uint64_t running_msec;
1047 /* Avoid compiler warnings. */
1051 /* Get the current position. */
1052 sigma_read_pos(&ctx->state.stoppos, &ctx->state.triggerpos, ctx);
1054 numchunks = (ctx->state.stoppos + 511) / 512;
1056 if (ctx->state.state == SIGMA_IDLE)
1059 if (ctx->state.state == SIGMA_CAPTURE) {
1060 /* Check if the timer has expired, or memory is full. */
1061 gettimeofday(&tv, 0);
1062 running_msec = (tv.tv_sec - ctx->start_tv.tv_sec) * 1000 +
1063 (tv.tv_usec - ctx->start_tv.tv_usec) / 1000;
1065 if (running_msec < ctx->limit_msec && numchunks < 32767)
1066 return TRUE; /* While capturing... */
1068 hw_dev_acquisition_stop(sdi->index, sdi);
1070 } else if (ctx->state.state == SIGMA_DOWNLOAD) {
1071 if (ctx->state.chunks_downloaded >= numchunks) {
1072 /* End of samples. */
1073 packet.type = SR_DF_END;
1074 sr_session_send(ctx->session_dev_id, &packet);
1076 ctx->state.state = SIGMA_IDLE;
1081 newchunks = MIN(chunks_per_read,
1082 numchunks - ctx->state.chunks_downloaded);
1084 sr_info("sigma: Downloading sample data: %.0f %%",
1085 100.0 * ctx->state.chunks_downloaded / numchunks);
1087 bufsz = sigma_read_dram(ctx->state.chunks_downloaded,
1088 newchunks, buf, ctx);
1089 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1092 /* Find first ts. */
1093 if (ctx->state.chunks_downloaded == 0) {
1094 ctx->state.lastts = *(uint16_t *) buf - 1;
1095 ctx->state.lastsample = 0;
1098 /* Decode chunks and send them to sigrok. */
1099 for (i = 0; i < newchunks; ++i) {
1100 int limit_chunk = 0;
1102 /* The last chunk may potentially be only in part. */
1103 if (ctx->state.chunks_downloaded == numchunks - 1) {
1104 /* Find the last valid timestamp */
1105 limit_chunk = ctx->state.stoppos % 512 + ctx->state.lastts;
1108 if (ctx->state.chunks_downloaded + i == ctx->state.triggerchunk)
1109 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1111 &ctx->state.lastsample,
1112 ctx->state.triggerpos & 0x1ff,
1115 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1117 &ctx->state.lastsample,
1118 -1, limit_chunk, sdi);
1120 ++ctx->state.chunks_downloaded;
1127 /* Build a LUT entry used by the trigger functions. */
1128 static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1132 /* For each quad probe. */
1133 for (i = 0; i < 4; ++i) {
1136 /* For each bit in LUT. */
1137 for (j = 0; j < 16; ++j)
1139 /* For each probe in quad. */
1140 for (k = 0; k < 4; ++k) {
1141 bit = 1 << (i * 4 + k);
1143 /* Set bit in entry */
1145 ((!(value & bit)) !=
1147 entry[i] &= ~(1 << j);
1152 /* Add a logical function to LUT mask. */
1153 static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1154 int index, int neg, uint16_t *mask)
1157 int x[2][2], tmp, a, b, aset, bset, rset;
1159 memset(x, 0, 4 * sizeof(int));
1161 /* Trigger detect condition. */
1191 case OP_NOTRISEFALL:
1197 /* Transpose if neg is set. */
1199 for (i = 0; i < 2; ++i) {
1200 for (j = 0; j < 2; ++j) {
1202 x[i][j] = x[1-i][1-j];
1208 /* Update mask with function. */
1209 for (i = 0; i < 16; ++i) {
1210 a = (i >> (2 * index + 0)) & 1;
1211 b = (i >> (2 * index + 1)) & 1;
1213 aset = (*mask >> i) & 1;
1216 if (func == FUNC_AND || func == FUNC_NAND)
1218 else if (func == FUNC_OR || func == FUNC_NOR)
1220 else if (func == FUNC_XOR || func == FUNC_NXOR)
1223 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1234 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1235 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1236 * set at any time, but a full mask and value can be set (0/1).
1238 static int build_basic_trigger(struct triggerlut *lut, struct context *ctx)
1241 uint16_t masks[2] = { 0, 0 };
1243 memset(lut, 0, sizeof(struct triggerlut));
1245 /* Contant for simple triggers. */
1248 /* Value/mask trigger support. */
1249 build_lut_entry(ctx->trigger.simplevalue, ctx->trigger.simplemask,
1252 /* Rise/fall trigger support. */
1253 for (i = 0, j = 0; i < 16; ++i) {
1254 if (ctx->trigger.risingmask & (1 << i) ||
1255 ctx->trigger.fallingmask & (1 << i))
1256 masks[j++] = 1 << i;
1259 build_lut_entry(masks[0], masks[0], lut->m0d);
1260 build_lut_entry(masks[1], masks[1], lut->m1d);
1262 /* Add glue logic */
1263 if (masks[0] || masks[1]) {
1264 /* Transition trigger. */
1265 if (masks[0] & ctx->trigger.risingmask)
1266 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1267 if (masks[0] & ctx->trigger.fallingmask)
1268 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1269 if (masks[1] & ctx->trigger.risingmask)
1270 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1271 if (masks[1] & ctx->trigger.fallingmask)
1272 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1274 /* Only value/mask trigger. */
1278 /* Triggertype: event. */
1279 lut->params.selres = 3;
1284 static int hw_dev_acquisition_start(int dev_index, void *cb_data)
1286 struct sr_dev_inst *sdi;
1287 struct context *ctx;
1288 struct sr_datafeed_packet *packet;
1289 struct sr_datafeed_header *header;
1290 struct sr_datafeed_meta_logic meta;
1291 struct clockselect_50 clockselect;
1292 int frac, triggerpin, ret;
1293 uint8_t triggerselect;
1294 struct triggerinout triggerinout_conf;
1295 struct triggerlut lut;
1297 if (!(sdi = sr_dev_inst_get(adi->instances, dev_index)))
1302 /* If the samplerate has not been set, default to 200 kHz. */
1303 if (ctx->cur_firmware == -1) {
1304 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1308 /* Enter trigger programming mode. */
1309 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, ctx);
1311 /* 100 and 200 MHz mode. */
1312 if (ctx->cur_samplerate >= SR_MHZ(100)) {
1313 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, ctx);
1315 /* Find which pin to trigger on from mask. */
1316 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1317 if ((ctx->trigger.risingmask | ctx->trigger.fallingmask) &
1321 /* Set trigger pin and light LED on trigger. */
1322 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1324 /* Default rising edge. */
1325 if (ctx->trigger.fallingmask)
1326 triggerselect |= 1 << 3;
1328 /* All other modes. */
1329 } else if (ctx->cur_samplerate <= SR_MHZ(50)) {
1330 build_basic_trigger(&lut, ctx);
1332 sigma_write_trigger_lut(&lut, ctx);
1334 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1337 /* Setup trigger in and out pins to default values. */
1338 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1339 triggerinout_conf.trgout_bytrigger = 1;
1340 triggerinout_conf.trgout_enable = 1;
1342 sigma_write_register(WRITE_TRIGGER_OPTION,
1343 (uint8_t *) &triggerinout_conf,
1344 sizeof(struct triggerinout), ctx);
1346 /* Go back to normal mode. */
1347 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, ctx);
1349 /* Set clock select register. */
1350 if (ctx->cur_samplerate == SR_MHZ(200))
1351 /* Enable 4 probes. */
1352 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, ctx);
1353 else if (ctx->cur_samplerate == SR_MHZ(100))
1354 /* Enable 8 probes. */
1355 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, ctx);
1358 * 50 MHz mode (or fraction thereof). Any fraction down to
1359 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1361 frac = SR_MHZ(50) / ctx->cur_samplerate - 1;
1363 clockselect.async = 0;
1364 clockselect.fraction = frac;
1365 clockselect.disabled_probes = 0;
1367 sigma_write_register(WRITE_CLOCK_SELECT,
1368 (uint8_t *) &clockselect,
1369 sizeof(clockselect), ctx);
1372 /* Setup maximum post trigger time. */
1373 sigma_set_register(WRITE_POST_TRIGGER,
1374 (ctx->capture_ratio * 255) / 100, ctx);
1376 /* Start acqusition. */
1377 gettimeofday(&ctx->start_tv, 0);
1378 sigma_set_register(WRITE_MODE, 0x0d, ctx);
1380 ctx->session_dev_id = cb_data;
1382 if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) {
1383 sr_err("sigma: %s: packet malloc failed.", __func__);
1384 return SR_ERR_MALLOC;
1387 if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) {
1388 sr_err("sigma: %s: header malloc failed.", __func__);
1389 return SR_ERR_MALLOC;
1392 /* Send header packet to the session bus. */
1393 packet->type = SR_DF_HEADER;
1394 packet->payload = header;
1395 header->feed_version = 1;
1396 gettimeofday(&header->starttime, NULL);
1397 sr_session_send(ctx->session_dev_id, packet);
1399 /* Send metadata about the SR_DF_LOGIC packets to come. */
1400 packet->type = SR_DF_META_LOGIC;
1401 packet->payload = &meta;
1402 meta.samplerate = ctx->cur_samplerate;
1403 meta.num_probes = ctx->num_probes;
1404 sr_session_send(ctx->session_dev_id, packet);
1406 /* Add capture source. */
1407 sr_source_add(0, G_IO_IN, 10, receive_data, sdi);
1412 ctx->state.state = SIGMA_CAPTURE;
1417 static int hw_dev_acquisition_stop(int dev_index, void *cb_data)
1419 struct sr_dev_inst *sdi;
1420 struct context *ctx;
1423 /* Avoid compiler warnings. */
1426 if (!(sdi = sr_dev_inst_get(adi->instances, dev_index))) {
1427 sr_err("sigma: %s: sdi was NULL", __func__);
1431 if (!(ctx = sdi->priv)) {
1432 sr_err("sigma: %s: sdi->priv was NULL", __func__);
1436 /* Stop acquisition. */
1437 sigma_set_register(WRITE_MODE, 0x11, ctx);
1439 /* Set SDRAM Read Enable. */
1440 sigma_set_register(WRITE_MODE, 0x02, ctx);
1442 /* Get the current position. */
1443 sigma_read_pos(&ctx->state.stoppos, &ctx->state.triggerpos, ctx);
1445 /* Check if trigger has fired. */
1446 modestatus = sigma_get_register(READ_MODE, ctx);
1447 if (modestatus & 0x20)
1448 ctx->state.triggerchunk = ctx->state.triggerpos / 512;
1450 ctx->state.triggerchunk = -1;
1452 ctx->state.chunks_downloaded = 0;
1454 ctx->state.state = SIGMA_DOWNLOAD;
1459 SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
1460 .name = "asix-sigma",
1461 .longname = "ASIX SIGMA/SIGMA2",
1464 .cleanup = hw_cleanup,
1466 .dev_open = hw_dev_open,
1467 .dev_close = hw_dev_close,
1468 .dev_info_get = hw_dev_info_get,
1469 .dev_status_get = hw_dev_status_get,
1470 // .hwcap_get_all = hw_hwcap_get_all,
1471 .dev_config_set = hw_dev_config_set,
1472 .dev_acquisition_start = hw_dev_acquisition_start,
1473 .dev_acquisition_stop = hw_dev_acquisition_stop,