2 * This file is part of the sigrok project.
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
27 #include <glib/gstdio.h>
30 #include "libsigrok.h"
31 #include "libsigrok-internal.h"
32 #include "asix-sigma.h"
34 #define USB_VENDOR 0xa600
35 #define USB_PRODUCT 0xa000
36 #define USB_DESCRIPTION "ASIX SIGMA"
37 #define USB_VENDOR_NAME "ASIX"
38 #define USB_MODEL_NAME "SIGMA"
39 #define USB_MODEL_VERSION ""
40 #define TRIGGER_TYPES "rf10"
43 SR_PRIV struct sr_dev_driver asix_sigma_driver_info;
44 static struct sr_dev_driver *adi = &asix_sigma_driver_info;
46 static const uint64_t supported_samplerates[] = {
61 * Probe numbers seem to go from 1-16, according to this image:
62 * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
63 * (the cable has two additional GND pins, and a TI and TO pin)
65 static const char *probe_names[NUM_PROBES + 1] = {
85 static const struct sr_samplerates samplerates = {
89 supported_samplerates,
92 static const int hwcaps[] = {
93 SR_HWCAP_LOGIC_ANALYZER,
95 SR_HWCAP_CAPTURE_RATIO,
101 /* Force the FPGA to reboot. */
102 static uint8_t suicide[] = {
103 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
106 /* Prepare to upload firmware (FPGA specific). */
107 static uint8_t init[] = {
108 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
111 /* Initialize the logic analyzer mode. */
112 static uint8_t logic_mode_start[] = {
113 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
114 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
117 static const char *firmware_files[] = {
118 "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */
119 "asix-sigma-100.fw", /* 100 MHz */
120 "asix-sigma-200.fw", /* 200 MHz */
121 "asix-sigma-50sync.fw", /* Synchronous clock from pin */
122 "asix-sigma-phasor.fw", /* Frequency counter */
125 static int hw_dev_acquisition_stop(const struct sr_dev_inst *sdi,
128 static int sigma_read(void *buf, size_t size, struct dev_context *devc)
132 ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size);
134 sr_err("sigma: ftdi_read_data failed: %s",
135 ftdi_get_error_string(&devc->ftdic));
141 static int sigma_write(void *buf, size_t size, struct dev_context *devc)
145 ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size);
147 sr_err("sigma: ftdi_write_data failed: %s",
148 ftdi_get_error_string(&devc->ftdic));
149 } else if ((size_t) ret != size) {
150 sr_err("sigma: ftdi_write_data did not complete write.");
156 static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
157 struct dev_context *devc)
160 uint8_t buf[len + 2];
163 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
164 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
166 for (i = 0; i < len; ++i) {
167 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
168 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
171 return sigma_write(buf, idx, devc);
174 static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc)
176 return sigma_write_register(reg, &value, 1, devc);
179 static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
180 struct dev_context *devc)
184 buf[0] = REG_ADDR_LOW | (reg & 0xf);
185 buf[1] = REG_ADDR_HIGH | (reg >> 4);
186 buf[2] = REG_READ_ADDR;
188 sigma_write(buf, sizeof(buf), devc);
190 return sigma_read(data, len, devc);
193 static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc)
197 if (1 != sigma_read_register(reg, &value, 1, devc)) {
198 sr_err("sigma: sigma_get_register: 1 byte expected");
205 static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
206 struct dev_context *devc)
209 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
211 REG_READ_ADDR | NEXT_REG,
212 REG_READ_ADDR | NEXT_REG,
213 REG_READ_ADDR | NEXT_REG,
214 REG_READ_ADDR | NEXT_REG,
215 REG_READ_ADDR | NEXT_REG,
216 REG_READ_ADDR | NEXT_REG,
220 sigma_write(buf, sizeof(buf), devc);
222 sigma_read(result, sizeof(result), devc);
224 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
225 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
227 /* Not really sure why this must be done, but according to spec. */
228 if ((--*stoppos & 0x1ff) == 0x1ff)
231 if ((*--triggerpos & 0x1ff) == 0x1ff)
237 static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
238 uint8_t *data, struct dev_context *devc)
244 /* Send the startchunk. Index start with 1. */
245 buf[0] = startchunk >> 8;
246 buf[1] = startchunk & 0xff;
247 sigma_write_register(WRITE_MEMROW, buf, 2, devc);
250 buf[idx++] = REG_DRAM_BLOCK;
251 buf[idx++] = REG_DRAM_WAIT_ACK;
253 for (i = 0; i < numchunks; ++i) {
254 /* Alternate bit to copy from DRAM to cache. */
255 if (i != (numchunks - 1))
256 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
258 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
260 if (i != (numchunks - 1))
261 buf[idx++] = REG_DRAM_WAIT_ACK;
264 sigma_write(buf, idx, devc);
266 return sigma_read(data, numchunks * CHUNK_SIZE, devc);
269 /* Upload trigger look-up tables to Sigma. */
270 static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc)
276 /* Transpose the table and send to Sigma. */
277 for (i = 0; i < 16; ++i) {
282 if (lut->m2d[0] & bit)
284 if (lut->m2d[1] & bit)
286 if (lut->m2d[2] & bit)
288 if (lut->m2d[3] & bit)
298 if (lut->m0d[0] & bit)
300 if (lut->m0d[1] & bit)
302 if (lut->m0d[2] & bit)
304 if (lut->m0d[3] & bit)
307 if (lut->m1d[0] & bit)
309 if (lut->m1d[1] & bit)
311 if (lut->m1d[2] & bit)
313 if (lut->m1d[3] & bit)
316 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
318 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
321 /* Send the parameters */
322 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
323 sizeof(lut->params), devc);
328 /* Generate the bitbang stream for programming the FPGA. */
329 static int bin2bitbang(const char *filename,
330 unsigned char **buf, size_t *buf_size)
333 unsigned long file_size;
334 unsigned long offset = 0;
337 unsigned long fwsize = 0;
338 const int buffer_size = 65536;
341 uint32_t imm = 0x3f6df2ab;
343 f = g_fopen(filename, "rb");
345 sr_err("sigma: g_fopen(\"%s\", \"rb\")", filename);
349 if (-1 == fseek(f, 0, SEEK_END)) {
350 sr_err("sigma: fseek on %s failed", filename);
355 file_size = ftell(f);
357 fseek(f, 0, SEEK_SET);
359 if (!(firmware = g_try_malloc(buffer_size))) {
360 sr_err("sigma: %s: firmware malloc failed", __func__);
362 return SR_ERR_MALLOC;
365 while ((c = getc(f)) != EOF) {
366 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
367 firmware[fwsize++] = c ^ imm;
371 if(fwsize != file_size) {
372 sr_err("sigma: %s: Error reading firmware", filename);
378 *buf_size = fwsize * 2 * 8;
380 *buf = p = (unsigned char *)g_try_malloc(*buf_size);
382 sr_err("sigma: %s: buf/p malloc failed", __func__);
384 return SR_ERR_MALLOC;
387 for (i = 0; i < fwsize; ++i) {
388 for (bit = 7; bit >= 0; --bit) {
389 v = firmware[i] & 1 << bit ? 0x40 : 0x00;
390 p[offset++] = v | 0x01;
397 if (offset != *buf_size) {
399 sr_err("sigma: Error reading firmware %s "
400 "offset=%ld, file_size=%ld, buf_size=%zd.",
401 filename, offset, file_size, *buf_size);
409 static void clear_instances(void)
412 struct sr_dev_inst *sdi;
413 struct drv_context *drvc;
414 struct dev_context *devc;
418 /* Properly close all devices. */
419 for (l = drvc->instances; l; l = l->next) {
420 if (!(sdi = l->data)) {
421 /* Log error, but continue cleaning up the rest. */
422 sr_err("sigma: %s: sdi was NULL, continuing", __func__);
427 ftdi_free(&devc->ftdic);
429 sr_dev_inst_free(sdi);
431 g_slist_free(drvc->instances);
432 drvc->instances = NULL;
436 static int hw_init(void)
438 struct drv_context *drvc;
440 if (!(drvc = g_try_malloc0(sizeof(struct drv_context)))) {
441 sr_err("asix-sigma: driver context malloc failed.");
449 static GSList *hw_scan(GSList *options)
451 struct sr_dev_inst *sdi;
452 struct sr_probe *probe;
453 struct drv_context *drvc;
454 struct dev_context *devc;
456 struct ftdi_device_list *devlist;
466 if (!(devc = g_try_malloc(sizeof(struct dev_context)))) {
467 sr_err("sigma: %s: devc malloc failed", __func__);
471 ftdi_init(&devc->ftdic);
473 /* Look for SIGMAs. */
475 if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist,
476 USB_VENDOR, USB_PRODUCT)) <= 0) {
478 sr_err("ftdi_usb_find_all(): %d", ret);
482 /* Make sure it's a version 1 or 2 SIGMA. */
483 ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0,
484 serial_txt, sizeof(serial_txt));
485 sscanf(serial_txt, "%x", &serial);
487 if (serial < 0xa6010000 || serial > 0xa602ffff) {
488 sr_err("sigma: Only SIGMA and SIGMA2 are supported "
489 "in this version of sigrok.");
493 sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
495 devc->cur_samplerate = 0;
497 devc->limit_msec = 0;
498 devc->cur_firmware = -1;
499 devc->num_probes = 0;
500 devc->samples_per_event = 0;
501 devc->capture_ratio = 50;
502 devc->use_triggers = 0;
504 /* Register SIGMA device. */
505 if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME,
506 USB_MODEL_NAME, USB_MODEL_VERSION))) {
507 sr_err("sigma: %s: sdi was NULL", __func__);
512 for (i = 0; probe_names[i]; i++) {
513 if (!(probe = sr_probe_new(i, SR_PROBE_ANALOG, TRUE,
516 sdi->probes = g_slist_append(sdi->probes, probe);
519 devices = g_slist_append(devices, sdi);
520 drvc->instances = g_slist_append(drvc->instances, sdi);
523 /* We will open the device again when we need it. */
524 ftdi_list_free(&devlist);
529 ftdi_deinit(&devc->ftdic);
534 static int upload_firmware(int firmware_idx, struct dev_context *devc)
540 unsigned char result[32];
541 char firmware_path[128];
543 /* Make sure it's an ASIX SIGMA. */
544 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
545 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
546 sr_err("sigma: ftdi_usb_open failed: %s",
547 ftdi_get_error_string(&devc->ftdic));
551 if ((ret = ftdi_set_bitmode(&devc->ftdic, 0xdf, BITMODE_BITBANG)) < 0) {
552 sr_err("sigma: ftdi_set_bitmode failed: %s",
553 ftdi_get_error_string(&devc->ftdic));
557 /* Four times the speed of sigmalogan - Works well. */
558 if ((ret = ftdi_set_baudrate(&devc->ftdic, 750000)) < 0) {
559 sr_err("sigma: ftdi_set_baudrate failed: %s",
560 ftdi_get_error_string(&devc->ftdic));
564 /* Force the FPGA to reboot. */
565 sigma_write(suicide, sizeof(suicide), devc);
566 sigma_write(suicide, sizeof(suicide), devc);
567 sigma_write(suicide, sizeof(suicide), devc);
568 sigma_write(suicide, sizeof(suicide), devc);
570 /* Prepare to upload firmware (FPGA specific). */
571 sigma_write(init, sizeof(init), devc);
573 ftdi_usb_purge_buffers(&devc->ftdic);
575 /* Wait until the FPGA asserts INIT_B. */
577 ret = sigma_read(result, 1, devc);
578 if (result[0] & 0x20)
582 /* Prepare firmware. */
583 snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR,
584 firmware_files[firmware_idx]);
586 if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) {
587 sr_err("sigma: An error occured while reading the firmware: %s",
592 /* Upload firmare. */
593 sr_info("sigma: Uploading firmware %s", firmware_files[firmware_idx]);
594 sigma_write(buf, buf_size, devc);
598 if ((ret = ftdi_set_bitmode(&devc->ftdic, 0x00, BITMODE_RESET)) < 0) {
599 sr_err("sigma: ftdi_set_bitmode failed: %s",
600 ftdi_get_error_string(&devc->ftdic));
604 ftdi_usb_purge_buffers(&devc->ftdic);
606 /* Discard garbage. */
607 while (1 == sigma_read(&pins, 1, devc))
610 /* Initialize the logic analyzer mode. */
611 sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
613 /* Expect a 3 byte reply. */
614 ret = sigma_read(result, 3, devc);
616 result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
617 sr_err("sigma: Configuration failed. Invalid reply received.");
621 devc->cur_firmware = firmware_idx;
623 sr_info("sigma: Firmware uploaded");
628 static int hw_dev_open(struct sr_dev_inst *sdi)
630 struct dev_context *devc;
635 /* Make sure it's an ASIX SIGMA. */
636 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
637 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
639 sr_err("sigma: ftdi_usb_open failed: %s",
640 ftdi_get_error_string(&devc->ftdic));
645 sdi->status = SR_ST_ACTIVE;
650 static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
653 struct dev_context *devc = sdi->priv;
655 for (i = 0; supported_samplerates[i]; i++) {
656 if (supported_samplerates[i] == samplerate)
659 if (supported_samplerates[i] == 0)
660 return SR_ERR_SAMPLERATE;
662 if (samplerate <= SR_MHZ(50)) {
663 ret = upload_firmware(0, devc);
664 devc->num_probes = 16;
666 if (samplerate == SR_MHZ(100)) {
667 ret = upload_firmware(1, devc);
668 devc->num_probes = 8;
670 else if (samplerate == SR_MHZ(200)) {
671 ret = upload_firmware(2, devc);
672 devc->num_probes = 4;
675 devc->cur_samplerate = samplerate;
676 devc->period_ps = 1000000000000 / samplerate;
677 devc->samples_per_event = 16 / devc->num_probes;
678 devc->state.state = SIGMA_IDLE;
684 * In 100 and 200 MHz mode, only a single pin rising/falling can be
685 * set as trigger. In other modes, two rising/falling triggers can be set,
686 * in addition to value/mask trigger for any number of probes.
688 * The Sigma supports complex triggers using boolean expressions, but this
689 * has not been implemented yet.
691 static int configure_probes(const struct sr_dev_inst *sdi)
693 struct dev_context *devc = sdi->priv;
694 const struct sr_probe *probe;
699 memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
701 for (l = sdi->probes; l; l = l->next) {
702 probe = (struct sr_probe *)l->data;
703 probebit = 1 << (probe->index);
705 if (!probe->enabled || !probe->trigger)
708 if (devc->cur_samplerate >= SR_MHZ(100)) {
709 /* Fast trigger support. */
711 sr_err("sigma: ASIX SIGMA only supports a single "
712 "pin trigger in 100 and 200MHz mode.");
715 if (probe->trigger[0] == 'f')
716 devc->trigger.fallingmask |= probebit;
717 else if (probe->trigger[0] == 'r')
718 devc->trigger.risingmask |= probebit;
720 sr_err("sigma: ASIX SIGMA only supports "
721 "rising/falling trigger in 100 "
728 /* Simple trigger support (event). */
729 if (probe->trigger[0] == '1') {
730 devc->trigger.simplevalue |= probebit;
731 devc->trigger.simplemask |= probebit;
733 else if (probe->trigger[0] == '0') {
734 devc->trigger.simplevalue &= ~probebit;
735 devc->trigger.simplemask |= probebit;
737 else if (probe->trigger[0] == 'f') {
738 devc->trigger.fallingmask |= probebit;
741 else if (probe->trigger[0] == 'r') {
742 devc->trigger.risingmask |= probebit;
747 * Actually, Sigma supports 2 rising/falling triggers,
748 * but they are ORed and the current trigger syntax
749 * does not permit ORed triggers.
751 if (trigger_set > 1) {
752 sr_err("sigma: ASIX SIGMA only supports 1 "
753 "rising/falling triggers.");
759 devc->use_triggers = 1;
765 static int hw_dev_close(struct sr_dev_inst *sdi)
767 struct dev_context *devc;
769 if (!(devc = sdi->priv)) {
770 sr_err("sigma: %s: sdi->priv was NULL", __func__);
775 if (sdi->status == SR_ST_ACTIVE)
776 ftdi_usb_close(&devc->ftdic);
778 sdi->status = SR_ST_INACTIVE;
783 static int hw_cleanup(void)
794 static int hw_info_get(int info_id, const void **data,
795 const struct sr_dev_inst *sdi)
797 struct dev_context *devc;
803 case SR_DI_NUM_PROBES:
804 *data = GINT_TO_POINTER(NUM_PROBES);
806 case SR_DI_PROBE_NAMES:
809 case SR_DI_SAMPLERATES:
810 *data = &samplerates;
812 case SR_DI_TRIGGER_TYPES:
813 *data = (char *)TRIGGER_TYPES;
815 case SR_DI_CUR_SAMPLERATE:
818 *data = &devc->cur_samplerate;
829 static int hw_dev_config_set(const struct sr_dev_inst *sdi, int hwcap,
832 struct dev_context *devc;
837 if (hwcap == SR_HWCAP_SAMPLERATE) {
838 ret = set_samplerate(sdi, *(const uint64_t *)value);
839 } else if (hwcap == SR_HWCAP_LIMIT_MSEC) {
840 devc->limit_msec = *(const uint64_t *)value;
841 if (devc->limit_msec > 0)
845 } else if (hwcap == SR_HWCAP_CAPTURE_RATIO) {
846 devc->capture_ratio = *(const uint64_t *)value;
847 if (devc->capture_ratio < 0 || devc->capture_ratio > 100)
858 /* Software trigger to determine exact trigger position. */
859 static int get_trigger_offset(uint16_t *samples, uint16_t last_sample,
860 struct sigma_trigger *t)
864 for (i = 0; i < 8; ++i) {
866 last_sample = samples[i-1];
868 /* Simple triggers. */
869 if ((samples[i] & t->simplemask) != t->simplevalue)
873 if ((last_sample & t->risingmask) != 0 || (samples[i] &
874 t->risingmask) != t->risingmask)
878 if ((last_sample & t->fallingmask) != t->fallingmask ||
879 (samples[i] & t->fallingmask) != 0)
885 /* If we did not match, return original trigger pos. */
890 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
891 * Each event is 20ns apart, and can contain multiple samples.
893 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
894 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
895 * For 50 MHz and below, events contain one sample for each channel,
896 * spread 20 ns apart.
898 static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
899 uint16_t *lastsample, int triggerpos,
900 uint16_t limit_chunk, void *cb_data)
902 struct sr_dev_inst *sdi = cb_data;
903 struct dev_context *devc = sdi->priv;
905 uint16_t samples[65536 * devc->samples_per_event];
906 struct sr_datafeed_packet packet;
907 struct sr_datafeed_logic logic;
908 int i, j, k, l, numpad, tosend;
909 size_t n = 0, sent = 0;
910 int clustersize = EVENTS_PER_CLUSTER * devc->samples_per_event;
915 /* Check if trigger is in this chunk. */
916 if (triggerpos != -1) {
917 if (devc->cur_samplerate <= SR_MHZ(50))
918 triggerpos -= EVENTS_PER_CLUSTER - 1;
923 /* Find in which cluster the trigger occured. */
924 triggerts = triggerpos / 7;
928 for (i = 0; i < 64; ++i) {
929 ts = *(uint16_t *) &buf[i * 16];
930 tsdiff = ts - *lastts;
933 /* Decode partial chunk. */
934 if (limit_chunk && ts > limit_chunk)
937 /* Pad last sample up to current point. */
938 numpad = tsdiff * devc->samples_per_event - clustersize;
940 for (j = 0; j < numpad; ++j)
941 samples[j] = *lastsample;
946 /* Send samples between previous and this timestamp to sigrok. */
949 tosend = MIN(2048, n - sent);
951 packet.type = SR_DF_LOGIC;
952 packet.payload = &logic;
953 logic.length = tosend * sizeof(uint16_t);
955 logic.data = samples + sent;
956 sr_session_send(devc->session_dev_id, &packet);
962 event = (uint16_t *) &buf[i * 16 + 2];
965 /* For each event in cluster. */
966 for (j = 0; j < 7; ++j) {
968 /* For each sample in event. */
969 for (k = 0; k < devc->samples_per_event; ++k) {
972 /* For each probe. */
973 for (l = 0; l < devc->num_probes; ++l)
974 cur_sample |= (!!(event[j] & (1 << (l *
975 devc->samples_per_event + k)))) << l;
977 samples[n++] = cur_sample;
981 /* Send data up to trigger point (if triggered). */
983 if (i == triggerts) {
985 * Trigger is not always accurate to sample because of
986 * pipeline delay. However, it always triggers before
987 * the actual event. We therefore look at the next
988 * samples to pinpoint the exact position of the trigger.
990 tosend = get_trigger_offset(samples, *lastsample,
994 packet.type = SR_DF_LOGIC;
995 packet.payload = &logic;
996 logic.length = tosend * sizeof(uint16_t);
998 logic.data = samples;
999 sr_session_send(devc->session_dev_id, &packet);
1004 /* Only send trigger if explicitly enabled. */
1005 if (devc->use_triggers) {
1006 packet.type = SR_DF_TRIGGER;
1007 sr_session_send(devc->session_dev_id, &packet);
1011 /* Send rest of the chunk to sigrok. */
1015 packet.type = SR_DF_LOGIC;
1016 packet.payload = &logic;
1017 logic.length = tosend * sizeof(uint16_t);
1019 logic.data = samples + sent;
1020 sr_session_send(devc->session_dev_id, &packet);
1023 *lastsample = samples[n - 1];
1029 static int receive_data(int fd, int revents, void *cb_data)
1031 struct sr_dev_inst *sdi = cb_data;
1032 struct dev_context *devc = sdi->priv;
1033 struct sr_datafeed_packet packet;
1034 const int chunks_per_read = 32;
1035 unsigned char buf[chunks_per_read * CHUNK_SIZE];
1036 int bufsz, numchunks, i, newchunks;
1037 uint64_t running_msec;
1040 /* Avoid compiler warnings. */
1044 /* Get the current position. */
1045 sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
1047 numchunks = (devc->state.stoppos + 511) / 512;
1049 if (devc->state.state == SIGMA_IDLE)
1052 if (devc->state.state == SIGMA_CAPTURE) {
1053 /* Check if the timer has expired, or memory is full. */
1054 gettimeofday(&tv, 0);
1055 running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 +
1056 (tv.tv_usec - devc->start_tv.tv_usec) / 1000;
1058 if (running_msec < devc->limit_msec && numchunks < 32767)
1059 return TRUE; /* While capturing... */
1061 hw_dev_acquisition_stop(sdi, sdi);
1063 } else if (devc->state.state == SIGMA_DOWNLOAD) {
1064 if (devc->state.chunks_downloaded >= numchunks) {
1065 /* End of samples. */
1066 packet.type = SR_DF_END;
1067 sr_session_send(devc->session_dev_id, &packet);
1069 devc->state.state = SIGMA_IDLE;
1074 newchunks = MIN(chunks_per_read,
1075 numchunks - devc->state.chunks_downloaded);
1077 sr_info("sigma: Downloading sample data: %.0f %%",
1078 100.0 * devc->state.chunks_downloaded / numchunks);
1080 bufsz = sigma_read_dram(devc->state.chunks_downloaded,
1081 newchunks, buf, devc);
1082 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1085 /* Find first ts. */
1086 if (devc->state.chunks_downloaded == 0) {
1087 devc->state.lastts = *(uint16_t *) buf - 1;
1088 devc->state.lastsample = 0;
1091 /* Decode chunks and send them to sigrok. */
1092 for (i = 0; i < newchunks; ++i) {
1093 int limit_chunk = 0;
1095 /* The last chunk may potentially be only in part. */
1096 if (devc->state.chunks_downloaded == numchunks - 1) {
1097 /* Find the last valid timestamp */
1098 limit_chunk = devc->state.stoppos % 512 + devc->state.lastts;
1101 if (devc->state.chunks_downloaded + i == devc->state.triggerchunk)
1102 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1103 &devc->state.lastts,
1104 &devc->state.lastsample,
1105 devc->state.triggerpos & 0x1ff,
1108 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1109 &devc->state.lastts,
1110 &devc->state.lastsample,
1111 -1, limit_chunk, sdi);
1113 ++devc->state.chunks_downloaded;
1120 /* Build a LUT entry used by the trigger functions. */
1121 static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1125 /* For each quad probe. */
1126 for (i = 0; i < 4; ++i) {
1129 /* For each bit in LUT. */
1130 for (j = 0; j < 16; ++j)
1132 /* For each probe in quad. */
1133 for (k = 0; k < 4; ++k) {
1134 bit = 1 << (i * 4 + k);
1136 /* Set bit in entry */
1138 ((!(value & bit)) !=
1140 entry[i] &= ~(1 << j);
1145 /* Add a logical function to LUT mask. */
1146 static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1147 int index, int neg, uint16_t *mask)
1150 int x[2][2], tmp, a, b, aset, bset, rset;
1152 memset(x, 0, 4 * sizeof(int));
1154 /* Trigger detect condition. */
1184 case OP_NOTRISEFALL:
1190 /* Transpose if neg is set. */
1192 for (i = 0; i < 2; ++i) {
1193 for (j = 0; j < 2; ++j) {
1195 x[i][j] = x[1-i][1-j];
1201 /* Update mask with function. */
1202 for (i = 0; i < 16; ++i) {
1203 a = (i >> (2 * index + 0)) & 1;
1204 b = (i >> (2 * index + 1)) & 1;
1206 aset = (*mask >> i) & 1;
1209 if (func == FUNC_AND || func == FUNC_NAND)
1211 else if (func == FUNC_OR || func == FUNC_NOR)
1213 else if (func == FUNC_XOR || func == FUNC_NXOR)
1216 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1227 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1228 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1229 * set at any time, but a full mask and value can be set (0/1).
1231 static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc)
1234 uint16_t masks[2] = { 0, 0 };
1236 memset(lut, 0, sizeof(struct triggerlut));
1238 /* Contant for simple triggers. */
1241 /* Value/mask trigger support. */
1242 build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask,
1245 /* Rise/fall trigger support. */
1246 for (i = 0, j = 0; i < 16; ++i) {
1247 if (devc->trigger.risingmask & (1 << i) ||
1248 devc->trigger.fallingmask & (1 << i))
1249 masks[j++] = 1 << i;
1252 build_lut_entry(masks[0], masks[0], lut->m0d);
1253 build_lut_entry(masks[1], masks[1], lut->m1d);
1255 /* Add glue logic */
1256 if (masks[0] || masks[1]) {
1257 /* Transition trigger. */
1258 if (masks[0] & devc->trigger.risingmask)
1259 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1260 if (masks[0] & devc->trigger.fallingmask)
1261 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1262 if (masks[1] & devc->trigger.risingmask)
1263 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1264 if (masks[1] & devc->trigger.fallingmask)
1265 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1267 /* Only value/mask trigger. */
1271 /* Triggertype: event. */
1272 lut->params.selres = 3;
1277 static int hw_dev_acquisition_start(const struct sr_dev_inst *sdi,
1280 struct dev_context *devc;
1281 struct sr_datafeed_packet *packet;
1282 struct sr_datafeed_header *header;
1283 struct sr_datafeed_meta_logic meta;
1284 struct clockselect_50 clockselect;
1285 int frac, triggerpin, ret;
1286 uint8_t triggerselect;
1287 struct triggerinout triggerinout_conf;
1288 struct triggerlut lut;
1292 if (configure_probes(sdi) != SR_OK) {
1293 sr_err("asix-sigma: failed to configured probes");
1297 /* If the samplerate has not been set, default to 200 kHz. */
1298 if (devc->cur_firmware == -1) {
1299 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1303 /* Enter trigger programming mode. */
1304 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc);
1306 /* 100 and 200 MHz mode. */
1307 if (devc->cur_samplerate >= SR_MHZ(100)) {
1308 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc);
1310 /* Find which pin to trigger on from mask. */
1311 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1312 if ((devc->trigger.risingmask | devc->trigger.fallingmask) &
1316 /* Set trigger pin and light LED on trigger. */
1317 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1319 /* Default rising edge. */
1320 if (devc->trigger.fallingmask)
1321 triggerselect |= 1 << 3;
1323 /* All other modes. */
1324 } else if (devc->cur_samplerate <= SR_MHZ(50)) {
1325 build_basic_trigger(&lut, devc);
1327 sigma_write_trigger_lut(&lut, devc);
1329 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1332 /* Setup trigger in and out pins to default values. */
1333 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1334 triggerinout_conf.trgout_bytrigger = 1;
1335 triggerinout_conf.trgout_enable = 1;
1337 sigma_write_register(WRITE_TRIGGER_OPTION,
1338 (uint8_t *) &triggerinout_conf,
1339 sizeof(struct triggerinout), devc);
1341 /* Go back to normal mode. */
1342 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc);
1344 /* Set clock select register. */
1345 if (devc->cur_samplerate == SR_MHZ(200))
1346 /* Enable 4 probes. */
1347 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc);
1348 else if (devc->cur_samplerate == SR_MHZ(100))
1349 /* Enable 8 probes. */
1350 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc);
1353 * 50 MHz mode (or fraction thereof). Any fraction down to
1354 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1356 frac = SR_MHZ(50) / devc->cur_samplerate - 1;
1358 clockselect.async = 0;
1359 clockselect.fraction = frac;
1360 clockselect.disabled_probes = 0;
1362 sigma_write_register(WRITE_CLOCK_SELECT,
1363 (uint8_t *) &clockselect,
1364 sizeof(clockselect), devc);
1367 /* Setup maximum post trigger time. */
1368 sigma_set_register(WRITE_POST_TRIGGER,
1369 (devc->capture_ratio * 255) / 100, devc);
1371 /* Start acqusition. */
1372 gettimeofday(&devc->start_tv, 0);
1373 sigma_set_register(WRITE_MODE, 0x0d, devc);
1375 devc->session_dev_id = cb_data;
1377 if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) {
1378 sr_err("sigma: %s: packet malloc failed.", __func__);
1379 return SR_ERR_MALLOC;
1382 if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) {
1383 sr_err("sigma: %s: header malloc failed.", __func__);
1384 return SR_ERR_MALLOC;
1387 /* Send header packet to the session bus. */
1388 packet->type = SR_DF_HEADER;
1389 packet->payload = header;
1390 header->feed_version = 1;
1391 gettimeofday(&header->starttime, NULL);
1392 sr_session_send(devc->session_dev_id, packet);
1394 /* Send metadata about the SR_DF_LOGIC packets to come. */
1395 packet->type = SR_DF_META_LOGIC;
1396 packet->payload = &meta;
1397 meta.samplerate = devc->cur_samplerate;
1398 meta.num_probes = devc->num_probes;
1399 sr_session_send(devc->session_dev_id, packet);
1401 /* Add capture source. */
1402 sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi);
1407 devc->state.state = SIGMA_CAPTURE;
1412 static int hw_dev_acquisition_stop(const struct sr_dev_inst *sdi,
1415 struct dev_context *devc;
1418 /* Avoid compiler warnings. */
1421 sr_source_remove(0);
1423 if (!(devc = sdi->priv)) {
1424 sr_err("sigma: %s: sdi->priv was NULL", __func__);
1428 /* Stop acquisition. */
1429 sigma_set_register(WRITE_MODE, 0x11, devc);
1431 /* Set SDRAM Read Enable. */
1432 sigma_set_register(WRITE_MODE, 0x02, devc);
1434 /* Get the current position. */
1435 sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
1437 /* Check if trigger has fired. */
1438 modestatus = sigma_get_register(READ_MODE, devc);
1439 if (modestatus & 0x20)
1440 devc->state.triggerchunk = devc->state.triggerpos / 512;
1442 devc->state.triggerchunk = -1;
1444 devc->state.chunks_downloaded = 0;
1446 devc->state.state = SIGMA_DOWNLOAD;
1451 SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
1452 .name = "asix-sigma",
1453 .longname = "ASIX SIGMA/SIGMA2",
1456 .cleanup = hw_cleanup,
1458 .dev_open = hw_dev_open,
1459 .dev_close = hw_dev_close,
1460 .info_get = hw_info_get,
1461 .dev_config_set = hw_dev_config_set,
1462 .dev_acquisition_start = hw_dev_acquisition_start,
1463 .dev_acquisition_stop = hw_dev_acquisition_stop,