hardware/asix-sigma/asix-sigma.c

   1 /*
   2  * This file is part of the sigrok project.
   3  *
   4  * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
   5  * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
   6  * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
   7  *
   8  * This program is free software: you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation, either version 3 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 /*
  23  * ASIX SIGMA/SIGMA2 logic analyzer driver
  24  */
  25
  26 #include <glib.h>
  27 #include <glib/gstdio.h>
  28 #include <ftdi.h>
  29 #include <string.h>
  30 #include "libsigrok.h"
  31 #include "libsigrok-internal.h"
  32 #include "asix-sigma.h"
  33
  34 #define USB_VENDOR                      0xa600
  35 #define USB_PRODUCT                     0xa000
  36 #define USB_DESCRIPTION                 "ASIX SIGMA"
  37 #define USB_VENDOR_NAME                 "ASIX"
  38 #define USB_MODEL_NAME                  "SIGMA"
  39 #define USB_MODEL_VERSION               ""
  40 #define TRIGGER_TYPES                   "rf10"
  41 #define NUM_PROBES                      16
  42
  43 SR_PRIV struct sr_dev_driver asix_sigma_driver_info;
  44 static struct sr_dev_driver *di = &asix_sigma_driver_info;
  45 static int hw_dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data);
  46
  47 static const uint64_t supported_samplerates[] = {
  48         SR_KHZ(200),
  49         SR_KHZ(250),
  50         SR_KHZ(500),
  51         SR_MHZ(1),
  52         SR_MHZ(5),
  53         SR_MHZ(10),
  54         SR_MHZ(25),
  55         SR_MHZ(50),
  56         SR_MHZ(100),
  57         SR_MHZ(200),
  58         0,
  59 };
  60
  61 /*
  62  * Probe numbers seem to go from 1-16, according to this image:
  63  * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
  64  * (the cable has two additional GND pins, and a TI and TO pin)
  65  */
  66 static const char *probe_names[NUM_PROBES + 1] = {
  67         "1", "2", "3", "4", "5", "6", "7", "8",
  68         "9", "10", "11", "12", "13", "14", "15", "16",
  69         NULL,
  70 };
  71
  72 static const struct sr_samplerates samplerates = {
  73         0,
  74         0,
  75         0,
  76         supported_samplerates,
  77 };
  78
  79 static const int hwcaps[] = {
  80         SR_HWCAP_LOGIC_ANALYZER,
  81         SR_HWCAP_SAMPLERATE,
  82         SR_HWCAP_CAPTURE_RATIO,
  83
  84         SR_HWCAP_LIMIT_MSEC,
  85         0,
  86 };
  87
  88 /* Force the FPGA to reboot. */
  89 static uint8_t suicide[] = {
  90         0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
  91 };
  92
  93 /* Prepare to upload firmware (FPGA specific). */
  94 static uint8_t init[] = {
  95         0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
  96 };
  97
  98 /* Initialize the logic analyzer mode. */
  99 static uint8_t logic_mode_start[] = {
 100         0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
 101         0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
 102 };
 103
 104 static const char *firmware_files[] = {
 105         "asix-sigma-50.fw",     /* 50 MHz, supports 8 bit fractions */
 106         "asix-sigma-100.fw",    /* 100 MHz */
 107         "asix-sigma-200.fw",    /* 200 MHz */
 108         "asix-sigma-50sync.fw", /* Synchronous clock from pin */
 109         "asix-sigma-phasor.fw", /* Frequency counter */
 110 };
 111
 112 static int sigma_read(void *buf, size_t size, struct dev_context *devc)
 113 {
 114         int ret;
 115
 116         ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size);
 117         if (ret < 0) {
 118                 sr_err("ftdi_read_data failed: %s",
 119                        ftdi_get_error_string(&devc->ftdic));
 120         }
 121
 122         return ret;
 123 }
 124
 125 static int sigma_write(void *buf, size_t size, struct dev_context *devc)
 126 {
 127         int ret;
 128
 129         ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size);
 130         if (ret < 0) {
 131                 sr_err("ftdi_write_data failed: %s",
 132                        ftdi_get_error_string(&devc->ftdic));
 133         } else if ((size_t) ret != size) {
 134                 sr_err("ftdi_write_data did not complete write.");
 135         }
 136
 137         return ret;
 138 }
 139
 140 static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
 141                                 struct dev_context *devc)
 142 {
 143         size_t i;
 144         uint8_t buf[len + 2];
 145         int idx = 0;
 146
 147         buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
 148         buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
 149
 150         for (i = 0; i < len; ++i) {
 151                 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
 152                 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
 153         }
 154
 155         return sigma_write(buf, idx, devc);
 156 }
 157
 158 static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc)
 159 {
 160         return sigma_write_register(reg, &value, 1, devc);
 161 }
 162
 163 static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
 164                                struct dev_context *devc)
 165 {
 166         uint8_t buf[3];
 167
 168         buf[0] = REG_ADDR_LOW | (reg & 0xf);
 169         buf[1] = REG_ADDR_HIGH | (reg >> 4);
 170         buf[2] = REG_READ_ADDR;
 171
 172         sigma_write(buf, sizeof(buf), devc);
 173
 174         return sigma_read(data, len, devc);
 175 }
 176
 177 static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc)
 178 {
 179         uint8_t value;
 180
 181         if (1 != sigma_read_register(reg, &value, 1, devc)) {
 182                 sr_err("sigma_get_register: 1 byte expected");
 183                 return 0;
 184         }
 185
 186         return value;
 187 }
 188
 189 static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
 190                           struct dev_context *devc)
 191 {
 192         uint8_t buf[] = {
 193                 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
 194
 195                 REG_READ_ADDR | NEXT_REG,
 196                 REG_READ_ADDR | NEXT_REG,
 197                 REG_READ_ADDR | NEXT_REG,
 198                 REG_READ_ADDR | NEXT_REG,
 199                 REG_READ_ADDR | NEXT_REG,
 200                 REG_READ_ADDR | NEXT_REG,
 201         };
 202         uint8_t result[6];
 203
 204         sigma_write(buf, sizeof(buf), devc);
 205
 206         sigma_read(result, sizeof(result), devc);
 207
 208         *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
 209         *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
 210
 211         /* Not really sure why this must be done, but according to spec. */
 212         if ((--*stoppos & 0x1ff) == 0x1ff)
 213                 stoppos -= 64;
 214
 215         if ((*--triggerpos & 0x1ff) == 0x1ff)
 216                 triggerpos -= 64;
 217
 218         return 1;
 219 }
 220
 221 static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
 222                            uint8_t *data, struct dev_context *devc)
 223 {
 224         size_t i;
 225         uint8_t buf[4096];
 226         int idx = 0;
 227
 228         /* Send the startchunk. Index start with 1. */
 229         buf[0] = startchunk >> 8;
 230         buf[1] = startchunk & 0xff;
 231         sigma_write_register(WRITE_MEMROW, buf, 2, devc);
 232
 233         /* Read the DRAM. */
 234         buf[idx++] = REG_DRAM_BLOCK;
 235         buf[idx++] = REG_DRAM_WAIT_ACK;
 236
 237         for (i = 0; i < numchunks; ++i) {
 238                 /* Alternate bit to copy from DRAM to cache. */
 239                 if (i != (numchunks - 1))
 240                         buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
 241
 242                 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
 243
 244                 if (i != (numchunks - 1))
 245                         buf[idx++] = REG_DRAM_WAIT_ACK;
 246         }
 247
 248         sigma_write(buf, idx, devc);
 249
 250         return sigma_read(data, numchunks * CHUNK_SIZE, devc);
 251 }
 252
 253 /* Upload trigger look-up tables to Sigma. */
 254 static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc)
 255 {
 256         int i;
 257         uint8_t tmp[2];
 258         uint16_t bit;
 259
 260         /* Transpose the table and send to Sigma. */
 261         for (i = 0; i < 16; ++i) {
 262                 bit = 1 << i;
 263
 264                 tmp[0] = tmp[1] = 0;
 265
 266                 if (lut->m2d[0] & bit)
 267                         tmp[0] |= 0x01;
 268                 if (lut->m2d[1] & bit)
 269                         tmp[0] |= 0x02;
 270                 if (lut->m2d[2] & bit)
 271                         tmp[0] |= 0x04;
 272                 if (lut->m2d[3] & bit)
 273                         tmp[0] |= 0x08;
 274
 275                 if (lut->m3 & bit)
 276                         tmp[0] |= 0x10;
 277                 if (lut->m3s & bit)
 278                         tmp[0] |= 0x20;
 279                 if (lut->m4 & bit)
 280                         tmp[0] |= 0x40;
 281
 282                 if (lut->m0d[0] & bit)
 283                         tmp[1] |= 0x01;
 284                 if (lut->m0d[1] & bit)
 285                         tmp[1] |= 0x02;
 286                 if (lut->m0d[2] & bit)
 287                         tmp[1] |= 0x04;
 288                 if (lut->m0d[3] & bit)
 289                         tmp[1] |= 0x08;
 290
 291                 if (lut->m1d[0] & bit)
 292                         tmp[1] |= 0x10;
 293                 if (lut->m1d[1] & bit)
 294                         tmp[1] |= 0x20;
 295                 if (lut->m1d[2] & bit)
 296                         tmp[1] |= 0x40;
 297                 if (lut->m1d[3] & bit)
 298                         tmp[1] |= 0x80;
 299
 300                 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
 301                                      devc);
 302                 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
 303         }
 304
 305         /* Send the parameters */
 306         sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
 307                              sizeof(lut->params), devc);
 308
 309         return SR_OK;
 310 }
 311
 312 /* Generate the bitbang stream for programming the FPGA. */
 313 static int bin2bitbang(const char *filename,
 314                        unsigned char **buf, size_t *buf_size)
 315 {
 316         FILE *f;
 317         unsigned long file_size;
 318         unsigned long offset = 0;
 319         unsigned char *p;
 320         uint8_t *firmware;
 321         unsigned long fwsize = 0;
 322         const int buffer_size = 65536;
 323         size_t i;
 324         int c, bit, v;
 325         uint32_t imm = 0x3f6df2ab;
 326
 327         f = g_fopen(filename, "rb");
 328         if (!f) {
 329                 sr_err("g_fopen(\"%s\", \"rb\")", filename);
 330                 return SR_ERR;
 331         }
 332
 333         if (-1 == fseek(f, 0, SEEK_END)) {
 334                 sr_err("fseek on %s failed", filename);
 335                 fclose(f);
 336                 return SR_ERR;
 337         }
 338
 339         file_size = ftell(f);
 340
 341         fseek(f, 0, SEEK_SET);
 342
 343         if (!(firmware = g_try_malloc(buffer_size))) {
 344                 sr_err("%s: firmware malloc failed", __func__);
 345                 fclose(f);
 346                 return SR_ERR_MALLOC;
 347         }
 348
 349         while ((c = getc(f)) != EOF) {
 350                 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
 351                 firmware[fwsize++] = c ^ imm;
 352         }
 353         fclose(f);
 354
 355         if(fwsize != file_size) {
 356             sr_err("%s: Error reading firmware", filename);
 357             fclose(f);
 358             g_free(firmware);
 359             return SR_ERR;
 360         }
 361
 362         *buf_size = fwsize * 2 * 8;
 363
 364         *buf = p = (unsigned char *)g_try_malloc(*buf_size);
 365         if (!p) {
 366                 sr_err("%s: buf/p malloc failed", __func__);
 367                 g_free(firmware);
 368                 return SR_ERR_MALLOC;
 369         }
 370
 371         for (i = 0; i < fwsize; ++i) {
 372                 for (bit = 7; bit >= 0; --bit) {
 373                         v = firmware[i] & 1 << bit ? 0x40 : 0x00;
 374                         p[offset++] = v | 0x01;
 375                         p[offset++] = v;
 376                 }
 377         }
 378
 379         g_free(firmware);
 380
 381         if (offset != *buf_size) {
 382                 g_free(*buf);
 383                 sr_err("Error reading firmware %s "
 384                        "offset=%ld, file_size=%ld, buf_size=%zd.",
 385                        filename, offset, file_size, *buf_size);
 386
 387                 return SR_ERR;
 388         }
 389
 390         return SR_OK;
 391 }
 392
 393 static int clear_instances(void)
 394 {
 395         GSList *l;
 396         struct sr_dev_inst *sdi;
 397         struct drv_context *drvc;
 398         struct dev_context *devc;
 399
 400         drvc = di->priv;
 401
 402         /* Properly close all devices. */
 403         for (l = drvc->instances; l; l = l->next) {
 404                 if (!(sdi = l->data)) {
 405                         /* Log error, but continue cleaning up the rest. */
 406                         sr_err("%s: sdi was NULL, continuing", __func__);
 407                         continue;
 408                 }
 409                 if (sdi->priv) {
 410                         devc = sdi->priv;
 411                         ftdi_free(&devc->ftdic);
 412                 }
 413                 sr_dev_inst_free(sdi);
 414         }
 415         g_slist_free(drvc->instances);
 416         drvc->instances = NULL;
 417
 418         return SR_OK;
 419 }
 420
 421 static int hw_init(struct sr_context *sr_ctx)
 422 {
 423         struct drv_context *drvc;
 424
 425         if (!(drvc = g_try_malloc0(sizeof(struct drv_context)))) {
 426                 sr_err("Driver context malloc failed.");
 427                 return SR_ERR_MALLOC;
 428         }
 429         drvc->sr_ctx = sr_ctx;
 430         di->priv = drvc;
 431
 432         return SR_OK;
 433 }
 434
 435 static GSList *hw_scan(GSList *options)
 436 {
 437         struct sr_dev_inst *sdi;
 438         struct sr_probe *probe;
 439         struct drv_context *drvc;
 440         struct dev_context *devc;
 441         GSList *devices;
 442         struct ftdi_device_list *devlist;
 443         char serial_txt[10];
 444         uint32_t serial;
 445         int ret, i;
 446
 447         (void)options;
 448
 449         drvc = di->priv;
 450         devices = NULL;
 451         clear_instances();
 452
 453         if (!(devc = g_try_malloc(sizeof(struct dev_context)))) {
 454                 sr_err("%s: devc malloc failed", __func__);
 455                 return NULL;
 456         }
 457
 458         ftdi_init(&devc->ftdic);
 459
 460         /* Look for SIGMAs. */
 461
 462         if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist,
 463             USB_VENDOR, USB_PRODUCT)) <= 0) {
 464                 if (ret < 0)
 465                         sr_err("ftdi_usb_find_all(): %d", ret);
 466                 goto free;
 467         }
 468
 469         /* Make sure it's a version 1 or 2 SIGMA. */
 470         ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0,
 471                              serial_txt, sizeof(serial_txt));
 472         sscanf(serial_txt, "%x", &serial);
 473
 474         if (serial < 0xa6010000 || serial > 0xa602ffff) {
 475                 sr_err("Only SIGMA and SIGMA2 are supported "
 476                        "in this version of libsigrok.");
 477                 goto free;
 478         }
 479
 480         sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
 481
 482         devc->cur_samplerate = 0;
 483         devc->period_ps = 0;
 484         devc->limit_msec = 0;
 485         devc->cur_firmware = -1;
 486         devc->num_probes = 0;
 487         devc->samples_per_event = 0;
 488         devc->capture_ratio = 50;
 489         devc->use_triggers = 0;
 490
 491         /* Register SIGMA device. */
 492         if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME,
 493                                     USB_MODEL_NAME, USB_MODEL_VERSION))) {
 494                 sr_err("%s: sdi was NULL", __func__);
 495                 goto free;
 496         }
 497         sdi->driver = di;
 498
 499         for (i = 0; probe_names[i]; i++) {
 500                 if (!(probe = sr_probe_new(i, SR_PROBE_LOGIC, TRUE,
 501                                 probe_names[i])))
 502                         return NULL;
 503                 sdi->probes = g_slist_append(sdi->probes, probe);
 504         }
 505
 506         devices = g_slist_append(devices, sdi);
 507         drvc->instances = g_slist_append(drvc->instances, sdi);
 508         sdi->priv = devc;
 509
 510         /* We will open the device again when we need it. */
 511         ftdi_list_free(&devlist);
 512
 513         return devices;
 514
 515 free:
 516         ftdi_deinit(&devc->ftdic);
 517         g_free(devc);
 518         return NULL;
 519 }
 520
 521 static GSList *hw_dev_list(void)
 522 {
 523         struct drv_context *drvc;
 524
 525         drvc = di->priv;
 526
 527         return drvc->instances;
 528 }
 529
 530 static int upload_firmware(int firmware_idx, struct dev_context *devc)
 531 {
 532         int ret;
 533         unsigned char *buf;
 534         unsigned char pins;
 535         size_t buf_size;
 536         unsigned char result[32];
 537         char firmware_path[128];
 538
 539         /* Make sure it's an ASIX SIGMA. */
 540         if ((ret = ftdi_usb_open_desc(&devc->ftdic,
 541                 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
 542                 sr_err("ftdi_usb_open failed: %s",
 543                        ftdi_get_error_string(&devc->ftdic));
 544                 return 0;
 545         }
 546
 547         if ((ret = ftdi_set_bitmode(&devc->ftdic, 0xdf, BITMODE_BITBANG)) < 0) {
 548                 sr_err("ftdi_set_bitmode failed: %s",
 549                        ftdi_get_error_string(&devc->ftdic));
 550                 return 0;
 551         }
 552
 553         /* Four times the speed of sigmalogan - Works well. */
 554         if ((ret = ftdi_set_baudrate(&devc->ftdic, 750000)) < 0) {
 555                 sr_err("ftdi_set_baudrate failed: %s",
 556                        ftdi_get_error_string(&devc->ftdic));
 557                 return 0;
 558         }
 559
 560         /* Force the FPGA to reboot. */
 561         sigma_write(suicide, sizeof(suicide), devc);
 562         sigma_write(suicide, sizeof(suicide), devc);
 563         sigma_write(suicide, sizeof(suicide), devc);
 564         sigma_write(suicide, sizeof(suicide), devc);
 565
 566         /* Prepare to upload firmware (FPGA specific). */
 567         sigma_write(init, sizeof(init), devc);
 568
 569         ftdi_usb_purge_buffers(&devc->ftdic);
 570
 571         /* Wait until the FPGA asserts INIT_B. */
 572         while (1) {
 573                 ret = sigma_read(result, 1, devc);
 574                 if (result[0] & 0x20)
 575                         break;
 576         }
 577
 578         /* Prepare firmware. */
 579         snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR,
 580                  firmware_files[firmware_idx]);
 581
 582         if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) {
 583                 sr_err("An error occured while reading the firmware: %s",
 584                        firmware_path);
 585                 return ret;
 586         }
 587
 588         /* Upload firmare. */
 589         sr_info("Uploading firmware file '%s'.", firmware_files[firmware_idx]);
 590         sigma_write(buf, buf_size, devc);
 591
 592         g_free(buf);
 593
 594         if ((ret = ftdi_set_bitmode(&devc->ftdic, 0x00, BITMODE_RESET)) < 0) {
 595                 sr_err("ftdi_set_bitmode failed: %s",
 596                        ftdi_get_error_string(&devc->ftdic));
 597                 return SR_ERR;
 598         }
 599
 600         ftdi_usb_purge_buffers(&devc->ftdic);
 601
 602         /* Discard garbage. */
 603         while (1 == sigma_read(&pins, 1, devc))
 604                 ;
 605
 606         /* Initialize the logic analyzer mode. */
 607         sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
 608
 609         /* Expect a 3 byte reply. */
 610         ret = sigma_read(result, 3, devc);
 611         if (ret != 3 ||
 612             result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
 613                 sr_err("Configuration failed. Invalid reply received.");
 614                 return SR_ERR;
 615         }
 616
 617         devc->cur_firmware = firmware_idx;
 618
 619         sr_info("Firmware uploaded.");
 620
 621         return SR_OK;
 622 }
 623
 624 static int hw_dev_open(struct sr_dev_inst *sdi)
 625 {
 626         struct dev_context *devc;
 627         int ret;
 628
 629         devc = sdi->priv;
 630
 631         /* Make sure it's an ASIX SIGMA. */
 632         if ((ret = ftdi_usb_open_desc(&devc->ftdic,
 633                 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
 634
 635                 sr_err("ftdi_usb_open failed: %s",
 636                        ftdi_get_error_string(&devc->ftdic));
 637
 638                 return 0;
 639         }
 640
 641         sdi->status = SR_ST_ACTIVE;
 642
 643         return SR_OK;
 644 }
 645
 646 static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
 647 {
 648         int i, ret;
 649         struct dev_context *devc = sdi->priv;
 650
 651         ret = SR_OK;
 652
 653         for (i = 0; supported_samplerates[i]; i++) {
 654                 if (supported_samplerates[i] == samplerate)
 655                         break;
 656         }
 657         if (supported_samplerates[i] == 0)
 658                 return SR_ERR_SAMPLERATE;
 659
 660         if (samplerate <= SR_MHZ(50)) {
 661                 ret = upload_firmware(0, devc);
 662                 devc->num_probes = 16;
 663         }
 664         if (samplerate == SR_MHZ(100)) {
 665                 ret = upload_firmware(1, devc);
 666                 devc->num_probes = 8;
 667         }
 668         else if (samplerate == SR_MHZ(200)) {
 669                 ret = upload_firmware(2, devc);
 670                 devc->num_probes = 4;
 671         }
 672
 673         devc->cur_samplerate = samplerate;
 674         devc->period_ps = 1000000000000 / samplerate;
 675         devc->samples_per_event = 16 / devc->num_probes;
 676         devc->state.state = SIGMA_IDLE;
 677
 678         return ret;
 679 }
 680
 681 /*
 682  * In 100 and 200 MHz mode, only a single pin rising/falling can be
 683  * set as trigger. In other modes, two rising/falling triggers can be set,
 684  * in addition to value/mask trigger for any number of probes.
 685  *
 686  * The Sigma supports complex triggers using boolean expressions, but this
 687  * has not been implemented yet.
 688  */
 689 static int configure_probes(const struct sr_dev_inst *sdi)
 690 {
 691         struct dev_context *devc = sdi->priv;
 692         const struct sr_probe *probe;
 693         const GSList *l;
 694         int trigger_set = 0;
 695         int probebit;
 696
 697         memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
 698
 699         for (l = sdi->probes; l; l = l->next) {
 700                 probe = (struct sr_probe *)l->data;
 701                 probebit = 1 << (probe->index);
 702
 703                 if (!probe->enabled || !probe->trigger)
 704                         continue;
 705
 706                 if (devc->cur_samplerate >= SR_MHZ(100)) {
 707                         /* Fast trigger support. */
 708                         if (trigger_set) {
 709                                 sr_err("Only a single pin trigger in 100 and "
 710                                        "200MHz mode is supported.");
 711                                 return SR_ERR;
 712                         }
 713                         if (probe->trigger[0] == 'f')
 714                                 devc->trigger.fallingmask |= probebit;
 715                         else if (probe->trigger[0] == 'r')
 716                                 devc->trigger.risingmask |= probebit;
 717                         else {
 718                                 sr_err("Only rising/falling trigger in 100 "
 719                                        "and 200MHz mode is supported.");
 720                                 return SR_ERR;
 721                         }
 722
 723                         ++trigger_set;
 724                 } else {
 725                         /* Simple trigger support (event). */
 726                         if (probe->trigger[0] == '1') {
 727                                 devc->trigger.simplevalue |= probebit;
 728                                 devc->trigger.simplemask |= probebit;
 729                         }
 730                         else if (probe->trigger[0] == '0') {
 731                                 devc->trigger.simplevalue &= ~probebit;
 732                                 devc->trigger.simplemask |= probebit;
 733                         }
 734                         else if (probe->trigger[0] == 'f') {
 735                                 devc->trigger.fallingmask |= probebit;
 736                                 ++trigger_set;
 737                         }
 738                         else if (probe->trigger[0] == 'r') {
 739                                 devc->trigger.risingmask |= probebit;
 740                                 ++trigger_set;
 741                         }
 742
 743                         /*
 744                          * Actually, Sigma supports 2 rising/falling triggers,
 745                          * but they are ORed and the current trigger syntax
 746                          * does not permit ORed triggers.
 747                          */
 748                         if (trigger_set > 1) {
 749                                 sr_err("Only 1 rising/falling trigger "
 750                                        "is supported.");
 751                                 return SR_ERR;
 752                         }
 753                 }
 754
 755                 if (trigger_set)
 756                         devc->use_triggers = 1;
 757         }
 758
 759         return SR_OK;
 760 }
 761
 762 static int hw_dev_close(struct sr_dev_inst *sdi)
 763 {
 764         struct dev_context *devc;
 765
 766         if (!(devc = sdi->priv)) {
 767                 sr_err("%s: sdi->priv was NULL", __func__);
 768                 return SR_ERR_BUG;
 769         }
 770
 771         /* TODO */
 772         if (sdi->status == SR_ST_ACTIVE)
 773                 ftdi_usb_close(&devc->ftdic);
 774
 775         sdi->status = SR_ST_INACTIVE;
 776
 777         return SR_OK;
 778 }
 779
 780 static int hw_cleanup(void)
 781 {
 782         if (!di->priv)
 783                 return SR_OK;
 784
 785         clear_instances();
 786
 787         return SR_OK;
 788 }
 789
 790 static int hw_info_get(int info_id, const void **data,
 791                        const struct sr_dev_inst *sdi)
 792 {
 793         struct dev_context *devc;
 794
 795         switch (info_id) {
 796         case SR_DI_HWCAPS:
 797                 *data = hwcaps;
 798                 break;
 799         case SR_DI_NUM_PROBES:
 800                 *data = GINT_TO_POINTER(NUM_PROBES);
 801                 break;
 802         case SR_DI_PROBE_NAMES:
 803                 *data = probe_names;
 804                 break;
 805         case SR_DI_SAMPLERATES:
 806                 *data = &samplerates;
 807                 break;
 808         case SR_DI_TRIGGER_TYPES:
 809                 *data = (char *)TRIGGER_TYPES;
 810                 break;
 811         case SR_DI_CUR_SAMPLERATE:
 812                 if (sdi) {
 813                         devc = sdi->priv;
 814                         *data = &devc->cur_samplerate;
 815                 } else
 816                         return SR_ERR;
 817                 break;
 818         default:
 819                 return SR_ERR_ARG;
 820         }
 821
 822         return SR_OK;
 823 }
 824
 825 static int hw_dev_config_set(const struct sr_dev_inst *sdi, int hwcap,
 826                              const void *value)
 827 {
 828         struct dev_context *devc;
 829         int ret;
 830
 831         devc = sdi->priv;
 832
 833         if (hwcap == SR_HWCAP_SAMPLERATE) {
 834                 ret = set_samplerate(sdi, *(const uint64_t *)value);
 835         } else if (hwcap == SR_HWCAP_LIMIT_MSEC) {
 836                 devc->limit_msec = *(const uint64_t *)value;
 837                 if (devc->limit_msec > 0)
 838                         ret = SR_OK;
 839                 else
 840                         ret = SR_ERR;
 841         } else if (hwcap == SR_HWCAP_CAPTURE_RATIO) {
 842                 devc->capture_ratio = *(const uint64_t *)value;
 843                 if (devc->capture_ratio < 0 || devc->capture_ratio > 100)
 844                         ret = SR_ERR;
 845                 else
 846                         ret = SR_OK;
 847         } else {
 848                 ret = SR_ERR;
 849         }
 850
 851         return ret;
 852 }
 853
 854 /* Software trigger to determine exact trigger position. */
 855 static int get_trigger_offset(uint16_t *samples, uint16_t last_sample,
 856                               struct sigma_trigger *t)
 857 {
 858         int i;
 859
 860         for (i = 0; i < 8; ++i) {
 861                 if (i > 0)
 862                         last_sample = samples[i-1];
 863
 864                 /* Simple triggers. */
 865                 if ((samples[i] & t->simplemask) != t->simplevalue)
 866                         continue;
 867
 868                 /* Rising edge. */
 869                 if ((last_sample & t->risingmask) != 0 || (samples[i] &
 870                     t->risingmask) != t->risingmask)
 871                         continue;
 872
 873                 /* Falling edge. */
 874                 if ((last_sample & t->fallingmask) != t->fallingmask ||
 875                     (samples[i] & t->fallingmask) != 0)
 876                         continue;
 877
 878                 break;
 879         }
 880
 881         /* If we did not match, return original trigger pos. */
 882         return i & 0x7;
 883 }
 884
 885 /*
 886  * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
 887  * Each event is 20ns apart, and can contain multiple samples.
 888  *
 889  * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
 890  * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
 891  * For 50 MHz and below, events contain one sample for each channel,
 892  * spread 20 ns apart.
 893  */
 894 static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
 895                            uint16_t *lastsample, int triggerpos,
 896                            uint16_t limit_chunk, void *cb_data)
 897 {
 898         struct sr_dev_inst *sdi = cb_data;
 899         struct dev_context *devc = sdi->priv;
 900         uint16_t tsdiff, ts;
 901         uint16_t samples[65536 * devc->samples_per_event];
 902         struct sr_datafeed_packet packet;
 903         struct sr_datafeed_logic logic;
 904         int i, j, k, l, numpad, tosend;
 905         size_t n = 0, sent = 0;
 906         int clustersize = EVENTS_PER_CLUSTER * devc->samples_per_event;
 907         uint16_t *event;
 908         uint16_t cur_sample;
 909         int triggerts = -1;
 910
 911         /* Check if trigger is in this chunk. */
 912         if (triggerpos != -1) {
 913                 if (devc->cur_samplerate <= SR_MHZ(50))
 914                         triggerpos -= EVENTS_PER_CLUSTER - 1;
 915
 916                 if (triggerpos < 0)
 917                         triggerpos = 0;
 918
 919                 /* Find in which cluster the trigger occured. */
 920                 triggerts = triggerpos / 7;
 921         }
 922
 923         /* For each ts. */
 924         for (i = 0; i < 64; ++i) {
 925                 ts = *(uint16_t *) &buf[i * 16];
 926                 tsdiff = ts - *lastts;
 927                 *lastts = ts;
 928
 929                 /* Decode partial chunk. */
 930                 if (limit_chunk && ts > limit_chunk)
 931                         return SR_OK;
 932
 933                 /* Pad last sample up to current point. */
 934                 numpad = tsdiff * devc->samples_per_event - clustersize;
 935                 if (numpad > 0) {
 936                         for (j = 0; j < numpad; ++j)
 937                                 samples[j] = *lastsample;
 938
 939                         n = numpad;
 940                 }
 941
 942                 /* Send samples between previous and this timestamp to sigrok. */
 943                 sent = 0;
 944                 while (sent < n) {
 945                         tosend = MIN(2048, n - sent);
 946
 947                         packet.type = SR_DF_LOGIC;
 948                         packet.payload = &logic;
 949                         logic.length = tosend * sizeof(uint16_t);
 950                         logic.unitsize = 2;
 951                         logic.data = samples + sent;
 952                         sr_session_send(devc->session_dev_id, &packet);
 953
 954                         sent += tosend;
 955                 }
 956                 n = 0;
 957
 958                 event = (uint16_t *) &buf[i * 16 + 2];
 959                 cur_sample = 0;
 960
 961                 /* For each event in cluster. */
 962                 for (j = 0; j < 7; ++j) {
 963
 964                         /* For each sample in event. */
 965                         for (k = 0; k < devc->samples_per_event; ++k) {
 966                                 cur_sample = 0;
 967
 968                                 /* For each probe. */
 969                                 for (l = 0; l < devc->num_probes; ++l)
 970                                         cur_sample |= (!!(event[j] & (1 << (l *
 971                                            devc->samples_per_event + k)))) << l;
 972
 973                                 samples[n++] = cur_sample;
 974                         }
 975                 }
 976
 977                 /* Send data up to trigger point (if triggered). */
 978                 sent = 0;
 979                 if (i == triggerts) {
 980                         /*
 981                          * Trigger is not always accurate to sample because of
 982                          * pipeline delay. However, it always triggers before
 983                          * the actual event. We therefore look at the next
 984                          * samples to pinpoint the exact position of the trigger.
 985                          */
 986                         tosend = get_trigger_offset(samples, *lastsample,
 987                                                     &devc->trigger);
 988
 989                         if (tosend > 0) {
 990                                 packet.type = SR_DF_LOGIC;
 991                                 packet.payload = &logic;
 992                                 logic.length = tosend * sizeof(uint16_t);
 993                                 logic.unitsize = 2;
 994                                 logic.data = samples;
 995                                 sr_session_send(devc->session_dev_id, &packet);
 996
 997                                 sent += tosend;
 998                         }
 999
1000                         /* Only send trigger if explicitly enabled. */
1001                         if (devc->use_triggers) {
1002                                 packet.type = SR_DF_TRIGGER;
1003                                 sr_session_send(devc->session_dev_id, &packet);
1004                         }
1005                 }
1006
1007                 /* Send rest of the chunk to sigrok. */
1008                 tosend = n - sent;
1009
1010                 if (tosend > 0) {
1011                         packet.type = SR_DF_LOGIC;
1012                         packet.payload = &logic;
1013                         logic.length = tosend * sizeof(uint16_t);
1014                         logic.unitsize = 2;
1015                         logic.data = samples + sent;
1016                         sr_session_send(devc->session_dev_id, &packet);
1017                 }
1018
1019                 *lastsample = samples[n - 1];
1020         }
1021
1022         return SR_OK;
1023 }
1024
1025 static int receive_data(int fd, int revents, void *cb_data)
1026 {
1027         struct sr_dev_inst *sdi = cb_data;
1028         struct dev_context *devc = sdi->priv;
1029         struct sr_datafeed_packet packet;
1030         const int chunks_per_read = 32;
1031         unsigned char buf[chunks_per_read * CHUNK_SIZE];
1032         int bufsz, numchunks, i, newchunks;
1033         uint64_t running_msec;
1034         struct timeval tv;
1035
1036         (void)fd;
1037         (void)revents;
1038
1039         /* Get the current position. */
1040         sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
1041
1042         numchunks = (devc->state.stoppos + 511) / 512;
1043
1044         if (devc->state.state == SIGMA_IDLE)
1045                 return TRUE;
1046
1047         if (devc->state.state == SIGMA_CAPTURE) {
1048                 /* Check if the timer has expired, or memory is full. */
1049                 gettimeofday(&tv, 0);
1050                 running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 +
1051                         (tv.tv_usec - devc->start_tv.tv_usec) / 1000;
1052
1053                 if (running_msec < devc->limit_msec && numchunks < 32767)
1054                         return TRUE; /* While capturing... */
1055                 else
1056                         hw_dev_acquisition_stop(sdi, sdi);
1057
1058         }
1059
1060         if (devc->state.state == SIGMA_DOWNLOAD) {
1061                 if (devc->state.chunks_downloaded >= numchunks) {
1062                         /* End of samples. */
1063                         packet.type = SR_DF_END;
1064                         sr_session_send(devc->session_dev_id, &packet);
1065
1066                         devc->state.state = SIGMA_IDLE;
1067
1068                         return TRUE;
1069                 }
1070
1071                 newchunks = MIN(chunks_per_read,
1072                                 numchunks - devc->state.chunks_downloaded);
1073
1074                 sr_info("Downloading sample data: %.0f %%.",
1075                         100.0 * devc->state.chunks_downloaded / numchunks);
1076
1077                 bufsz = sigma_read_dram(devc->state.chunks_downloaded,
1078                                         newchunks, buf, devc);
1079                 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1080                 (void)bufsz;
1081
1082                 /* Find first ts. */
1083                 if (devc->state.chunks_downloaded == 0) {
1084                         devc->state.lastts = *(uint16_t *) buf - 1;
1085                         devc->state.lastsample = 0;
1086                 }
1087
1088                 /* Decode chunks and send them to sigrok. */
1089                 for (i = 0; i < newchunks; ++i) {
1090                         int limit_chunk = 0;
1091
1092                         /* The last chunk may potentially be only in part. */
1093                         if (devc->state.chunks_downloaded == numchunks - 1) {
1094                                 /* Find the last valid timestamp */
1095                                 limit_chunk = devc->state.stoppos % 512 + devc->state.lastts;
1096                         }
1097
1098                         if (devc->state.chunks_downloaded + i == devc->state.triggerchunk)
1099                                 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1100                                                 &devc->state.lastts,
1101                                                 &devc->state.lastsample,
1102                                                 devc->state.triggerpos & 0x1ff,
1103                                                 limit_chunk, sdi);
1104                         else
1105                                 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1106                                                 &devc->state.lastts,
1107                                                 &devc->state.lastsample,
1108                                                 -1, limit_chunk, sdi);
1109
1110                         ++devc->state.chunks_downloaded;
1111                 }
1112         }
1113
1114         return TRUE;
1115 }
1116
1117 /* Build a LUT entry used by the trigger functions. */
1118 static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1119 {
1120         int i, j, k, bit;
1121
1122         /* For each quad probe. */
1123         for (i = 0; i < 4; ++i) {
1124                 entry[i] = 0xffff;
1125
1126                 /* For each bit in LUT. */
1127                 for (j = 0; j < 16; ++j)
1128
1129                         /* For each probe in quad. */
1130                         for (k = 0; k < 4; ++k) {
1131                                 bit = 1 << (i * 4 + k);
1132
1133                                 /* Set bit in entry */
1134                                 if ((mask & bit) &&
1135                                     ((!(value & bit)) !=
1136                                     (!(j & (1 << k)))))
1137                                         entry[i] &= ~(1 << j);
1138                         }
1139         }
1140 }
1141
1142 /* Add a logical function to LUT mask. */
1143 static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1144                                  int index, int neg, uint16_t *mask)
1145 {
1146         int i, j;
1147         int x[2][2], tmp, a, b, aset, bset, rset;
1148
1149         memset(x, 0, 4 * sizeof(int));
1150
1151         /* Trigger detect condition. */
1152         switch (oper) {
1153         case OP_LEVEL:
1154                 x[0][1] = 1;
1155                 x[1][1] = 1;
1156                 break;
1157         case OP_NOT:
1158                 x[0][0] = 1;
1159                 x[1][0] = 1;
1160                 break;
1161         case OP_RISE:
1162                 x[0][1] = 1;
1163                 break;
1164         case OP_FALL:
1165                 x[1][0] = 1;
1166                 break;
1167         case OP_RISEFALL:
1168                 x[0][1] = 1;
1169                 x[1][0] = 1;
1170                 break;
1171         case OP_NOTRISE:
1172                 x[1][1] = 1;
1173                 x[0][0] = 1;
1174                 x[1][0] = 1;
1175                 break;
1176         case OP_NOTFALL:
1177                 x[1][1] = 1;
1178                 x[0][0] = 1;
1179                 x[0][1] = 1;
1180                 break;
1181         case OP_NOTRISEFALL:
1182                 x[1][1] = 1;
1183                 x[0][0] = 1;
1184                 break;
1185         }
1186
1187         /* Transpose if neg is set. */
1188         if (neg) {
1189                 for (i = 0; i < 2; ++i) {
1190                         for (j = 0; j < 2; ++j) {
1191                                 tmp = x[i][j];
1192                                 x[i][j] = x[1-i][1-j];
1193                                 x[1-i][1-j] = tmp;
1194                         }
1195                 }
1196         }
1197
1198         /* Update mask with function. */
1199         for (i = 0; i < 16; ++i) {
1200                 a = (i >> (2 * index + 0)) & 1;
1201                 b = (i >> (2 * index + 1)) & 1;
1202
1203                 aset = (*mask >> i) & 1;
1204                 bset = x[b][a];
1205
1206                 if (func == FUNC_AND || func == FUNC_NAND)
1207                         rset = aset & bset;
1208                 else if (func == FUNC_OR || func == FUNC_NOR)
1209                         rset = aset | bset;
1210                 else if (func == FUNC_XOR || func == FUNC_NXOR)
1211                         rset = aset ^ bset;
1212
1213                 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1214                         rset = !rset;
1215
1216                 *mask &= ~(1 << i);
1217
1218                 if (rset)
1219                         *mask |= 1 << i;
1220         }
1221 }
1222
1223 /*
1224  * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1225  * simple pin change and state triggers. Only two transitions (rise/fall) can be
1226  * set at any time, but a full mask and value can be set (0/1).
1227  */
1228 static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc)
1229 {
1230         int i,j;
1231         uint16_t masks[2] = { 0, 0 };
1232
1233         memset(lut, 0, sizeof(struct triggerlut));
1234
1235         /* Contant for simple triggers. */
1236         lut->m4 = 0xa000;
1237
1238         /* Value/mask trigger support. */
1239         build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask,
1240                         lut->m2d);
1241
1242         /* Rise/fall trigger support. */
1243         for (i = 0, j = 0; i < 16; ++i) {
1244                 if (devc->trigger.risingmask & (1 << i) ||
1245                     devc->trigger.fallingmask & (1 << i))
1246                         masks[j++] = 1 << i;
1247         }
1248
1249         build_lut_entry(masks[0], masks[0], lut->m0d);
1250         build_lut_entry(masks[1], masks[1], lut->m1d);
1251
1252         /* Add glue logic */
1253         if (masks[0] || masks[1]) {
1254                 /* Transition trigger. */
1255                 if (masks[0] & devc->trigger.risingmask)
1256                         add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1257                 if (masks[0] & devc->trigger.fallingmask)
1258                         add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1259                 if (masks[1] & devc->trigger.risingmask)
1260                         add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1261                 if (masks[1] & devc->trigger.fallingmask)
1262                         add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1263         } else {
1264                 /* Only value/mask trigger. */
1265                 lut->m3 = 0xffff;
1266         }
1267
1268         /* Triggertype: event. */
1269         lut->params.selres = 3;
1270
1271         return SR_OK;
1272 }
1273
1274 static int hw_dev_acquisition_start(const struct sr_dev_inst *sdi,
1275                 void *cb_data)
1276 {
1277         struct dev_context *devc;
1278         struct sr_datafeed_packet *packet;
1279         struct sr_datafeed_header *header;
1280         struct sr_datafeed_meta_logic meta;
1281         struct clockselect_50 clockselect;
1282         int frac, triggerpin, ret;
1283         uint8_t triggerselect = 0;
1284         struct triggerinout triggerinout_conf;
1285         struct triggerlut lut;
1286
1287         devc = sdi->priv;
1288
1289         if (configure_probes(sdi) != SR_OK) {
1290                 sr_err("Failed to configure probes.");
1291                 return SR_ERR;
1292         }
1293
1294         /* If the samplerate has not been set, default to 200 kHz. */
1295         if (devc->cur_firmware == -1) {
1296                 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1297                         return ret;
1298         }
1299
1300         /* Enter trigger programming mode. */
1301         sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc);
1302
1303         /* 100 and 200 MHz mode. */
1304         if (devc->cur_samplerate >= SR_MHZ(100)) {
1305                 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc);
1306
1307                 /* Find which pin to trigger on from mask. */
1308                 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1309                         if ((devc->trigger.risingmask | devc->trigger.fallingmask) &
1310                             (1 << triggerpin))
1311                                 break;
1312
1313                 /* Set trigger pin and light LED on trigger. */
1314                 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1315
1316                 /* Default rising edge. */
1317                 if (devc->trigger.fallingmask)
1318                         triggerselect |= 1 << 3;
1319
1320         /* All other modes. */
1321         } else if (devc->cur_samplerate <= SR_MHZ(50)) {
1322                 build_basic_trigger(&lut, devc);
1323
1324                 sigma_write_trigger_lut(&lut, devc);
1325
1326                 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1327         }
1328
1329         /* Setup trigger in and out pins to default values. */
1330         memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1331         triggerinout_conf.trgout_bytrigger = 1;
1332         triggerinout_conf.trgout_enable = 1;
1333
1334         sigma_write_register(WRITE_TRIGGER_OPTION,
1335                              (uint8_t *) &triggerinout_conf,
1336                              sizeof(struct triggerinout), devc);
1337
1338         /* Go back to normal mode. */
1339         sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc);
1340
1341         /* Set clock select register. */
1342         if (devc->cur_samplerate == SR_MHZ(200))
1343                 /* Enable 4 probes. */
1344                 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc);
1345         else if (devc->cur_samplerate == SR_MHZ(100))
1346                 /* Enable 8 probes. */
1347                 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc);
1348         else {
1349                 /*
1350                  * 50 MHz mode (or fraction thereof). Any fraction down to
1351                  * 50 MHz / 256 can be used, but is not supported by sigrok API.
1352                  */
1353                 frac = SR_MHZ(50) / devc->cur_samplerate - 1;
1354
1355                 clockselect.async = 0;
1356                 clockselect.fraction = frac;
1357                 clockselect.disabled_probes = 0;
1358
1359                 sigma_write_register(WRITE_CLOCK_SELECT,
1360                                      (uint8_t *) &clockselect,
1361                                      sizeof(clockselect), devc);
1362         }
1363
1364         /* Setup maximum post trigger time. */
1365         sigma_set_register(WRITE_POST_TRIGGER,
1366                            (devc->capture_ratio * 255) / 100, devc);
1367
1368         /* Start acqusition. */
1369         gettimeofday(&devc->start_tv, 0);
1370         sigma_set_register(WRITE_MODE, 0x0d, devc);
1371
1372         devc->session_dev_id = cb_data;
1373
1374         if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) {
1375                 sr_err("%s: packet malloc failed.", __func__);
1376                 return SR_ERR_MALLOC;
1377         }
1378
1379         if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) {
1380                 sr_err("%s: header malloc failed.", __func__);
1381                 return SR_ERR_MALLOC;
1382         }
1383
1384         /* Send header packet to the session bus. */
1385         packet->type = SR_DF_HEADER;
1386         packet->payload = header;
1387         header->feed_version = 1;
1388         gettimeofday(&header->starttime, NULL);
1389         sr_session_send(devc->session_dev_id, packet);
1390
1391         /* Send metadata about the SR_DF_LOGIC packets to come. */
1392         packet->type = SR_DF_META_LOGIC;
1393         packet->payload = &meta;
1394         meta.samplerate = devc->cur_samplerate;
1395         meta.num_probes = devc->num_probes;
1396         sr_session_send(devc->session_dev_id, packet);
1397
1398         /* Add capture source. */
1399         sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi);
1400
1401         g_free(header);
1402         g_free(packet);
1403
1404         devc->state.state = SIGMA_CAPTURE;
1405
1406         return SR_OK;
1407 }
1408
1409 static int hw_dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
1410 {
1411         struct dev_context *devc;
1412         uint8_t modestatus;
1413
1414         (void)cb_data;
1415
1416         sr_source_remove(0);
1417
1418         if (!(devc = sdi->priv)) {
1419                 sr_err("%s: sdi->priv was NULL", __func__);
1420                 return SR_ERR_BUG;
1421         }
1422
1423         /* Stop acquisition. */
1424         sigma_set_register(WRITE_MODE, 0x11, devc);
1425
1426         /* Set SDRAM Read Enable. */
1427         sigma_set_register(WRITE_MODE, 0x02, devc);
1428
1429         /* Get the current position. */
1430         sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
1431
1432         /* Check if trigger has fired. */
1433         modestatus = sigma_get_register(READ_MODE, devc);
1434         if (modestatus & 0x20)
1435                 devc->state.triggerchunk = devc->state.triggerpos / 512;
1436         else
1437                 devc->state.triggerchunk = -1;
1438
1439         devc->state.chunks_downloaded = 0;
1440
1441         devc->state.state = SIGMA_DOWNLOAD;
1442
1443         return SR_OK;
1444 }
1445
1446 SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
1447         .name = "asix-sigma",
1448         .longname = "ASIX SIGMA/SIGMA2",
1449         .api_version = 1,
1450         .init = hw_init,
1451         .cleanup = hw_cleanup,
1452         .scan = hw_scan,
1453         .dev_list = hw_dev_list,
1454         .dev_clear = clear_instances,
1455         .dev_open = hw_dev_open,
1456         .dev_close = hw_dev_close,
1457         .info_get = hw_info_get,
1458         .dev_config_set = hw_dev_config_set,
1459         .dev_acquisition_start = hw_dev_acquisition_start,
1460         .dev_acquisition_stop = hw_dev_acquisition_stop,
1461         .priv = NULL,
1462 };