hardware/asix-sigma/asix-sigma.c

   1 /*
   2  * This file is part of the sigrok project.
   3  *
   4  * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
   5  * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
   6  * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
   7  *
   8  * This program is free software: you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation, either version 3 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 /*
  23  * ASIX SIGMA/SIGMA2 logic analyzer driver
  24  */
  25
  26 #include <glib.h>
  27 #include <glib/gstdio.h>
  28 #include <ftdi.h>
  29 #include <string.h>
  30 #include "libsigrok.h"
  31 #include "libsigrok-internal.h"
  32 #include "asix-sigma.h"
  33
  34 #define USB_VENDOR                      0xa600
  35 #define USB_PRODUCT                     0xa000
  36 #define USB_DESCRIPTION                 "ASIX SIGMA"
  37 #define USB_VENDOR_NAME                 "ASIX"
  38 #define USB_MODEL_NAME                  "SIGMA"
  39 #define USB_MODEL_VERSION               ""
  40 #define TRIGGER_TYPES                   "rf10"
  41 #define NUM_PROBES                      16
  42
  43 SR_PRIV struct sr_dev_driver asix_sigma_driver_info;
  44 static struct sr_dev_driver *di = &asix_sigma_driver_info;
  45 static int hw_dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data);
  46
  47 static const uint64_t supported_samplerates[] = {
  48         SR_KHZ(200),
  49         SR_KHZ(250),
  50         SR_KHZ(500),
  51         SR_MHZ(1),
  52         SR_MHZ(5),
  53         SR_MHZ(10),
  54         SR_MHZ(25),
  55         SR_MHZ(50),
  56         SR_MHZ(100),
  57         SR_MHZ(200),
  58         0,
  59 };
  60
  61 /*
  62  * Probe numbers seem to go from 1-16, according to this image:
  63  * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
  64  * (the cable has two additional GND pins, and a TI and TO pin)
  65  */
  66 static const char *probe_names[NUM_PROBES + 1] = {
  67         "1", "2", "3", "4", "5", "6", "7", "8",
  68         "9", "10", "11", "12", "13", "14", "15", "16",
  69         NULL,
  70 };
  71
  72 static const struct sr_samplerates samplerates = {
  73         0,
  74         0,
  75         0,
  76         supported_samplerates,
  77 };
  78
  79 static const int hwcaps[] = {
  80         SR_HWCAP_LOGIC_ANALYZER,
  81         SR_HWCAP_SAMPLERATE,
  82         SR_HWCAP_CAPTURE_RATIO,
  83
  84         SR_HWCAP_LIMIT_MSEC,
  85         0,
  86 };
  87
  88 /* Force the FPGA to reboot. */
  89 static uint8_t suicide[] = {
  90         0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
  91 };
  92
  93 /* Prepare to upload firmware (FPGA specific). */
  94 static uint8_t init[] = {
  95         0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
  96 };
  97
  98 /* Initialize the logic analyzer mode. */
  99 static uint8_t logic_mode_start[] = {
 100         0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
 101         0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
 102 };
 103
 104 static const char *firmware_files[] = {
 105         "asix-sigma-50.fw",     /* 50 MHz, supports 8 bit fractions */
 106         "asix-sigma-100.fw",    /* 100 MHz */
 107         "asix-sigma-200.fw",    /* 200 MHz */
 108         "asix-sigma-50sync.fw", /* Synchronous clock from pin */
 109         "asix-sigma-phasor.fw", /* Frequency counter */
 110 };
 111
 112 static int sigma_read(void *buf, size_t size, struct dev_context *devc)
 113 {
 114         int ret;
 115
 116         ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size);
 117         if (ret < 0) {
 118                 sr_err("ftdi_read_data failed: %s",
 119                        ftdi_get_error_string(&devc->ftdic));
 120         }
 121
 122         return ret;
 123 }
 124
 125 static int sigma_write(void *buf, size_t size, struct dev_context *devc)
 126 {
 127         int ret;
 128
 129         ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size);
 130         if (ret < 0) {
 131                 sr_err("ftdi_write_data failed: %s",
 132                        ftdi_get_error_string(&devc->ftdic));
 133         } else if ((size_t) ret != size) {
 134                 sr_err("ftdi_write_data did not complete write.");
 135         }
 136
 137         return ret;
 138 }
 139
 140 static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
 141                                 struct dev_context *devc)
 142 {
 143         size_t i;
 144         uint8_t buf[len + 2];
 145         int idx = 0;
 146
 147         buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
 148         buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
 149
 150         for (i = 0; i < len; ++i) {
 151                 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
 152                 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
 153         }
 154
 155         return sigma_write(buf, idx, devc);
 156 }
 157
 158 static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc)
 159 {
 160         return sigma_write_register(reg, &value, 1, devc);
 161 }
 162
 163 static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
 164                                struct dev_context *devc)
 165 {
 166         uint8_t buf[3];
 167
 168         buf[0] = REG_ADDR_LOW | (reg & 0xf);
 169         buf[1] = REG_ADDR_HIGH | (reg >> 4);
 170         buf[2] = REG_READ_ADDR;
 171
 172         sigma_write(buf, sizeof(buf), devc);
 173
 174         return sigma_read(data, len, devc);
 175 }
 176
 177 static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc)
 178 {
 179         uint8_t value;
 180
 181         if (1 != sigma_read_register(reg, &value, 1, devc)) {
 182                 sr_err("sigma_get_register: 1 byte expected");
 183                 return 0;
 184         }
 185
 186         return value;
 187 }
 188
 189 static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
 190                           struct dev_context *devc)
 191 {
 192         uint8_t buf[] = {
 193                 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
 194
 195                 REG_READ_ADDR | NEXT_REG,
 196                 REG_READ_ADDR | NEXT_REG,
 197                 REG_READ_ADDR | NEXT_REG,
 198                 REG_READ_ADDR | NEXT_REG,
 199                 REG_READ_ADDR | NEXT_REG,
 200                 REG_READ_ADDR | NEXT_REG,
 201         };
 202         uint8_t result[6];
 203
 204         sigma_write(buf, sizeof(buf), devc);
 205
 206         sigma_read(result, sizeof(result), devc);
 207
 208         *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
 209         *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
 210
 211         /* Not really sure why this must be done, but according to spec. */
 212         if ((--*stoppos & 0x1ff) == 0x1ff)
 213                 stoppos -= 64;
 214
 215         if ((*--triggerpos & 0x1ff) == 0x1ff)
 216                 triggerpos -= 64;
 217
 218         return 1;
 219 }
 220
 221 static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
 222                            uint8_t *data, struct dev_context *devc)
 223 {
 224         size_t i;
 225         uint8_t buf[4096];
 226         int idx = 0;
 227
 228         /* Send the startchunk. Index start with 1. */
 229         buf[0] = startchunk >> 8;
 230         buf[1] = startchunk & 0xff;
 231         sigma_write_register(WRITE_MEMROW, buf, 2, devc);
 232
 233         /* Read the DRAM. */
 234         buf[idx++] = REG_DRAM_BLOCK;
 235         buf[idx++] = REG_DRAM_WAIT_ACK;
 236
 237         for (i = 0; i < numchunks; ++i) {
 238                 /* Alternate bit to copy from DRAM to cache. */
 239                 if (i != (numchunks - 1))
 240                         buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
 241
 242                 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
 243
 244                 if (i != (numchunks - 1))
 245                         buf[idx++] = REG_DRAM_WAIT_ACK;
 246         }
 247
 248         sigma_write(buf, idx, devc);
 249
 250         return sigma_read(data, numchunks * CHUNK_SIZE, devc);
 251 }
 252
 253 /* Upload trigger look-up tables to Sigma. */
 254 static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc)
 255 {
 256         int i;
 257         uint8_t tmp[2];
 258         uint16_t bit;
 259
 260         /* Transpose the table and send to Sigma. */
 261         for (i = 0; i < 16; ++i) {
 262                 bit = 1 << i;
 263
 264                 tmp[0] = tmp[1] = 0;
 265
 266                 if (lut->m2d[0] & bit)
 267                         tmp[0] |= 0x01;
 268                 if (lut->m2d[1] & bit)
 269                         tmp[0] |= 0x02;
 270                 if (lut->m2d[2] & bit)
 271                         tmp[0] |= 0x04;
 272                 if (lut->m2d[3] & bit)
 273                         tmp[0] |= 0x08;
 274
 275                 if (lut->m3 & bit)
 276                         tmp[0] |= 0x10;
 277                 if (lut->m3s & bit)
 278                         tmp[0] |= 0x20;
 279                 if (lut->m4 & bit)
 280                         tmp[0] |= 0x40;
 281
 282                 if (lut->m0d[0] & bit)
 283                         tmp[1] |= 0x01;
 284                 if (lut->m0d[1] & bit)
 285                         tmp[1] |= 0x02;
 286                 if (lut->m0d[2] & bit)
 287                         tmp[1] |= 0x04;
 288                 if (lut->m0d[3] & bit)
 289                         tmp[1] |= 0x08;
 290
 291                 if (lut->m1d[0] & bit)
 292                         tmp[1] |= 0x10;
 293                 if (lut->m1d[1] & bit)
 294                         tmp[1] |= 0x20;
 295                 if (lut->m1d[2] & bit)
 296                         tmp[1] |= 0x40;
 297                 if (lut->m1d[3] & bit)
 298                         tmp[1] |= 0x80;
 299
 300                 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
 301                                      devc);
 302                 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
 303         }
 304
 305         /* Send the parameters */
 306         sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
 307                              sizeof(lut->params), devc);
 308
 309         return SR_OK;
 310 }
 311
 312 /* Generate the bitbang stream for programming the FPGA. */
 313 static int bin2bitbang(const char *filename,
 314                        unsigned char **buf, size_t *buf_size)
 315 {
 316         FILE *f;
 317         unsigned long file_size;
 318         unsigned long offset = 0;
 319         unsigned char *p;
 320         uint8_t *firmware;
 321         unsigned long fwsize = 0;
 322         const int buffer_size = 65536;
 323         size_t i;
 324         int c, bit, v;
 325         uint32_t imm = 0x3f6df2ab;
 326
 327         f = g_fopen(filename, "rb");
 328         if (!f) {
 329                 sr_err("g_fopen(\"%s\", \"rb\")", filename);
 330                 return SR_ERR;
 331         }
 332
 333         if (-1 == fseek(f, 0, SEEK_END)) {
 334                 sr_err("fseek on %s failed", filename);
 335                 fclose(f);
 336                 return SR_ERR;
 337         }
 338
 339         file_size = ftell(f);
 340
 341         fseek(f, 0, SEEK_SET);
 342
 343         if (!(firmware = g_try_malloc(buffer_size))) {
 344                 sr_err("%s: firmware malloc failed", __func__);
 345                 fclose(f);
 346                 return SR_ERR_MALLOC;
 347         }
 348
 349         while ((c = getc(f)) != EOF) {
 350                 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
 351                 firmware[fwsize++] = c ^ imm;
 352         }
 353         fclose(f);
 354
 355         if(fwsize != file_size) {
 356             sr_err("%s: Error reading firmware", filename);
 357             fclose(f);
 358             g_free(firmware);
 359             return SR_ERR;
 360         }
 361
 362         *buf_size = fwsize * 2 * 8;
 363
 364         *buf = p = (unsigned char *)g_try_malloc(*buf_size);
 365         if (!p) {
 366                 sr_err("%s: buf/p malloc failed", __func__);
 367                 g_free(firmware);
 368                 return SR_ERR_MALLOC;
 369         }
 370
 371         for (i = 0; i < fwsize; ++i) {
 372                 for (bit = 7; bit >= 0; --bit) {
 373                         v = firmware[i] & 1 << bit ? 0x40 : 0x00;
 374                         p[offset++] = v | 0x01;
 375                         p[offset++] = v;
 376                 }
 377         }
 378
 379         g_free(firmware);
 380
 381         if (offset != *buf_size) {
 382                 g_free(*buf);
 383                 sr_err("Error reading firmware %s "
 384                        "offset=%ld, file_size=%ld, buf_size=%zd.",
 385                        filename, offset, file_size, *buf_size);
 386
 387                 return SR_ERR;
 388         }
 389
 390         return SR_OK;
 391 }
 392
 393 static int clear_instances(void)
 394 {
 395         GSList *l;
 396         struct sr_dev_inst *sdi;
 397         struct drv_context *drvc;
 398         struct dev_context *devc;
 399
 400         drvc = di->priv;
 401
 402         /* Properly close all devices. */
 403         for (l = drvc->instances; l; l = l->next) {
 404                 if (!(sdi = l->data)) {
 405                         /* Log error, but continue cleaning up the rest. */
 406                         sr_err("%s: sdi was NULL, continuing", __func__);
 407                         continue;
 408                 }
 409                 if (sdi->priv) {
 410                         devc = sdi->priv;
 411                         ftdi_free(&devc->ftdic);
 412                 }
 413                 sr_dev_inst_free(sdi);
 414         }
 415         g_slist_free(drvc->instances);
 416         drvc->instances = NULL;
 417
 418         return SR_OK;
 419 }
 420
 421 static int hw_init(struct sr_context *sr_ctx)
 422 {
 423         struct drv_context *drvc;
 424
 425         if (!(drvc = g_try_malloc0(sizeof(struct drv_context)))) {
 426                 sr_err("Driver context malloc failed.");
 427                 return SR_ERR_MALLOC;
 428         }
 429         drvc->sr_ctx = sr_ctx;
 430         di->priv = drvc;
 431
 432         return SR_OK;
 433 }
 434
 435 static GSList *hw_scan(GSList *options)
 436 {
 437         struct sr_dev_inst *sdi;
 438         struct sr_probe *probe;
 439         struct drv_context *drvc;
 440         struct dev_context *devc;
 441         GSList *devices;
 442         struct ftdi_device_list *devlist;
 443         char serial_txt[10];
 444         uint32_t serial;
 445         int ret, i;
 446
 447         (void)options;
 448
 449         drvc = di->priv;
 450         devices = NULL;
 451         clear_instances();
 452
 453         if (!(devc = g_try_malloc(sizeof(struct dev_context)))) {
 454                 sr_err("%s: devc malloc failed", __func__);
 455                 return NULL;
 456         }
 457
 458         ftdi_init(&devc->ftdic);
 459
 460         /* Look for SIGMAs. */
 461
 462         if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist,
 463             USB_VENDOR, USB_PRODUCT)) <= 0) {
 464                 if (ret < 0)
 465                         sr_err("ftdi_usb_find_all(): %d", ret);
 466                 goto free;
 467         }
 468
 469         /* Make sure it's a version 1 or 2 SIGMA. */
 470         ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0,
 471                              serial_txt, sizeof(serial_txt));
 472         sscanf(serial_txt, "%x", &serial);
 473
 474         if (serial < 0xa6010000 || serial > 0xa602ffff) {
 475                 sr_err("Only SIGMA and SIGMA2 are supported "
 476                        "in this version of libsigrok.");
 477                 goto free;
 478         }
 479
 480         sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
 481
 482         devc->cur_samplerate = 0;
 483         devc->period_ps = 0;
 484         devc->limit_msec = 0;
 485         devc->cur_firmware = -1;
 486         devc->num_probes = 0;
 487         devc->samples_per_event = 0;
 488         devc->capture_ratio = 50;
 489         devc->use_triggers = 0;
 490
 491         /* Register SIGMA device. */
 492         if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME,
 493                                     USB_MODEL_NAME, USB_MODEL_VERSION))) {
 494                 sr_err("%s: sdi was NULL", __func__);
 495                 goto free;
 496         }
 497         sdi->driver = di;
 498
 499         for (i = 0; probe_names[i]; i++) {
 500                 if (!(probe = sr_probe_new(i, SR_PROBE_LOGIC, TRUE,
 501                                 probe_names[i])))
 502                         return NULL;
 503                 sdi->probes = g_slist_append(sdi->probes, probe);
 504         }
 505
 506         devices = g_slist_append(devices, sdi);
 507         drvc->instances = g_slist_append(drvc->instances, sdi);
 508         sdi->priv = devc;
 509
 510         /* We will open the device again when we need it. */
 511         ftdi_list_free(&devlist);
 512
 513         return devices;
 514
 515 free:
 516         ftdi_deinit(&devc->ftdic);
 517         g_free(devc);
 518         return NULL;
 519 }
 520
 521 static GSList *hw_dev_list(void)
 522 {
 523         struct drv_context *drvc;
 524
 525         drvc = di->priv;
 526
 527         return drvc->instances;
 528 }
 529
 530 static int upload_firmware(int firmware_idx, struct dev_context *devc)
 531 {
 532         int ret;
 533         unsigned char *buf;
 534         unsigned char pins;
 535         size_t buf_size;
 536         unsigned char result[32];
 537         char firmware_path[128];
 538
 539         /* Make sure it's an ASIX SIGMA. */
 540         if ((ret = ftdi_usb_open_desc(&devc->ftdic,
 541                 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
 542                 sr_err("ftdi_usb_open failed: %s",
 543                        ftdi_get_error_string(&devc->ftdic));
 544                 return 0;
 545         }
 546
 547         if ((ret = ftdi_set_bitmode(&devc->ftdic, 0xdf, BITMODE_BITBANG)) < 0) {
 548                 sr_err("ftdi_set_bitmode failed: %s",
 549                        ftdi_get_error_string(&devc->ftdic));
 550                 return 0;
 551         }
 552
 553         /* Four times the speed of sigmalogan - Works well. */
 554         if ((ret = ftdi_set_baudrate(&devc->ftdic, 750000)) < 0) {
 555                 sr_err("ftdi_set_baudrate failed: %s",
 556                        ftdi_get_error_string(&devc->ftdic));
 557                 return 0;
 558         }
 559
 560         /* Force the FPGA to reboot. */
 561         sigma_write(suicide, sizeof(suicide), devc);
 562         sigma_write(suicide, sizeof(suicide), devc);
 563         sigma_write(suicide, sizeof(suicide), devc);
 564         sigma_write(suicide, sizeof(suicide), devc);
 565
 566         /* Prepare to upload firmware (FPGA specific). */
 567         sigma_write(init, sizeof(init), devc);
 568
 569         ftdi_usb_purge_buffers(&devc->ftdic);
 570
 571         /* Wait until the FPGA asserts INIT_B. */
 572         while (1) {
 573                 ret = sigma_read(result, 1, devc);
 574                 if (result[0] & 0x20)
 575                         break;
 576         }
 577
 578         /* Prepare firmware. */
 579         snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR,
 580                  firmware_files[firmware_idx]);
 581
 582         if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) {
 583                 sr_err("An error occured while reading the firmware: %s",
 584                        firmware_path);
 585                 return ret;
 586         }
 587
 588         /* Upload firmare. */
 589         sr_info("Uploading firmware file '%s'.", firmware_files[firmware_idx]);
 590         sigma_write(buf, buf_size, devc);
 591
 592         g_free(buf);
 593
 594         if ((ret = ftdi_set_bitmode(&devc->ftdic, 0x00, BITMODE_RESET)) < 0) {
 595                 sr_err("ftdi_set_bitmode failed: %s",
 596                        ftdi_get_error_string(&devc->ftdic));
 597                 return SR_ERR;
 598         }
 599
 600         ftdi_usb_purge_buffers(&devc->ftdic);
 601
 602         /* Discard garbage. */
 603         while (1 == sigma_read(&pins, 1, devc))
 604                 ;
 605
 606         /* Initialize the logic analyzer mode. */
 607         sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
 608
 609         /* Expect a 3 byte reply. */
 610         ret = sigma_read(result, 3, devc);
 611         if (ret != 3 ||
 612             result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
 613                 sr_err("Configuration failed. Invalid reply received.");
 614                 return SR_ERR;
 615         }
 616
 617         devc->cur_firmware = firmware_idx;
 618
 619         sr_info("Firmware uploaded.");
 620
 621         return SR_OK;
 622 }
 623
 624 static int hw_dev_open(struct sr_dev_inst *sdi)
 625 {
 626         struct dev_context *devc;
 627         int ret;
 628
 629         devc = sdi->priv;
 630
 631         /* Make sure it's an ASIX SIGMA. */
 632         if ((ret = ftdi_usb_open_desc(&devc->ftdic,
 633                 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
 634
 635                 sr_err("ftdi_usb_open failed: %s",
 636                        ftdi_get_error_string(&devc->ftdic));
 637
 638                 return 0;
 639         }
 640
 641         sdi->status = SR_ST_ACTIVE;
 642
 643         return SR_OK;
 644 }
 645
 646 static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
 647 {
 648         int i, ret;
 649         struct dev_context *devc = sdi->priv;
 650
 651         for (i = 0; supported_samplerates[i]; i++) {
 652                 if (supported_samplerates[i] == samplerate)
 653                         break;
 654         }
 655         if (supported_samplerates[i] == 0)
 656                 return SR_ERR_SAMPLERATE;
 657
 658         if (samplerate <= SR_MHZ(50)) {
 659                 ret = upload_firmware(0, devc);
 660                 devc->num_probes = 16;
 661         }
 662         if (samplerate == SR_MHZ(100)) {
 663                 ret = upload_firmware(1, devc);
 664                 devc->num_probes = 8;
 665         }
 666         else if (samplerate == SR_MHZ(200)) {
 667                 ret = upload_firmware(2, devc);
 668                 devc->num_probes = 4;
 669         }
 670
 671         devc->cur_samplerate = samplerate;
 672         devc->period_ps = 1000000000000 / samplerate;
 673         devc->samples_per_event = 16 / devc->num_probes;
 674         devc->state.state = SIGMA_IDLE;
 675
 676         return ret;
 677 }
 678
 679 /*
 680  * In 100 and 200 MHz mode, only a single pin rising/falling can be
 681  * set as trigger. In other modes, two rising/falling triggers can be set,
 682  * in addition to value/mask trigger for any number of probes.
 683  *
 684  * The Sigma supports complex triggers using boolean expressions, but this
 685  * has not been implemented yet.
 686  */
 687 static int configure_probes(const struct sr_dev_inst *sdi)
 688 {
 689         struct dev_context *devc = sdi->priv;
 690         const struct sr_probe *probe;
 691         const GSList *l;
 692         int trigger_set = 0;
 693         int probebit;
 694
 695         memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
 696
 697         for (l = sdi->probes; l; l = l->next) {
 698                 probe = (struct sr_probe *)l->data;
 699                 probebit = 1 << (probe->index);
 700
 701                 if (!probe->enabled || !probe->trigger)
 702                         continue;
 703
 704                 if (devc->cur_samplerate >= SR_MHZ(100)) {
 705                         /* Fast trigger support. */
 706                         if (trigger_set) {
 707                                 sr_err("Only a single pin trigger in 100 and "
 708                                        "200MHz mode is supported.");
 709                                 return SR_ERR;
 710                         }
 711                         if (probe->trigger[0] == 'f')
 712                                 devc->trigger.fallingmask |= probebit;
 713                         else if (probe->trigger[0] == 'r')
 714                                 devc->trigger.risingmask |= probebit;
 715                         else {
 716                                 sr_err("Only rising/falling trigger in 100 "
 717                                        "and 200MHz mode is supported.");
 718                                 return SR_ERR;
 719                         }
 720
 721                         ++trigger_set;
 722                 } else {
 723                         /* Simple trigger support (event). */
 724                         if (probe->trigger[0] == '1') {
 725                                 devc->trigger.simplevalue |= probebit;
 726                                 devc->trigger.simplemask |= probebit;
 727                         }
 728                         else if (probe->trigger[0] == '0') {
 729                                 devc->trigger.simplevalue &= ~probebit;
 730                                 devc->trigger.simplemask |= probebit;
 731                         }
 732                         else if (probe->trigger[0] == 'f') {
 733                                 devc->trigger.fallingmask |= probebit;
 734                                 ++trigger_set;
 735                         }
 736                         else if (probe->trigger[0] == 'r') {
 737                                 devc->trigger.risingmask |= probebit;
 738                                 ++trigger_set;
 739                         }
 740
 741                         /*
 742                          * Actually, Sigma supports 2 rising/falling triggers,
 743                          * but they are ORed and the current trigger syntax
 744                          * does not permit ORed triggers.
 745                          */
 746                         if (trigger_set > 1) {
 747                                 sr_err("Only 1 rising/falling trigger "
 748                                        "is supported.");
 749                                 return SR_ERR;
 750                         }
 751                 }
 752
 753                 if (trigger_set)
 754                         devc->use_triggers = 1;
 755         }
 756
 757         return SR_OK;
 758 }
 759
 760 static int hw_dev_close(struct sr_dev_inst *sdi)
 761 {
 762         struct dev_context *devc;
 763
 764         if (!(devc = sdi->priv)) {
 765                 sr_err("%s: sdi->priv was NULL", __func__);
 766                 return SR_ERR_BUG;
 767         }
 768
 769         /* TODO */
 770         if (sdi->status == SR_ST_ACTIVE)
 771                 ftdi_usb_close(&devc->ftdic);
 772
 773         sdi->status = SR_ST_INACTIVE;
 774
 775         return SR_OK;
 776 }
 777
 778 static int hw_cleanup(void)
 779 {
 780         if (!di->priv)
 781                 return SR_OK;
 782
 783         clear_instances();
 784
 785         return SR_OK;
 786 }
 787
 788 static int hw_info_get(int info_id, const void **data,
 789                        const struct sr_dev_inst *sdi)
 790 {
 791         struct dev_context *devc;
 792
 793         switch (info_id) {
 794         case SR_DI_HWCAPS:
 795                 *data = hwcaps;
 796                 break;
 797         case SR_DI_NUM_PROBES:
 798                 *data = GINT_TO_POINTER(NUM_PROBES);
 799                 break;
 800         case SR_DI_PROBE_NAMES:
 801                 *data = probe_names;
 802                 break;
 803         case SR_DI_SAMPLERATES:
 804                 *data = &samplerates;
 805                 break;
 806         case SR_DI_TRIGGER_TYPES:
 807                 *data = (char *)TRIGGER_TYPES;
 808                 break;
 809         case SR_DI_CUR_SAMPLERATE:
 810                 if (sdi) {
 811                         devc = sdi->priv;
 812                         *data = &devc->cur_samplerate;
 813                 } else
 814                         return SR_ERR;
 815                 break;
 816         default:
 817                 return SR_ERR_ARG;
 818         }
 819
 820         return SR_OK;
 821 }
 822
 823 static int hw_dev_config_set(const struct sr_dev_inst *sdi, int hwcap,
 824                              const void *value)
 825 {
 826         struct dev_context *devc;
 827         int ret;
 828
 829         devc = sdi->priv;
 830
 831         if (hwcap == SR_HWCAP_SAMPLERATE) {
 832                 ret = set_samplerate(sdi, *(const uint64_t *)value);
 833         } else if (hwcap == SR_HWCAP_LIMIT_MSEC) {
 834                 devc->limit_msec = *(const uint64_t *)value;
 835                 if (devc->limit_msec > 0)
 836                         ret = SR_OK;
 837                 else
 838                         ret = SR_ERR;
 839         } else if (hwcap == SR_HWCAP_CAPTURE_RATIO) {
 840                 devc->capture_ratio = *(const uint64_t *)value;
 841                 if (devc->capture_ratio < 0 || devc->capture_ratio > 100)
 842                         ret = SR_ERR;
 843                 else
 844                         ret = SR_OK;
 845         } else {
 846                 ret = SR_ERR;
 847         }
 848
 849         return ret;
 850 }
 851
 852 /* Software trigger to determine exact trigger position. */
 853 static int get_trigger_offset(uint16_t *samples, uint16_t last_sample,
 854                               struct sigma_trigger *t)
 855 {
 856         int i;
 857
 858         for (i = 0; i < 8; ++i) {
 859                 if (i > 0)
 860                         last_sample = samples[i-1];
 861
 862                 /* Simple triggers. */
 863                 if ((samples[i] & t->simplemask) != t->simplevalue)
 864                         continue;
 865
 866                 /* Rising edge. */
 867                 if ((last_sample & t->risingmask) != 0 || (samples[i] &
 868                     t->risingmask) != t->risingmask)
 869                         continue;
 870
 871                 /* Falling edge. */
 872                 if ((last_sample & t->fallingmask) != t->fallingmask ||
 873                     (samples[i] & t->fallingmask) != 0)
 874                         continue;
 875
 876                 break;
 877         }
 878
 879         /* If we did not match, return original trigger pos. */
 880         return i & 0x7;
 881 }
 882
 883 /*
 884  * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
 885  * Each event is 20ns apart, and can contain multiple samples.
 886  *
 887  * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
 888  * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
 889  * For 50 MHz and below, events contain one sample for each channel,
 890  * spread 20 ns apart.
 891  */
 892 static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
 893                            uint16_t *lastsample, int triggerpos,
 894                            uint16_t limit_chunk, void *cb_data)
 895 {
 896         struct sr_dev_inst *sdi = cb_data;
 897         struct dev_context *devc = sdi->priv;
 898         uint16_t tsdiff, ts;
 899         uint16_t samples[65536 * devc->samples_per_event];
 900         struct sr_datafeed_packet packet;
 901         struct sr_datafeed_logic logic;
 902         int i, j, k, l, numpad, tosend;
 903         size_t n = 0, sent = 0;
 904         int clustersize = EVENTS_PER_CLUSTER * devc->samples_per_event;
 905         uint16_t *event;
 906         uint16_t cur_sample;
 907         int triggerts = -1;
 908
 909         /* Check if trigger is in this chunk. */
 910         if (triggerpos != -1) {
 911                 if (devc->cur_samplerate <= SR_MHZ(50))
 912                         triggerpos -= EVENTS_PER_CLUSTER - 1;
 913
 914                 if (triggerpos < 0)
 915                         triggerpos = 0;
 916
 917                 /* Find in which cluster the trigger occured. */
 918                 triggerts = triggerpos / 7;
 919         }
 920
 921         /* For each ts. */
 922         for (i = 0; i < 64; ++i) {
 923                 ts = *(uint16_t *) &buf[i * 16];
 924                 tsdiff = ts - *lastts;
 925                 *lastts = ts;
 926
 927                 /* Decode partial chunk. */
 928                 if (limit_chunk && ts > limit_chunk)
 929                         return SR_OK;
 930
 931                 /* Pad last sample up to current point. */
 932                 numpad = tsdiff * devc->samples_per_event - clustersize;
 933                 if (numpad > 0) {
 934                         for (j = 0; j < numpad; ++j)
 935                                 samples[j] = *lastsample;
 936
 937                         n = numpad;
 938                 }
 939
 940                 /* Send samples between previous and this timestamp to sigrok. */
 941                 sent = 0;
 942                 while (sent < n) {
 943                         tosend = MIN(2048, n - sent);
 944
 945                         packet.type = SR_DF_LOGIC;
 946                         packet.payload = &logic;
 947                         logic.length = tosend * sizeof(uint16_t);
 948                         logic.unitsize = 2;
 949                         logic.data = samples + sent;
 950                         sr_session_send(devc->session_dev_id, &packet);
 951
 952                         sent += tosend;
 953                 }
 954                 n = 0;
 955
 956                 event = (uint16_t *) &buf[i * 16 + 2];
 957                 cur_sample = 0;
 958
 959                 /* For each event in cluster. */
 960                 for (j = 0; j < 7; ++j) {
 961
 962                         /* For each sample in event. */
 963                         for (k = 0; k < devc->samples_per_event; ++k) {
 964                                 cur_sample = 0;
 965
 966                                 /* For each probe. */
 967                                 for (l = 0; l < devc->num_probes; ++l)
 968                                         cur_sample |= (!!(event[j] & (1 << (l *
 969                                            devc->samples_per_event + k)))) << l;
 970
 971                                 samples[n++] = cur_sample;
 972                         }
 973                 }
 974
 975                 /* Send data up to trigger point (if triggered). */
 976                 sent = 0;
 977                 if (i == triggerts) {
 978                         /*
 979                          * Trigger is not always accurate to sample because of
 980                          * pipeline delay. However, it always triggers before
 981                          * the actual event. We therefore look at the next
 982                          * samples to pinpoint the exact position of the trigger.
 983                          */
 984                         tosend = get_trigger_offset(samples, *lastsample,
 985                                                     &devc->trigger);
 986
 987                         if (tosend > 0) {
 988                                 packet.type = SR_DF_LOGIC;
 989                                 packet.payload = &logic;
 990                                 logic.length = tosend * sizeof(uint16_t);
 991                                 logic.unitsize = 2;
 992                                 logic.data = samples;
 993                                 sr_session_send(devc->session_dev_id, &packet);
 994
 995                                 sent += tosend;
 996                         }
 997
 998                         /* Only send trigger if explicitly enabled. */
 999                         if (devc->use_triggers) {
1000                                 packet.type = SR_DF_TRIGGER;
1001                                 sr_session_send(devc->session_dev_id, &packet);
1002                         }
1003                 }
1004
1005                 /* Send rest of the chunk to sigrok. */
1006                 tosend = n - sent;
1007
1008                 if (tosend > 0) {
1009                         packet.type = SR_DF_LOGIC;
1010                         packet.payload = &logic;
1011                         logic.length = tosend * sizeof(uint16_t);
1012                         logic.unitsize = 2;
1013                         logic.data = samples + sent;
1014                         sr_session_send(devc->session_dev_id, &packet);
1015                 }
1016
1017                 *lastsample = samples[n - 1];
1018         }
1019
1020         return SR_OK;
1021 }
1022
1023 static int receive_data(int fd, int revents, void *cb_data)
1024 {
1025         struct sr_dev_inst *sdi = cb_data;
1026         struct dev_context *devc = sdi->priv;
1027         struct sr_datafeed_packet packet;
1028         const int chunks_per_read = 32;
1029         unsigned char buf[chunks_per_read * CHUNK_SIZE];
1030         int bufsz, numchunks, i, newchunks;
1031         uint64_t running_msec;
1032         struct timeval tv;
1033
1034         (void)fd;
1035         (void)revents;
1036
1037         /* Get the current position. */
1038         sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
1039
1040         numchunks = (devc->state.stoppos + 511) / 512;
1041
1042         if (devc->state.state == SIGMA_IDLE)
1043                 return TRUE;
1044
1045         if (devc->state.state == SIGMA_CAPTURE) {
1046                 /* Check if the timer has expired, or memory is full. */
1047                 gettimeofday(&tv, 0);
1048                 running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 +
1049                         (tv.tv_usec - devc->start_tv.tv_usec) / 1000;
1050
1051                 if (running_msec < devc->limit_msec && numchunks < 32767)
1052                         return TRUE; /* While capturing... */
1053                 else
1054                         hw_dev_acquisition_stop(sdi, sdi);
1055
1056         }
1057
1058         if (devc->state.state == SIGMA_DOWNLOAD) {
1059                 if (devc->state.chunks_downloaded >= numchunks) {
1060                         /* End of samples. */
1061                         packet.type = SR_DF_END;
1062                         sr_session_send(devc->session_dev_id, &packet);
1063
1064                         devc->state.state = SIGMA_IDLE;
1065
1066                         return TRUE;
1067                 }
1068
1069                 newchunks = MIN(chunks_per_read,
1070                                 numchunks - devc->state.chunks_downloaded);
1071
1072                 sr_info("Downloading sample data: %.0f %%.",
1073                         100.0 * devc->state.chunks_downloaded / numchunks);
1074
1075                 bufsz = sigma_read_dram(devc->state.chunks_downloaded,
1076                                         newchunks, buf, devc);
1077                 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1078                 (void)bufsz;
1079
1080                 /* Find first ts. */
1081                 if (devc->state.chunks_downloaded == 0) {
1082                         devc->state.lastts = *(uint16_t *) buf - 1;
1083                         devc->state.lastsample = 0;
1084                 }
1085
1086                 /* Decode chunks and send them to sigrok. */
1087                 for (i = 0; i < newchunks; ++i) {
1088                         int limit_chunk = 0;
1089
1090                         /* The last chunk may potentially be only in part. */
1091                         if (devc->state.chunks_downloaded == numchunks - 1) {
1092                                 /* Find the last valid timestamp */
1093                                 limit_chunk = devc->state.stoppos % 512 + devc->state.lastts;
1094                         }
1095
1096                         if (devc->state.chunks_downloaded + i == devc->state.triggerchunk)
1097                                 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1098                                                 &devc->state.lastts,
1099                                                 &devc->state.lastsample,
1100                                                 devc->state.triggerpos & 0x1ff,
1101                                                 limit_chunk, sdi);
1102                         else
1103                                 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1104                                                 &devc->state.lastts,
1105                                                 &devc->state.lastsample,
1106                                                 -1, limit_chunk, sdi);
1107
1108                         ++devc->state.chunks_downloaded;
1109                 }
1110         }
1111
1112         return TRUE;
1113 }
1114
1115 /* Build a LUT entry used by the trigger functions. */
1116 static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1117 {
1118         int i, j, k, bit;
1119
1120         /* For each quad probe. */
1121         for (i = 0; i < 4; ++i) {
1122                 entry[i] = 0xffff;
1123
1124                 /* For each bit in LUT. */
1125                 for (j = 0; j < 16; ++j)
1126
1127                         /* For each probe in quad. */
1128                         for (k = 0; k < 4; ++k) {
1129                                 bit = 1 << (i * 4 + k);
1130
1131                                 /* Set bit in entry */
1132                                 if ((mask & bit) &&
1133                                     ((!(value & bit)) !=
1134                                     (!(j & (1 << k)))))
1135                                         entry[i] &= ~(1 << j);
1136                         }
1137         }
1138 }
1139
1140 /* Add a logical function to LUT mask. */
1141 static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1142                                  int index, int neg, uint16_t *mask)
1143 {
1144         int i, j;
1145         int x[2][2], tmp, a, b, aset, bset, rset;
1146
1147         memset(x, 0, 4 * sizeof(int));
1148
1149         /* Trigger detect condition. */
1150         switch (oper) {
1151         case OP_LEVEL:
1152                 x[0][1] = 1;
1153                 x[1][1] = 1;
1154                 break;
1155         case OP_NOT:
1156                 x[0][0] = 1;
1157                 x[1][0] = 1;
1158                 break;
1159         case OP_RISE:
1160                 x[0][1] = 1;
1161                 break;
1162         case OP_FALL:
1163                 x[1][0] = 1;
1164                 break;
1165         case OP_RISEFALL:
1166                 x[0][1] = 1;
1167                 x[1][0] = 1;
1168                 break;
1169         case OP_NOTRISE:
1170                 x[1][1] = 1;
1171                 x[0][0] = 1;
1172                 x[1][0] = 1;
1173                 break;
1174         case OP_NOTFALL:
1175                 x[1][1] = 1;
1176                 x[0][0] = 1;
1177                 x[0][1] = 1;
1178                 break;
1179         case OP_NOTRISEFALL:
1180                 x[1][1] = 1;
1181                 x[0][0] = 1;
1182                 break;
1183         }
1184
1185         /* Transpose if neg is set. */
1186         if (neg) {
1187                 for (i = 0; i < 2; ++i) {
1188                         for (j = 0; j < 2; ++j) {
1189                                 tmp = x[i][j];
1190                                 x[i][j] = x[1-i][1-j];
1191                                 x[1-i][1-j] = tmp;
1192                         }
1193                 }
1194         }
1195
1196         /* Update mask with function. */
1197         for (i = 0; i < 16; ++i) {
1198                 a = (i >> (2 * index + 0)) & 1;
1199                 b = (i >> (2 * index + 1)) & 1;
1200
1201                 aset = (*mask >> i) & 1;
1202                 bset = x[b][a];
1203
1204                 if (func == FUNC_AND || func == FUNC_NAND)
1205                         rset = aset & bset;
1206                 else if (func == FUNC_OR || func == FUNC_NOR)
1207                         rset = aset | bset;
1208                 else if (func == FUNC_XOR || func == FUNC_NXOR)
1209                         rset = aset ^ bset;
1210
1211                 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1212                         rset = !rset;
1213
1214                 *mask &= ~(1 << i);
1215
1216                 if (rset)
1217                         *mask |= 1 << i;
1218         }
1219 }
1220
1221 /*
1222  * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1223  * simple pin change and state triggers. Only two transitions (rise/fall) can be
1224  * set at any time, but a full mask and value can be set (0/1).
1225  */
1226 static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc)
1227 {
1228         int i,j;
1229         uint16_t masks[2] = { 0, 0 };
1230
1231         memset(lut, 0, sizeof(struct triggerlut));
1232
1233         /* Contant for simple triggers. */
1234         lut->m4 = 0xa000;
1235
1236         /* Value/mask trigger support. */
1237         build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask,
1238                         lut->m2d);
1239
1240         /* Rise/fall trigger support. */
1241         for (i = 0, j = 0; i < 16; ++i) {
1242                 if (devc->trigger.risingmask & (1 << i) ||
1243                     devc->trigger.fallingmask & (1 << i))
1244                         masks[j++] = 1 << i;
1245         }
1246
1247         build_lut_entry(masks[0], masks[0], lut->m0d);
1248         build_lut_entry(masks[1], masks[1], lut->m1d);
1249
1250         /* Add glue logic */
1251         if (masks[0] || masks[1]) {
1252                 /* Transition trigger. */
1253                 if (masks[0] & devc->trigger.risingmask)
1254                         add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1255                 if (masks[0] & devc->trigger.fallingmask)
1256                         add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1257                 if (masks[1] & devc->trigger.risingmask)
1258                         add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1259                 if (masks[1] & devc->trigger.fallingmask)
1260                         add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1261         } else {
1262                 /* Only value/mask trigger. */
1263                 lut->m3 = 0xffff;
1264         }
1265
1266         /* Triggertype: event. */
1267         lut->params.selres = 3;
1268
1269         return SR_OK;
1270 }
1271
1272 static int hw_dev_acquisition_start(const struct sr_dev_inst *sdi,
1273                 void *cb_data)
1274 {
1275         struct dev_context *devc;
1276         struct sr_datafeed_packet *packet;
1277         struct sr_datafeed_header *header;
1278         struct sr_datafeed_meta_logic meta;
1279         struct clockselect_50 clockselect;
1280         int frac, triggerpin, ret;
1281         uint8_t triggerselect;
1282         struct triggerinout triggerinout_conf;
1283         struct triggerlut lut;
1284
1285         devc = sdi->priv;
1286
1287         if (configure_probes(sdi) != SR_OK) {
1288                 sr_err("Failed to configure probes.");
1289                 return SR_ERR;
1290         }
1291
1292         /* If the samplerate has not been set, default to 200 kHz. */
1293         if (devc->cur_firmware == -1) {
1294                 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1295                         return ret;
1296         }
1297
1298         /* Enter trigger programming mode. */
1299         sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc);
1300
1301         /* 100 and 200 MHz mode. */
1302         if (devc->cur_samplerate >= SR_MHZ(100)) {
1303                 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc);
1304
1305                 /* Find which pin to trigger on from mask. */
1306                 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1307                         if ((devc->trigger.risingmask | devc->trigger.fallingmask) &
1308                             (1 << triggerpin))
1309                                 break;
1310
1311                 /* Set trigger pin and light LED on trigger. */
1312                 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1313
1314                 /* Default rising edge. */
1315                 if (devc->trigger.fallingmask)
1316                         triggerselect |= 1 << 3;
1317
1318         /* All other modes. */
1319         } else if (devc->cur_samplerate <= SR_MHZ(50)) {
1320                 build_basic_trigger(&lut, devc);
1321
1322                 sigma_write_trigger_lut(&lut, devc);
1323
1324                 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1325         }
1326
1327         /* Setup trigger in and out pins to default values. */
1328         memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1329         triggerinout_conf.trgout_bytrigger = 1;
1330         triggerinout_conf.trgout_enable = 1;
1331
1332         sigma_write_register(WRITE_TRIGGER_OPTION,
1333                              (uint8_t *) &triggerinout_conf,
1334                              sizeof(struct triggerinout), devc);
1335
1336         /* Go back to normal mode. */
1337         sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc);
1338
1339         /* Set clock select register. */
1340         if (devc->cur_samplerate == SR_MHZ(200))
1341                 /* Enable 4 probes. */
1342                 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc);
1343         else if (devc->cur_samplerate == SR_MHZ(100))
1344                 /* Enable 8 probes. */
1345                 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc);
1346         else {
1347                 /*
1348                  * 50 MHz mode (or fraction thereof). Any fraction down to
1349                  * 50 MHz / 256 can be used, but is not supported by sigrok API.
1350                  */
1351                 frac = SR_MHZ(50) / devc->cur_samplerate - 1;
1352
1353                 clockselect.async = 0;
1354                 clockselect.fraction = frac;
1355                 clockselect.disabled_probes = 0;
1356
1357                 sigma_write_register(WRITE_CLOCK_SELECT,
1358                                      (uint8_t *) &clockselect,
1359                                      sizeof(clockselect), devc);
1360         }
1361
1362         /* Setup maximum post trigger time. */
1363         sigma_set_register(WRITE_POST_TRIGGER,
1364                            (devc->capture_ratio * 255) / 100, devc);
1365
1366         /* Start acqusition. */
1367         gettimeofday(&devc->start_tv, 0);
1368         sigma_set_register(WRITE_MODE, 0x0d, devc);
1369
1370         devc->session_dev_id = cb_data;
1371
1372         if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) {
1373                 sr_err("%s: packet malloc failed.", __func__);
1374                 return SR_ERR_MALLOC;
1375         }
1376
1377         if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) {
1378                 sr_err("%s: header malloc failed.", __func__);
1379                 return SR_ERR_MALLOC;
1380         }
1381
1382         /* Send header packet to the session bus. */
1383         packet->type = SR_DF_HEADER;
1384         packet->payload = header;
1385         header->feed_version = 1;
1386         gettimeofday(&header->starttime, NULL);
1387         sr_session_send(devc->session_dev_id, packet);
1388
1389         /* Send metadata about the SR_DF_LOGIC packets to come. */
1390         packet->type = SR_DF_META_LOGIC;
1391         packet->payload = &meta;
1392         meta.samplerate = devc->cur_samplerate;
1393         meta.num_probes = devc->num_probes;
1394         sr_session_send(devc->session_dev_id, packet);
1395
1396         /* Add capture source. */
1397         sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi);
1398
1399         g_free(header);
1400         g_free(packet);
1401
1402         devc->state.state = SIGMA_CAPTURE;
1403
1404         return SR_OK;
1405 }
1406
1407 static int hw_dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
1408 {
1409         struct dev_context *devc;
1410         uint8_t modestatus;
1411
1412         (void)cb_data;
1413
1414         sr_source_remove(0);
1415
1416         if (!(devc = sdi->priv)) {
1417                 sr_err("%s: sdi->priv was NULL", __func__);
1418                 return SR_ERR_BUG;
1419         }
1420
1421         /* Stop acquisition. */
1422         sigma_set_register(WRITE_MODE, 0x11, devc);
1423
1424         /* Set SDRAM Read Enable. */
1425         sigma_set_register(WRITE_MODE, 0x02, devc);
1426
1427         /* Get the current position. */
1428         sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
1429
1430         /* Check if trigger has fired. */
1431         modestatus = sigma_get_register(READ_MODE, devc);
1432         if (modestatus & 0x20)
1433                 devc->state.triggerchunk = devc->state.triggerpos / 512;
1434         else
1435                 devc->state.triggerchunk = -1;
1436
1437         devc->state.chunks_downloaded = 0;
1438
1439         devc->state.state = SIGMA_DOWNLOAD;
1440
1441         return SR_OK;
1442 }
1443
1444 SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
1445         .name = "asix-sigma",
1446         .longname = "ASIX SIGMA/SIGMA2",
1447         .api_version = 1,
1448         .init = hw_init,
1449         .cleanup = hw_cleanup,
1450         .scan = hw_scan,
1451         .dev_list = hw_dev_list,
1452         .dev_clear = clear_instances,
1453         .dev_open = hw_dev_open,
1454         .dev_close = hw_dev_close,
1455         .info_get = hw_info_get,
1456         .dev_config_set = hw_dev_config_set,
1457         .dev_acquisition_start = hw_dev_acquisition_start,
1458         .dev_acquisition_stop = hw_dev_acquisition_stop,
1459         .priv = NULL,
1460 };