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1/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2012 Martin Ling <martin-git@earth.li>
5 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
6 * Copyright (C) 2013 Mathias Grimmberger <mgri@zaphod.sax.de>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#include <config.h>
23#include <stdlib.h>
24#include <stdarg.h>
25#include <unistd.h>
26#include <errno.h>
27#include <string.h>
28#include <math.h>
29#include <ctype.h>
30#include <time.h>
31#include <glib.h>
32#include <libsigrok/libsigrok.h>
33#include "libsigrok-internal.h"
34#include "scpi.h"
35#include "protocol.h"
36
37/*
38 * This is a unified protocol driver for the DS1000 and DS2000 series.
39 *
40 * DS1000 support tested with a Rigol DS1102D.
41 *
42 * DS2000 support tested with a Rigol DS2072 using firmware version 01.01.00.02.
43 *
44 * The Rigol DS2000 series scopes try to adhere to the IEEE 488.2 (I think)
45 * standard. If you want to read it - it costs real money...
46 *
47 * Every response from the scope has a linefeed appended because the
48 * standard says so. In principle this could be ignored because sending the
49 * next command clears the output queue of the scope. This driver tries to
50 * avoid doing that because it may cause an error being generated inside the
51 * scope and who knows what bugs the firmware has WRT this.
52 *
53 * Waveform data is transferred in a format called "arbitrary block program
54 * data" specified in IEEE 488.2. See Agilents programming manuals for their
55 * 2000/3000 series scopes for a nice description.
56 *
57 * Each data block from the scope has a header, e.g. "#900000001400".
58 * The '#' marks the start of a block.
59 * Next is one ASCII decimal digit between 1 and 9, this gives the number of
60 * ASCII decimal digits following.
61 * Last are the ASCII decimal digits giving the number of bytes (not
62 * samples!) in the block.
63 *
64 * After this header as many data bytes as indicated follow.
65 *
66 * Each data block has a trailing linefeed too.
67 */
68
69static int parse_int(const char *str, int *ret)
70{
71 char *e;
72 long tmp;
73
74 errno = 0;
75 tmp = strtol(str, &e, 10);
76 if (e == str || *e != '\0') {
77 sr_dbg("Failed to parse integer: '%s'", str);
78 return SR_ERR;
79 }
80 if (errno) {
81 sr_dbg("Failed to parse integer: '%s', numerical overflow", str);
82 return SR_ERR;
83 }
84 if (tmp > INT_MAX || tmp < INT_MIN) {
85 sr_dbg("Failed to parse integer: '%s', value to large/small", str);
86 return SR_ERR;
87 }
88
89 *ret = (int)tmp;
90 return SR_OK;
91}
92
93/* Set the next event to wait for in rigol_ds_receive */
94static void rigol_ds_set_wait_event(struct dev_context *devc, enum wait_events event)
95{
96 if (event == WAIT_STOP)
97 devc->wait_status = 2;
98 else
99 devc->wait_status = 1;
100 devc->wait_event = event;
101}
102
103/*
104 * Waiting for a event will return a timeout after 2 to 3 seconds in order
105 * to not block the application.
106 */
107static int rigol_ds_event_wait(const struct sr_dev_inst *sdi, char status1, char status2)
108{
109 char *buf;
110 struct dev_context *devc;
111 time_t start;
112
113 if (!(devc = sdi->priv))
114 return SR_ERR;
115
116 start = time(NULL);
117
118 /*
119 * Trigger status may return:
120 * "TD" or "T'D" - triggered
121 * "AUTO" - autotriggered
122 * "RUN" - running
123 * "WAIT" - waiting for trigger
124 * "STOP" - stopped
125 */
126
127 if (devc->wait_status == 1) {
128 do {
129 if (time(NULL) - start >= 3) {
130 sr_dbg("Timeout waiting for trigger");
131 return SR_ERR_TIMEOUT;
132 }
133
134 if (sr_scpi_get_string(sdi->conn, ":TRIG:STAT?", &buf) != SR_OK)
135 return SR_ERR;
136 } while (buf[0] == status1 || buf[0] == status2);
137
138 devc->wait_status = 2;
139 }
140 if (devc->wait_status == 2) {
141 do {
142 if (time(NULL) - start >= 3) {
143 sr_dbg("Timeout waiting for trigger");
144 return SR_ERR_TIMEOUT;
145 }
146
147 if (sr_scpi_get_string(sdi->conn, ":TRIG:STAT?", &buf) != SR_OK)
148 return SR_ERR;
149 } while (buf[0] != status1 && buf[0] != status2);
150
151 rigol_ds_set_wait_event(devc, WAIT_NONE);
152 }
153
154 return SR_OK;
155}
156
157/*
158 * For live capture we need to wait for a new trigger event to ensure that
159 * sample data is not returned twice.
160 *
161 * Unfortunately this will never really work because for sufficiently fast
162 * timebases and trigger rates it just can't catch the status changes.
163 *
164 * What would be needed is a trigger event register with autoreset like the
165 * Agilents have. The Rigols don't seem to have anything like this.
166 *
167 * The workaround is to only wait for the trigger when the timebase is slow
168 * enough. Of course this means that for faster timebases sample data can be
169 * returned multiple times, this effect is mitigated somewhat by sleeping
170 * for about one sweep time in that case.
171 */
172static int rigol_ds_trigger_wait(const struct sr_dev_inst *sdi)
173{
174 struct dev_context *devc;
175 long s;
176
177 if (!(devc = sdi->priv))
178 return SR_ERR;
179
180 /*
181 * If timebase < 50 msecs/DIV just sleep about one sweep time except
182 * for really fast sweeps.
183 */
184 if (devc->timebase < 0.0499) {
185 if (devc->timebase > 0.99e-6) {
186 /*
187 * Timebase * num hor. divs * 85(%) * 1e6(usecs) / 100
188 * -> 85 percent of sweep time
189 */
190 s = (devc->timebase * devc->model->series->num_horizontal_divs
191 * 85e6) / 100L;
192 sr_spew("Sleeping for %ld usecs instead of trigger-wait", s);
193 g_usleep(s);
194 }
195 rigol_ds_set_wait_event(devc, WAIT_NONE);
196 return SR_OK;
197 } else {
198 return rigol_ds_event_wait(sdi, 'T', 'A');
199 }
200}
201
202/* Wait for scope to got to "Stop" in single shot mode */
203static int rigol_ds_stop_wait(const struct sr_dev_inst *sdi)
204{
205 return rigol_ds_event_wait(sdi, 'S', 'S');
206}
207
208/* Check that a single shot acquisition actually succeeded on the DS2000 */
209static int rigol_ds_check_stop(const struct sr_dev_inst *sdi)
210{
211 struct dev_context *devc;
212 struct sr_channel *ch;
213 int tmp;
214
215 if (!(devc = sdi->priv))
216 return SR_ERR;
217
218 ch = devc->channel_entry->data;
219
220 if (devc->model->series->protocol != PROTOCOL_V3)
221 return SR_OK;
222
223 if (ch->type == SR_CHANNEL_LOGIC) {
224 if (rigol_ds_config_set(sdi, ":WAV:SOUR LA") != SR_OK)
225 return SR_ERR;
226 } else {
227 if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d",
228 ch->index + 1) != SR_OK)
229 return SR_ERR;
230 }
231 /* Check that the number of samples will be accepted */
232 if (rigol_ds_config_set(sdi, ":WAV:POIN %d",
233 ch->type == SR_CHANNEL_LOGIC ?
234 devc->digital_frame_size :
235 devc->analog_frame_size) != SR_OK)
236 return SR_ERR;
237 if (sr_scpi_get_int(sdi->conn, "*ESR?", &tmp) != SR_OK)
238 return SR_ERR;
239 /*
240 * If we get an "Execution error" the scope went from "Single" to
241 * "Stop" without actually triggering. There is no waveform
242 * displayed and trying to download one will fail - the scope thinks
243 * it has 1400 samples (like display memory) and the driver thinks
244 * it has a different number of samples.
245 *
246 * In that case just try to capture something again. Might still
247 * fail in interesting ways.
248 *
249 * Ain't firmware fun?
250 */
251 if (tmp & 0x10) {
252 sr_warn("Single shot acquisition failed, retrying...");
253 /* Sleep a bit, otherwise the single shot will often fail */
254 g_usleep(500 * 1000);
255 rigol_ds_config_set(sdi, ":SING");
256 rigol_ds_set_wait_event(devc, WAIT_STOP);
257 return SR_ERR;
258 }
259
260 return SR_OK;
261}
262
263/* Wait for enough data becoming available in scope output buffer */
264static int rigol_ds_block_wait(const struct sr_dev_inst *sdi)
265{
266 char *buf;
267 struct dev_context *devc;
268 time_t start;
269 int len;
270
271 if (!(devc = sdi->priv))
272 return SR_ERR;
273
274 if (devc->model->series->protocol == PROTOCOL_V3) {
275
276 start = time(NULL);
277
278 do {
279 if (time(NULL) - start >= 3) {
280 sr_dbg("Timeout waiting for data block");
281 return SR_ERR_TIMEOUT;
282 }
283
284 /*
285 * The scope copies data really slowly from sample
286 * memory to its output buffer, so try not to bother
287 * it too much with SCPI requests but don't wait too
288 * long for short sample frame sizes.
289 */
290 g_usleep(devc->analog_frame_size < (15 * 1000) ? (100 * 1000) : (1000 * 1000));
291
292 /* "READ,nnnn" (still working) or "IDLE,nnnn" (finished) */
293 if (sr_scpi_get_string(sdi->conn, ":WAV:STAT?", &buf) != SR_OK)
294 return SR_ERR;
295
296 if (parse_int(buf + 5, &len) != SR_OK)
297 return SR_ERR;
298 } while (buf[0] == 'R' && len < (1000 * 1000));
299 }
300
301 rigol_ds_set_wait_event(devc, WAIT_NONE);
302
303 return SR_OK;
304}
305
306/* Send a configuration setting. */
307SR_PRIV int rigol_ds_config_set(const struct sr_dev_inst *sdi, const char *format, ...)
308{
309 struct dev_context *devc = sdi->priv;
310 va_list args;
311 int ret;
312
313 va_start(args, format);
314 ret = sr_scpi_send_variadic(sdi->conn, format, args);
315 va_end(args);
316
317 if (ret != SR_OK)
318 return SR_ERR;
319
320 if (devc->model->series->protocol == PROTOCOL_V2) {
321 /* The DS1000 series needs this stupid delay, *OPC? doesn't work. */
322 sr_spew("delay %dms", 100);
323 g_usleep(100 * 1000);
324 return SR_OK;
325 } else {
326 return sr_scpi_get_opc(sdi->conn);
327 }
328}
329
330/* Start capturing a new frameset */
331SR_PRIV int rigol_ds_capture_start(const struct sr_dev_inst *sdi)
332{
333 struct dev_context *devc;
334 gchar *trig_mode;
335 unsigned int num_channels, i, j;
336 int buffer_samples;
337
338 if (!(devc = sdi->priv))
339 return SR_ERR;
340
341 const gboolean first_frame = (devc->num_frames == 0);
342
343 uint64_t limit_frames = devc->limit_frames;
344 if (devc->num_frames_segmented != 0 && devc->num_frames_segmented < limit_frames)
345 limit_frames = devc->num_frames_segmented;
346 if (limit_frames == 0)
347 sr_dbg("Starting data capture for frameset %" PRIu64,
348 devc->num_frames + 1);
349 else
350 sr_dbg("Starting data capture for frameset %" PRIu64 " of %"
351 PRIu64, devc->num_frames + 1, limit_frames);
352
353 switch (devc->model->series->protocol) {
354 case PROTOCOL_V1:
355 rigol_ds_set_wait_event(devc, WAIT_TRIGGER);
356 break;
357 case PROTOCOL_V2:
358 if (devc->data_source == DATA_SOURCE_LIVE) {
359 if (rigol_ds_config_set(sdi, ":WAV:POIN:MODE NORMAL") != SR_OK)
360 return SR_ERR;
361 rigol_ds_set_wait_event(devc, WAIT_TRIGGER);
362 } else {
363 if (rigol_ds_config_set(sdi, ":STOP") != SR_OK)
364 return SR_ERR;
365 if (rigol_ds_config_set(sdi, ":WAV:POIN:MODE RAW") != SR_OK)
366 return SR_ERR;
367 if (sr_scpi_get_string(sdi->conn, ":TRIG:MODE?", &trig_mode) != SR_OK)
368 return SR_ERR;
369 if (rigol_ds_config_set(sdi, ":TRIG:%s:SWE SING", trig_mode) != SR_OK)
370 return SR_ERR;
371 if (rigol_ds_config_set(sdi, ":RUN") != SR_OK)
372 return SR_ERR;
373 rigol_ds_set_wait_event(devc, WAIT_STOP);
374 }
375 break;
376 case PROTOCOL_V3:
377 case PROTOCOL_V4:
378 case PROTOCOL_V5:
379 if (first_frame && rigol_ds_config_set(sdi, ":WAV:FORM BYTE") != SR_OK)
380 return SR_ERR;
381 if (devc->data_source == DATA_SOURCE_LIVE) {
382 if (first_frame && rigol_ds_config_set(sdi, ":WAV:MODE NORM") != SR_OK)
383 return SR_ERR;
384 devc->analog_frame_size = devc->model->series->live_samples;
385 devc->digital_frame_size = devc->model->series->live_samples;
386 rigol_ds_set_wait_event(devc, WAIT_TRIGGER);
387 } else {
388 if (devc->model->series->protocol == PROTOCOL_V3) {
389 if (first_frame && rigol_ds_config_set(sdi, ":WAV:MODE RAW") != SR_OK)
390 return SR_ERR;
391 } else if (devc->model->series->protocol >= PROTOCOL_V4) {
392 num_channels = 0;
393
394 /* Channels 3 and 4 are multiplexed with D0-7 and D8-15 */
395 for (i = 0; i < devc->model->analog_channels; i++) {
396 if (devc->analog_channels[i]) {
397 num_channels++;
398 } else if (i >= 2 && devc->model->has_digital) {
399 for (j = 0; j < 8; j++) {
400 if (devc->digital_channels[8 * (i - 2) + j]) {
401 num_channels++;
402 break;
403 }
404 }
405 }
406 }
407
408 buffer_samples = devc->model->series->buffer_samples;
409 if (first_frame && buffer_samples == 0)
410 {
411 /* The DS4000 series does not have a fixed memory depth, it
412 * can be chosen from the menu and also varies with number
413 * of active channels. Retrieve the actual number with the
414 * ACQ:MDEP command. */
415 sr_scpi_get_int(sdi->conn, "ACQ:MDEP?", &buffer_samples);
416 devc->analog_frame_size = devc->digital_frame_size =
417 buffer_samples;
418 }
419 else if (first_frame)
420 {
421 /* The DS1000Z series has a fixed memory depth which we
422 * need to divide correctly according to the number of
423 * active channels. */
424 devc->analog_frame_size = devc->digital_frame_size =
425 num_channels == 1 ?
426 buffer_samples :
427 num_channels == 2 ?
428 buffer_samples / 2 :
429 buffer_samples / 4;
430 }
431 }
432
433 if (devc->data_source == DATA_SOURCE_LIVE && rigol_ds_config_set(sdi, ":SINGL") != SR_OK)
434 return SR_ERR;
435 rigol_ds_set_wait_event(devc, WAIT_STOP);
436 if (devc->data_source == DATA_SOURCE_SEGMENTED &&
437 devc->model->series->protocol <= PROTOCOL_V4)
438 if (rigol_ds_config_set(sdi, "FUNC:WREP:FCUR %d", devc->num_frames + 1) != SR_OK)
439 return SR_ERR;
440 }
441 break;
442 }
443
444 return SR_OK;
445}
446
447/* Start reading data from the current channel */
448SR_PRIV int rigol_ds_channel_start(const struct sr_dev_inst *sdi)
449{
450 struct dev_context *devc;
451 struct sr_channel *ch;
452
453 if (!(devc = sdi->priv))
454 return SR_ERR;
455
456 ch = devc->channel_entry->data;
457
458 sr_dbg("Starting reading data from channel %d", ch->index + 1);
459
460 const gboolean first_frame = (devc->num_frames == 0);
461
462 switch (devc->model->series->protocol) {
463 case PROTOCOL_V1:
464 case PROTOCOL_V2:
465 if (ch->type == SR_CHANNEL_LOGIC) {
466 if (sr_scpi_send(sdi->conn, ":WAV:DATA? DIG") != SR_OK)
467 return SR_ERR;
468 } else {
469 if (sr_scpi_send(sdi->conn, ":WAV:DATA? CHAN%d",
470 ch->index + 1) != SR_OK)
471 return SR_ERR;
472 }
473 rigol_ds_set_wait_event(devc, WAIT_NONE);
474 break;
475 case PROTOCOL_V3:
476 if (ch->type == SR_CHANNEL_LOGIC) {
477 if (rigol_ds_config_set(sdi, ":WAV:SOUR LA") != SR_OK)
478 return SR_ERR;
479 } else {
480 if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d",
481 ch->index + 1) != SR_OK)
482 return SR_ERR;
483 }
484 if (devc->data_source != DATA_SOURCE_LIVE) {
485 if (rigol_ds_config_set(sdi, ":WAV:RES") != SR_OK)
486 return SR_ERR;
487 if (rigol_ds_config_set(sdi, ":WAV:BEG") != SR_OK)
488 return SR_ERR;
489 }
490 break;
491 case PROTOCOL_V4:
492 case PROTOCOL_V5:
493 if (ch->type == SR_CHANNEL_ANALOG) {
494 if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d",
495 ch->index + 1) != SR_OK)
496 return SR_ERR;
497 } else {
498 if (rigol_ds_config_set(sdi, ":WAV:SOUR D%d",
499 ch->index) != SR_OK)
500 return SR_ERR;
501 }
502
503 if (first_frame && rigol_ds_config_set(sdi,
504 devc->data_source == DATA_SOURCE_LIVE ?
505 ":WAV:MODE NORM" :":WAV:MODE RAW") != SR_OK)
506 return SR_ERR;
507
508 if (devc->data_source != DATA_SOURCE_LIVE) {
509 if (rigol_ds_config_set(sdi, ":WAV:RES") != SR_OK)
510 return SR_ERR;
511 }
512 break;
513 }
514
515 if (devc->model->series->protocol >= PROTOCOL_V3 &&
516 ch->type == SR_CHANNEL_ANALOG) {
517 /* Vertical increment. */
518 if (first_frame && sr_scpi_get_float(sdi->conn, ":WAV:YINC?",
519 &devc->vert_inc[ch->index]) != SR_OK)
520 return SR_ERR;
521 /* Vertical origin. */
522 if (first_frame && sr_scpi_get_float(sdi->conn, ":WAV:YOR?",
523 &devc->vert_origin[ch->index]) != SR_OK)
524 return SR_ERR;
525 /* Vertical reference. */
526 if (first_frame && sr_scpi_get_int(sdi->conn, ":WAV:YREF?",
527 &devc->vert_reference[ch->index]) != SR_OK)
528 return SR_ERR;
529 } else if (ch->type == SR_CHANNEL_ANALOG) {
530 devc->vert_inc[ch->index] = devc->vdiv[ch->index] / 25.6;
531 }
532
533 rigol_ds_set_wait_event(devc, WAIT_BLOCK);
534
535 devc->num_channel_bytes = 0;
536 devc->num_header_bytes = 0;
537 devc->num_block_bytes = 0;
538
539 return SR_OK;
540}
541
542/* Read the header of a data block */
543static int rigol_ds_read_header(struct sr_dev_inst *sdi)
544{
545 struct sr_scpi_dev_inst *scpi = sdi->conn;
546 struct dev_context *devc = sdi->priv;
547 char *buf = (char *) devc->buffer;
548 size_t header_length;
549 int ret;
550
551 /* Try to read the hashsign and length digit. */
552 if (devc->num_header_bytes < 2) {
553 ret = sr_scpi_read_data(scpi, buf + devc->num_header_bytes,
554 2 - devc->num_header_bytes);
555 if (ret < 0) {
556 sr_err("Read error while reading data header.");
557 return SR_ERR;
558 }
559 devc->num_header_bytes += ret;
560 }
561
562 if (devc->num_header_bytes < 2)
563 return 0;
564
565 if (buf[0] != '#' || !isdigit(buf[1]) || buf[1] == '0') {
566 sr_err("Received invalid data block header '%c%c'.", buf[0], buf[1]);
567 return SR_ERR;
568 }
569
570 header_length = 2 + buf[1] - '0';
571
572 /* Try to read the length. */
573 if (devc->num_header_bytes < header_length) {
574 ret = sr_scpi_read_data(scpi, buf + devc->num_header_bytes,
575 header_length - devc->num_header_bytes);
576 if (ret < 0) {
577 sr_err("Read error while reading data header.");
578 return SR_ERR;
579 }
580 devc->num_header_bytes += ret;
581 }
582
583 if (devc->num_header_bytes < header_length)
584 return 0;
585
586 /* Read the data length. */
587 buf[header_length] = '\0';
588
589 if (parse_int(buf + 2, &ret) != SR_OK) {
590 sr_err("Received invalid data block length '%s'.", buf + 2);
591 return -1;
592 }
593
594 sr_dbg("Received data block header: '%s' -> block length %d", buf, ret);
595
596 return ret;
597}
598
599SR_PRIV int rigol_ds_receive(int fd, int revents, void *cb_data)
600{
601 struct sr_dev_inst *sdi;
602 struct sr_scpi_dev_inst *scpi;
603 struct dev_context *devc;
604 struct sr_datafeed_packet packet;
605 struct sr_datafeed_analog analog;
606 struct sr_analog_encoding encoding;
607 struct sr_analog_meaning meaning;
608 struct sr_analog_spec spec;
609 struct sr_datafeed_logic logic;
610 double vdiv, offset, origin;
611 int len, i, vref;
612 struct sr_channel *ch;
613 gsize expected_data_bytes;
614
615 (void)fd;
616
617 if (!(sdi = cb_data))
618 return TRUE;
619
620 if (!(devc = sdi->priv))
621 return TRUE;
622
623 scpi = sdi->conn;
624
625 if (!(revents == G_IO_IN || revents == 0))
626 return TRUE;
627
628 const gboolean first_frame = (devc->num_frames == 0);
629
630 switch (devc->wait_event) {
631 case WAIT_NONE:
632 break;
633 case WAIT_TRIGGER:
634 if (rigol_ds_trigger_wait(sdi) != SR_OK)
635 return TRUE;
636 if (rigol_ds_channel_start(sdi) != SR_OK)
637 return TRUE;
638 return TRUE;
639 case WAIT_BLOCK:
640 if (rigol_ds_block_wait(sdi) != SR_OK)
641 return TRUE;
642 break;
643 case WAIT_STOP:
644 if (rigol_ds_stop_wait(sdi) != SR_OK)
645 return TRUE;
646 if (rigol_ds_check_stop(sdi) != SR_OK)
647 return TRUE;
648 if (rigol_ds_channel_start(sdi) != SR_OK)
649 return TRUE;
650 return TRUE;
651 default:
652 sr_err("BUG: Unknown event target encountered");
653 break;
654 }
655
656 ch = devc->channel_entry->data;
657
658 expected_data_bytes = ch->type == SR_CHANNEL_ANALOG ?
659 devc->analog_frame_size : devc->digital_frame_size;
660
661 if (devc->num_block_bytes == 0) {
662 if (devc->model->series->protocol >= PROTOCOL_V4) {
663 if (first_frame && rigol_ds_config_set(sdi, ":WAV:START %d",
664 devc->num_channel_bytes + 1) != SR_OK)
665 return TRUE;
666 if (first_frame && rigol_ds_config_set(sdi, ":WAV:STOP %d",
667 MIN(devc->num_channel_bytes + ACQ_BLOCK_SIZE,
668 devc->analog_frame_size)) != SR_OK)
669 return TRUE;
670 }
671
672 if (devc->model->series->protocol >= PROTOCOL_V3) {
673 if (rigol_ds_config_set(sdi, ":WAV:BEG") != SR_OK)
674 return TRUE;
675 if (sr_scpi_send(sdi->conn, ":WAV:DATA?") != SR_OK)
676 return TRUE;
677 }
678
679 if (sr_scpi_read_begin(scpi) != SR_OK)
680 return TRUE;
681
682 if (devc->format == FORMAT_IEEE488_2) {
683 sr_dbg("New block header expected");
684 len = rigol_ds_read_header(sdi);
685 if (len == 0)
686 /* Still reading the header. */
687 return TRUE;
688 if (len == -1) {
689 sr_err("Error while reading block header, aborting capture.");
690 std_session_send_df_frame_end(sdi);
691 sr_dev_acquisition_stop(sdi);
692 return TRUE;
693 }
694 /* At slow timebases in live capture the DS2072 and
695 * DS1054Z sometimes return "short" data blocks, with
696 * apparently no way to get the rest of the data.
697 * Discard these, the complete data block will appear
698 * eventually.
699 */
700 if (devc->data_source == DATA_SOURCE_LIVE
701 && (unsigned)len < expected_data_bytes) {
702 sr_dbg("Discarding short data block: got %d/%d bytes\n", len, (int)expected_data_bytes);
703 sr_scpi_read_data(scpi, (char *)devc->buffer, len + 1);
704 devc->num_header_bytes = 0;
705 return TRUE;
706 }
707 devc->num_block_bytes = len;
708 } else {
709 devc->num_block_bytes = expected_data_bytes;
710 }
711 devc->num_block_read = 0;
712 }
713
714 len = devc->num_block_bytes - devc->num_block_read;
715 if (len > ACQ_BUFFER_SIZE)
716 len = ACQ_BUFFER_SIZE;
717 sr_dbg("Requesting read of %d bytes", len);
718
719 len = sr_scpi_read_data(scpi, (char *)devc->buffer, len);
720
721 if (len == -1) {
722 sr_err("Error while reading block data, aborting capture.");
723 std_session_send_df_frame_end(sdi);
724 sr_dev_acquisition_stop(sdi);
725 return TRUE;
726 }
727
728 sr_dbg("Received %d bytes.", len);
729
730 devc->num_block_read += len;
731
732 if (ch->type == SR_CHANNEL_ANALOG) {
733 vref = devc->vert_reference[ch->index];
734 vdiv = devc->vert_inc[ch->index];
735 origin = devc->vert_origin[ch->index];
736 offset = devc->vert_offset[ch->index];
737 if (devc->model->series->protocol >= PROTOCOL_V3)
738 for (i = 0; i < len; i++)
739 devc->data[i] = ((int)devc->buffer[i] - vref - origin) * vdiv;
740 else
741 for (i = 0; i < len; i++)
742 devc->data[i] = (128 - devc->buffer[i]) * vdiv - offset;
743 float vdivlog = log10f(vdiv);
744 int digits = -(int)vdivlog + (vdivlog < 0.0);
745 sr_analog_init(&analog, &encoding, &meaning, &spec, digits);
746 analog.meaning->channels = g_slist_append(NULL, ch);
747 analog.num_samples = len;
748 analog.data = devc->data;
749 analog.meaning->mq = SR_MQ_VOLTAGE;
750 analog.meaning->unit = SR_UNIT_VOLT;
751 analog.meaning->mqflags = 0;
752 packet.type = SR_DF_ANALOG;
753 packet.payload = &analog;
754 sr_session_send(sdi, &packet);
755 g_slist_free(analog.meaning->channels);
756 } else {
757 logic.length = len;
758 // TODO: For the MSO1000Z series, we need a way to express that
759 // this data is in fact just for a single channel, with the valid
760 // data for that channel in the LSB of each byte.
761 logic.unitsize = devc->model->series->protocol >= PROTOCOL_V4 ? 1 : 2;
762 logic.data = devc->buffer;
763 packet.type = SR_DF_LOGIC;
764 packet.payload = &logic;
765 sr_session_send(sdi, &packet);
766 }
767
768 if (devc->num_block_read == devc->num_block_bytes) {
769 sr_dbg("Block has been completed");
770 if (devc->model->series->protocol >= PROTOCOL_V3) {
771 /* Discard the terminating linefeed */
772 sr_scpi_read_data(scpi, (char *)devc->buffer, 1);
773 }
774 if (devc->format == FORMAT_IEEE488_2) {
775 /* Prepare for possible next block */
776 devc->num_header_bytes = 0;
777 devc->num_block_bytes = 0;
778 if (devc->data_source != DATA_SOURCE_LIVE)
779 rigol_ds_set_wait_event(devc, WAIT_BLOCK);
780 }
781 if (!sr_scpi_read_complete(scpi) && !devc->channel_entry->next) {
782 sr_err("Read should have been completed");
783 }
784 devc->num_block_read = 0;
785 } else {
786 sr_dbg("%" PRIu64 " of %" PRIu64 " block bytes read",
787 devc->num_block_read, devc->num_block_bytes);
788 }
789
790 devc->num_channel_bytes += len;
791
792 if (devc->num_channel_bytes < expected_data_bytes)
793 /* Don't have the full data for this channel yet, re-run. */
794 return TRUE;
795
796 /* End of data for this channel. */
797 if (devc->model->series->protocol == PROTOCOL_V3) {
798 /* Signal end of data download to scope */
799 if (devc->data_source != DATA_SOURCE_LIVE)
800 /*
801 * This causes a query error, without it switching
802 * to the next channel causes an error. Fun with
803 * firmware...
804 */
805 rigol_ds_config_set(sdi, ":WAV:END");
806 }
807
808 if (devc->channel_entry->next) {
809 /* We got the frame for this channel, now get the next channel. */
810 devc->channel_entry = devc->channel_entry->next;
811 rigol_ds_channel_start(sdi);
812 } else {
813 /* Done with this frame. */
814 std_session_send_df_frame_end(sdi);
815
816 devc->num_frames++;
817
818 /* V5 has no way to read the number of recorded frames, so try to set the
819 * next frame and read it back instead.
820 */
821 if (devc->data_source == DATA_SOURCE_SEGMENTED &&
822 devc->model->series->protocol == PROTOCOL_V5) {
823 int frames = 0;
824 if (rigol_ds_config_set(sdi, "REC:CURR %d", devc->num_frames + 1) != SR_OK)
825 return SR_ERR;
826 if (sr_scpi_get_int(sdi->conn, "REC:CURR?", &frames) != SR_OK)
827 return SR_ERR;
828 devc->num_frames_segmented = frames;
829 }
830
831 if (devc->num_frames == devc->limit_frames ||
832 devc->num_frames == devc->num_frames_segmented ||
833 devc->data_source == DATA_SOURCE_MEMORY) {
834 /* Last frame, stop capture. */
835 sr_dev_acquisition_stop(sdi);
836 } else {
837 /* Get the next frame, starting with the first channel. */
838 devc->channel_entry = devc->enabled_channels;
839
840 rigol_ds_capture_start(sdi);
841
842 /* Start of next frame. */
843 std_session_send_df_frame_begin(sdi);
844 }
845 }
846
847 return TRUE;
848}
849
850SR_PRIV int rigol_ds_get_dev_cfg(const struct sr_dev_inst *sdi)
851{
852 struct dev_context *devc;
853 struct sr_channel *ch;
854 char *cmd;
855 unsigned int i;
856 int res;
857
858 devc = sdi->priv;
859
860 /* Analog channel state. */
861 for (i = 0; i < devc->model->analog_channels; i++) {
862 cmd = g_strdup_printf(":CHAN%d:DISP?", i + 1);
863 res = sr_scpi_get_bool(sdi->conn, cmd, &devc->analog_channels[i]);
864 g_free(cmd);
865 if (res != SR_OK)
866 return SR_ERR;
867 ch = g_slist_nth_data(sdi->channels, i);
868 ch->enabled = devc->analog_channels[i];
869 }
870 sr_dbg("Current analog channel state:");
871 for (i = 0; i < devc->model->analog_channels; i++)
872 sr_dbg("CH%d %s", i + 1, devc->analog_channels[i] ? "on" : "off");
873
874 /* Digital channel state. */
875 if (devc->model->has_digital) {
876 if (sr_scpi_get_bool(sdi->conn,
877 devc->model->series->protocol >= PROTOCOL_V3 ?
878 ":LA:STAT?" : ":LA:DISP?",
879 &devc->la_enabled) != SR_OK)
880 return SR_ERR;
881 sr_dbg("Logic analyzer %s, current digital channel state:",
882 devc->la_enabled ? "enabled" : "disabled");
883 for (i = 0; i < ARRAY_SIZE(devc->digital_channels); i++) {
884 if (devc->model->series->protocol >= PROTOCOL_V5)
885 cmd = g_strdup_printf(":LA:DISP? D%d", i);
886 else if (devc->model->series->protocol >= PROTOCOL_V3)
887 cmd = g_strdup_printf(":LA:DIG%d:DISP?", i);
888 else
889 cmd = g_strdup_printf(":DIG%d:TURN?", i);
890 res = sr_scpi_get_bool(sdi->conn, cmd, &devc->digital_channels[i]);
891 g_free(cmd);
892 if (res != SR_OK)
893 return SR_ERR;
894 ch = g_slist_nth_data(sdi->channels, i + devc->model->analog_channels);
895 ch->enabled = devc->digital_channels[i];
896 sr_dbg("D%d: %s", i, devc->digital_channels[i] ? "on" : "off");
897 }
898 }
899
900 /* Timebase. */
901 if (sr_scpi_get_float(sdi->conn, ":TIM:SCAL?", &devc->timebase) != SR_OK)
902 return SR_ERR;
903 sr_dbg("Current timebase %g", devc->timebase);
904
905 /* Probe attenuation. */
906 for (i = 0; i < devc->model->analog_channels; i++) {
907 cmd = g_strdup_printf(":CHAN%d:PROB?", i + 1);
908 res = sr_scpi_get_float(sdi->conn, cmd, &devc->attenuation[i]);
909 g_free(cmd);
910 if (res != SR_OK)
911 return SR_ERR;
912 }
913 sr_dbg("Current probe attenuation:");
914 for (i = 0; i < devc->model->analog_channels; i++)
915 sr_dbg("CH%d %g", i + 1, devc->attenuation[i]);
916
917 /* Vertical gain and offset. */
918 if (rigol_ds_get_dev_cfg_vertical(sdi) != SR_OK)
919 return SR_ERR;
920
921 /* Coupling. */
922 for (i = 0; i < devc->model->analog_channels; i++) {
923 cmd = g_strdup_printf(":CHAN%d:COUP?", i + 1);
924 res = sr_scpi_get_string(sdi->conn, cmd, &devc->coupling[i]);
925 g_free(cmd);
926 if (res != SR_OK)
927 return SR_ERR;
928 }
929 sr_dbg("Current coupling:");
930 for (i = 0; i < devc->model->analog_channels; i++)
931 sr_dbg("CH%d %s", i + 1, devc->coupling[i]);
932
933 /* Trigger source. */
934 if (sr_scpi_get_string(sdi->conn, ":TRIG:EDGE:SOUR?", &devc->trigger_source) != SR_OK)
935 return SR_ERR;
936 sr_dbg("Current trigger source %s", devc->trigger_source);
937
938 /* Horizontal trigger position. */
939 if (sr_scpi_get_float(sdi->conn, devc->model->cmds[CMD_GET_HORIZ_TRIGGERPOS].str,
940 &devc->horiz_triggerpos) != SR_OK)
941 return SR_ERR;
942 sr_dbg("Current horizontal trigger position %g", devc->horiz_triggerpos);
943
944 /* Trigger slope. */
945 if (sr_scpi_get_string(sdi->conn, ":TRIG:EDGE:SLOP?", &devc->trigger_slope) != SR_OK)
946 return SR_ERR;
947 sr_dbg("Current trigger slope %s", devc->trigger_slope);
948
949 /* Trigger level. */
950 if (sr_scpi_get_float(sdi->conn, ":TRIG:EDGE:LEV?", &devc->trigger_level) != SR_OK)
951 return SR_ERR;
952 sr_dbg("Current trigger level %g", devc->trigger_level);
953
954 return SR_OK;
955}
956
957SR_PRIV int rigol_ds_get_dev_cfg_vertical(const struct sr_dev_inst *sdi)
958{
959 struct dev_context *devc;
960 char *cmd;
961 unsigned int i;
962 int res;
963
964 devc = sdi->priv;
965
966 /* Vertical gain. */
967 for (i = 0; i < devc->model->analog_channels; i++) {
968 cmd = g_strdup_printf(":CHAN%d:SCAL?", i + 1);
969 res = sr_scpi_get_float(sdi->conn, cmd, &devc->vdiv[i]);
970 g_free(cmd);
971 if (res != SR_OK)
972 return SR_ERR;
973 }
974 sr_dbg("Current vertical gain:");
975 for (i = 0; i < devc->model->analog_channels; i++)
976 sr_dbg("CH%d %g", i + 1, devc->vdiv[i]);
977
978 /* Vertical offset. */
979 for (i = 0; i < devc->model->analog_channels; i++) {
980 cmd = g_strdup_printf(":CHAN%d:OFFS?", i + 1);
981 res = sr_scpi_get_float(sdi->conn, cmd, &devc->vert_offset[i]);
982 g_free(cmd);
983 if (res != SR_OK)
984 return SR_ERR;
985 }
986 sr_dbg("Current vertical offset:");
987 for (i = 0; i < devc->model->analog_channels; i++)
988 sr_dbg("CH%d %g", i + 1, devc->vert_offset[i]);
989
990 return SR_OK;
991}
Hardware access and backend lib