[libsigrok.git] / src / hardware / zeroplus-logic-cube / analyzer.c

/*
 * This file is part of the libsigrok project.
 *
 * Copyright (C) 2010 Sven Peter <sven@fail0verflow.com>
 * Copyright (C) 2010 Haxx Enterprises <bushing@gmail.com>
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or
 * without modification, are permitted provided that the following
 * conditions are met:
 *
 * * Redistributions of source code must retain the above copyright notice,
 *   this list of conditions and the following disclaimer.
 *
 * * Redistributions in binary form must reproduce the above copyright notice,
 *   this list of conditions and the following disclaimer in the documentation
 *   and/or other materials provided with the distribution.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 *  THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <assert.h>
#include <libsigrok/libsigrok.h>
#include "libsigrok-internal.h"
#include "analyzer.h"
#include "gl_usb.h"
#include "protocol.h"

enum {
	HARD_DATA_CHECK_SUM		= 0x00,
	PASS_WORD,

	DEV_ID0				= 0x10,
	DEV_ID1,

	START_STATUS			= 0x20,
	DEV_STATUS			= 0x21,
	FREQUENCY_REG0			= 0x30,
	FREQUENCY_REG1,
	FREQUENCY_REG2,
	FREQUENCY_REG3,
	FREQUENCY_REG4,
	MEMORY_LENGTH,
	CLOCK_SOURCE,

	TRIGGER_STATUS0			= 0x40,
	TRIGGER_STATUS1,
	TRIGGER_STATUS2,
	TRIGGER_STATUS3,
	TRIGGER_STATUS4,
	TRIGGER_STATUS5,
	TRIGGER_STATUS6,
	TRIGGER_STATUS7,
	TRIGGER_STATUS8,

	TRIGGER_COUNT0			= 0x50,
	TRIGGER_COUNT1,

	TRIGGER_LEVEL0			= 0x55,
	TRIGGER_LEVEL1,
	TRIGGER_LEVEL2,
	TRIGGER_LEVEL3,

	RAMSIZE_TRIGGERBAR_ADDRESS0	= 0x60,
	RAMSIZE_TRIGGERBAR_ADDRESS1,
	RAMSIZE_TRIGGERBAR_ADDRESS2,
	TRIGGERBAR_ADDRESS0,
	TRIGGERBAR_ADDRESS1,
	TRIGGERBAR_ADDRESS2,
	DONT_CARE_TRIGGERBAR,

	FILTER_ENABLE			= 0x70,
	FILTER_STATUS,

	ENABLE_DELAY_TIME0		= 0x7a,
	ENABLE_DELAY_TIME1,

	ENABLE_INSERT_DATA0		= 0x80,
	ENABLE_INSERT_DATA1,
	ENABLE_INSERT_DATA2,
	ENABLE_INSERT_DATA3,
	COMPRESSION_TYPE0,
	COMPRESSION_TYPE1,

	TRIGGER_ADDRESS0		= 0x90,
	TRIGGER_ADDRESS1,
	TRIGGER_ADDRESS2,

	NOW_ADDRESS0			= 0x96,
	NOW_ADDRESS1,
	NOW_ADDRESS2,

	STOP_ADDRESS0			= 0x9b,
	STOP_ADDRESS1,
	STOP_ADDRESS2,

	READ_RAM_STATUS			= 0xa0,
};

static int g_trigger_status[9] = { 0 };
static int g_trigger_count = 1;
static int g_filter_status[8] = { 0 };
static int g_filter_enable = 0;

static int g_freq_value = 1;
static int g_freq_scale = FREQ_SCALE_MHZ;
static int g_memory_size = MEMORY_SIZE_8K;
static int g_ramsize_triggerbar_addr = 2 * 1024;
static int g_triggerbar_addr = 0;
static int g_compression = COMPRESSION_NONE;
static int g_thresh = 0x31; /* 1.5V */

/* Maybe unk specifies an "endpoint" or "register" of sorts. */
static int analyzer_write_status(libusb_device_handle *devh, unsigned char unk,
				 unsigned char flags)
{
	assert(unk <= 3);
	return gl_reg_write(devh, START_STATUS, unk << 6 | flags);
}

#if 0
static int __analyzer_set_freq(libusb_device_handle *devh, int freq, int scale)
{
	int reg0 = 0, divisor = 0, reg2 = 0;

	switch (scale) {
	case FREQ_SCALE_MHZ: /* MHz */
		if (freq >= 100 && freq <= 200) {
			reg0 = freq * 0.1;
			divisor = 1;
			reg2 = 0;
			break;
		}
		if (freq >= 50 && freq < 100) {
			reg0 = freq * 0.2;
			divisor = 2;
			reg2 = 0;
			break;
		}
		if (freq >= 10 && freq < 50) {
			if (freq == 25) {
				reg0 = 25;
				divisor = 5;
				reg2 = 1;
				break;
			} else {
				reg0 = freq * 0.5;
				divisor = 5;
				reg2 = 1;
				break;
			}
		}
		if (freq >= 2 && freq < 10) {
			divisor = 5;
			reg0 = freq * 2;
			reg2 = 2;
			break;
		}
		if (freq == 1) {
			divisor = 5;
			reg2 = 16;
			reg0 = 5;
			break;
		}
		divisor = 5;
		reg0 = 5;
		reg2 = 64;
		break;
	case FREQ_SCALE_HZ: /* Hz */
		if (freq >= 500 && freq < 1000) {
			reg0 = freq * 0.01;
			divisor = 10;
			reg2 = 64;
			break;
		}
		if (freq >= 300 && freq < 500) {
			reg0 = freq * 0.005 * 8;
			divisor = 5;
			reg2 = 67;
			break;
		}
		if (freq >= 100 && freq < 300) {
			reg0 = freq * 0.005 * 16;
			divisor = 5;
			reg2 = 68;
			break;
		}
		divisor = 5;
		reg0 = 5;
		reg2 = 64;
		break;
	case FREQ_SCALE_KHZ: /* kHz */
		if (freq >= 500 && freq < 1000) {
			reg0 = freq * 0.01;
			divisor = 5;
			reg2 = 17;
			break;
		}
		if (freq >= 100 && freq < 500) {
			reg0 = freq * 0.05;
			divisor = 5;
			reg2 = 32;
			break;
		}
		if (freq >= 50 && freq < 100) {
			reg0 = freq * 0.1;
			divisor = 5;
			reg2 = 33;
			break;
		}
		if (freq >= 10 && freq < 50) {
			if (freq == 25) {
				reg0 = 25;
				divisor = 5;
				reg2 = 49;
				break;
			}
			reg0 = freq * 0.5;
			divisor = 5;
			reg2 = 48;
			break;
		}
		if (freq >= 2 && freq < 10) {
			divisor = 5;
			reg0 = freq * 2;
			reg2 = 50;
			break;
		}
		divisor = 5;
		reg0 = 5;
		reg2 = 64;
		break;
	default:
		divisor = 5;
		reg0 = 5;
		reg2 = 64;
		break;
	}

	sr_dbg("Setting samplerate regs (freq=%d, scale=%d): "
	       "reg0: %d, reg1: %d, reg2: %d, reg3: %d.",
	       freq, scale, divisor, reg0, 0x02, reg2);

	if (gl_reg_write(devh, FREQUENCY_REG0, divisor) < 0)
		return -1; /* Divisor maybe? */

	if (gl_reg_write(devh, FREQUENCY_REG1, reg0) < 0)
		return -1; /* 10 / 0.2 */

	if (gl_reg_write(devh, FREQUENCY_REG2, 0x02) < 0)
		return -1; /* Always 2 */

	if (gl_reg_write(devh, FREQUENCY_REG4, reg2) < 0)
		return -1;

	return 0;
}
#endif

/*
 * It seems that ...
 *	FREQUENCT_REG0 - division factor (?)
 *	FREQUENCT_REG1 - multiplication factor (?)
 *	FREQUENCT_REG4 - clock selection (?)
 *
 *	clock selection
 *	0  10MHz  16   1MHz  32 100kHz  48  10kHz  64   1kHz
 *	1   5MHz  17 500kHz  33  50kHz  49   5kHz  65  500Hz
 *	2 2.5MHz   .          .         50 2.5kHz  66  250Hz
 *	.          .          .          .         67  125Hz
 *	.          .          .          .         68 62.5Hz
 */
static int __analyzer_set_freq(libusb_device_handle *devh, int freq, int scale)
{
	struct freq_factor {
		int freq;
		int scale;
		int sel;
		int div;
		int mul;
	};

	static const struct freq_factor f[] = {
		{ 200, FREQ_SCALE_MHZ,  0,  1, 20 },
		{ 150, FREQ_SCALE_MHZ,  0,  1, 15 },
		{ 100, FREQ_SCALE_MHZ,  0,  1, 10 },
		{  80, FREQ_SCALE_MHZ,  0,  2, 16 },
		{  50, FREQ_SCALE_MHZ,  0,  2, 10 },
		{  25, FREQ_SCALE_MHZ,  1,  5, 25 },
		{  10, FREQ_SCALE_MHZ,  1,  5, 10 },
		{   1, FREQ_SCALE_MHZ, 16,  5,  5 },
		{ 800, FREQ_SCALE_KHZ, 17,  5,  8 },
		{ 400, FREQ_SCALE_KHZ, 32,  5, 20 },
		{ 200, FREQ_SCALE_KHZ, 32,  5, 10 },
		{ 100, FREQ_SCALE_KHZ, 32,  5,  5 },
		{  50, FREQ_SCALE_KHZ, 33,  5,  5 },
		{  25, FREQ_SCALE_KHZ, 49,  5, 25 },
		{   5, FREQ_SCALE_KHZ, 50,  5, 10 },
		{   1, FREQ_SCALE_KHZ, 64,  5,  5 },
		{ 500, FREQ_SCALE_HZ,  64, 10,  5 },
		{ 100, FREQ_SCALE_HZ,  68,  5,  8 },
		{   0, 0,              0,   0,  0 }
	};

	int i;

	for (i = 0; f[i].freq; i++) {
		if (scale == f[i].scale && freq == f[i].freq)
			break;
	}
	if (!f[i].freq)
		return -1;

	sr_dbg("Setting samplerate regs (freq=%d, scale=%d): "
	       "reg0: %d, reg1: %d, reg2: %d, reg3: %d.",
	       freq, scale, f[i].div, f[i].mul, 0x02, f[i].sel);

	if (gl_reg_write(devh, FREQUENCY_REG0, f[i].div) < 0)
		return -1;

	if (gl_reg_write(devh, FREQUENCY_REG1, f[i].mul) < 0)
		return -1;

	if (gl_reg_write(devh, FREQUENCY_REG2, 0x02) < 0)
		return -1;

	if (gl_reg_write(devh, FREQUENCY_REG4, f[i].sel) < 0)
		return -1;

	return 0;
}

static void __analyzer_set_ramsize_trigger_address(libusb_device_handle *devh,
						   unsigned int address)
{
	gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
	gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
	gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
}

static void __analyzer_set_triggerbar_address(libusb_device_handle *devh,
					      unsigned int address)
{
	gl_reg_write(devh, TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
	gl_reg_write(devh, TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
	gl_reg_write(devh, TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
}

static void __analyzer_set_compression(libusb_device_handle *devh,
				       unsigned int type)
{
	gl_reg_write(devh, COMPRESSION_TYPE0, (type >> 0) & 0xFF);
	gl_reg_write(devh, COMPRESSION_TYPE1, (type >> 8) & 0xFF);
}

static void __analyzer_set_trigger_count(libusb_device_handle *devh,
					 unsigned int count)
{
	gl_reg_write(devh, TRIGGER_COUNT0, (count >> 0) & 0xFF);
	gl_reg_write(devh, TRIGGER_COUNT1, (count >> 8) & 0xFF);
}

static void analyzer_write_enable_insert_data(libusb_device_handle *devh)
{
	gl_reg_write(devh, ENABLE_INSERT_DATA0, 0x12);
	gl_reg_write(devh, ENABLE_INSERT_DATA1, 0x34);
	gl_reg_write(devh, ENABLE_INSERT_DATA2, 0x56);
	gl_reg_write(devh, ENABLE_INSERT_DATA3, 0x78);
}

static void analyzer_set_filter(libusb_device_handle *devh)
{
	int i;
	gl_reg_write(devh, FILTER_ENABLE, g_filter_enable);
	for (i = 0; i < 8; i++)
		gl_reg_write(devh, FILTER_STATUS + i, g_filter_status[i]);
}

SR_PRIV void analyzer_reset(libusb_device_handle *devh)
{
	analyzer_write_status(devh, 3, STATUS_FLAG_NONE);	// reset device
	analyzer_write_status(devh, 3, STATUS_FLAG_RESET);	// reset device
}

SR_PRIV void analyzer_initialize(libusb_device_handle *devh)
{
	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
}

SR_PRIV void analyzer_wait(libusb_device_handle *devh, int set, int unset)
{
	int status;

	while (1) {
		status = gl_reg_read(devh, DEV_STATUS);
		if ((!set || (status & set)) && ((status & unset) == 0))
			return;
	}
}

SR_PRIV void analyzer_read_start(libusb_device_handle *devh)
{
	analyzer_write_status(devh, 3, STATUS_FLAG_20 | STATUS_FLAG_READ);

	/* Prep for bulk reads */
	gl_reg_read_buf(devh, READ_RAM_STATUS, NULL, 0);
}

SR_PRIV int analyzer_read_data(libusb_device_handle *devh, void *buffer,
		       unsigned int size)
{
	return gl_read_bulk(devh, buffer, size);
}

SR_PRIV void analyzer_read_stop(libusb_device_handle *devh)
{
	analyzer_write_status(devh, 3, STATUS_FLAG_20);
	analyzer_write_status(devh, 3, STATUS_FLAG_NONE);
}

SR_PRIV void analyzer_start(libusb_device_handle *devh)
{
	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	analyzer_write_status(devh, 1, STATUS_FLAG_GO);
}

SR_PRIV void analyzer_configure(libusb_device_handle *devh)
{
	int i;

	/* Write_Start_Status */
	analyzer_write_status(devh, 1, STATUS_FLAG_RESET);
	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);

	/* Start_Config_Outside_Device ? */
	analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);

	/* SetData_To_Frequence_Reg */
	__analyzer_set_freq(devh, g_freq_value, g_freq_scale);

	/* SetMemory_Length */
	gl_reg_write(devh, MEMORY_LENGTH, g_memory_size);

	/* Sele_Inside_Outside_Clock */
	gl_reg_write(devh, CLOCK_SOURCE, 0x03);

	/* Set_Trigger_Status */
	for (i = 0; i < 9; i++)
		gl_reg_write(devh, TRIGGER_STATUS0 + i, g_trigger_status[i]);

	__analyzer_set_trigger_count(devh, g_trigger_count);

	/* Set_Trigger_Level */
	gl_reg_write(devh, TRIGGER_LEVEL0, g_thresh);
	gl_reg_write(devh, TRIGGER_LEVEL1, g_thresh);
	gl_reg_write(devh, TRIGGER_LEVEL2, g_thresh);
	gl_reg_write(devh, TRIGGER_LEVEL3, g_thresh);

	/* Size of actual memory >> 2 */
	__analyzer_set_ramsize_trigger_address(devh, g_ramsize_triggerbar_addr);
	__analyzer_set_triggerbar_address(devh, g_triggerbar_addr);

	/* Set_Dont_Care_TriggerBar */
	gl_reg_write(devh, DONT_CARE_TRIGGERBAR, 0x01);

	/* Enable_Status */
	analyzer_set_filter(devh);

	/* Set_Enable_Delay_Time */
	gl_reg_write(devh, 0x7a, 0x00);
	gl_reg_write(devh, 0x7b, 0x00);
	analyzer_write_enable_insert_data(devh);
	__analyzer_set_compression(devh, g_compression);
}

SR_PRIV int analyzer_add_triggers(const struct sr_dev_inst *sdi)
{
	struct dev_context *devc;
	struct sr_trigger *trigger;
	struct sr_trigger_stage *stage;
	struct sr_trigger_match *match;
	GSList *l, *m;
	int channel;

	devc = sdi->priv;

	if (!(trigger = sr_session_trigger_get(sdi->session)))
		return SR_OK;

	for (l = trigger->stages; l; l = l->next) {
		stage = l->data;
		for (m = stage->matches; m; m = m->next) {
			match = m->data;
			devc->trigger = 1;
			if (!match->channel->enabled)
				/* Ignore disabled channels with a trigger. */
				continue;
			channel = match->channel->index;
			switch (match->match) {
			case SR_TRIGGER_ZERO:
				g_trigger_status[channel / 4] |= 2 << (channel % 4 * 2);
				break;
			case SR_TRIGGER_ONE:
				g_trigger_status[channel / 4] |= 1 << (channel % 4 * 2);
				break;
			default:
				sr_err("Unsupported match %d", match->match);
				return SR_ERR;
			}
		}
	}

	return SR_OK;
}

SR_PRIV void analyzer_add_filter(int channel, int type)
{
	int i;

	if (type != FILTER_HIGH && type != FILTER_LOW)
		return;
	if ((channel & 0xf) >= 8)
		return;

	if (channel & CHANNEL_A)
		i = 0;
	else if (channel & CHANNEL_B)
		i = 2;
	else if (channel & CHANNEL_C)
		i = 4;
	else if (channel & CHANNEL_D)
		i = 6;
	else
		return;

	if ((channel & 0xf) >= 4) {
		i++;
		channel -= 4;
	}

	g_filter_status[i] |=
	    1 << ((2 * channel) + (type == FILTER_LOW ? 1 : 0));

	g_filter_enable = 1;
}

SR_PRIV void analyzer_set_trigger_count(int count)
{
	g_trigger_count = count;
}

SR_PRIV void analyzer_set_freq(int freq, int scale)
{
	g_freq_value = freq;
	g_freq_scale = scale;
}

SR_PRIV void analyzer_set_memory_size(unsigned int size)
{
	g_memory_size = size;
}

SR_PRIV void analyzer_set_ramsize_trigger_address(unsigned int address)
{
	g_ramsize_triggerbar_addr = address;
}

SR_PRIV unsigned int analyzer_get_ramsize_trigger_address(void)
{
	return g_ramsize_triggerbar_addr;
}

SR_PRIV void analyzer_set_triggerbar_address(unsigned int address)
{
	g_triggerbar_addr = address;
}

SR_PRIV unsigned int analyzer_get_triggerbar_address(void)
{
	return g_triggerbar_addr;
}

SR_PRIV unsigned int analyzer_read_status(libusb_device_handle *devh)
{
	return gl_reg_read(devh, DEV_STATUS);
}

SR_PRIV unsigned int analyzer_read_id(libusb_device_handle *devh)
{
	return gl_reg_read(devh, DEV_ID1) << 8 | gl_reg_read(devh, DEV_ID0);
}

SR_PRIV unsigned int analyzer_get_stop_address(libusb_device_handle *devh)
{
	return gl_reg_read(devh, STOP_ADDRESS2) << 16 | gl_reg_read(devh,
			STOP_ADDRESS1) << 8 | gl_reg_read(devh, STOP_ADDRESS0);
}

SR_PRIV unsigned int analyzer_get_now_address(libusb_device_handle *devh)
{
	return gl_reg_read(devh, NOW_ADDRESS2) << 16 | gl_reg_read(devh,
			NOW_ADDRESS1) << 8 | gl_reg_read(devh, NOW_ADDRESS0);
}

SR_PRIV unsigned int analyzer_get_trigger_address(libusb_device_handle *devh)
{
	return gl_reg_read(devh, TRIGGER_ADDRESS2) << 16 | gl_reg_read(devh,
		TRIGGER_ADDRESS1) << 8 | gl_reg_read(devh, TRIGGER_ADDRESS0);
}

SR_PRIV void analyzer_set_compression(unsigned int type)
{
	g_compression = type;
}

SR_PRIV void analyzer_set_voltage_threshold(int thresh)
{
	g_thresh = thresh;
}

SR_PRIV void analyzer_wait_button(libusb_device_handle *devh)
{
	analyzer_wait(devh, STATUS_BUTTON_PRESSED, 0);
}

SR_PRIV void analyzer_wait_data(libusb_device_handle *devh)
{
	analyzer_wait(devh, 0, STATUS_BUSY);
}

SR_PRIV int analyzer_decompress(void *input, unsigned int input_len,
				void *output, unsigned int output_len)
{
	unsigned char *in = input;
	unsigned char *out = output;
	unsigned int A, B, C, count;
	unsigned int written = 0;

	while (input_len > 0) {
		A = *in++;
		B = *in++;
		C = *in++;
		count = (*in++) + 1;

		if (count > output_len)
			count = output_len;
		output_len -= count;
		written += count;

		while (count--) {
			*out++ = A;
			*out++ = B;
			*out++ = C;
			*out++ = 0; /* Channel D */
		}

		input_len -= 4;
		if (output_len == 0)
			break;
	}

	return written;
}
Commit	Line	Data
a1bb33af	1	/*
50985c20	2	* This file is part of the libsigrok project.
fed16f06 UH	3	*
	4	* Copyright (C) 2010 Sven Peter <sven@fail0verflow.com>
	5	* Copyright (C) 2010 Haxx Enterprises <bushing@gmail.com>
	6	* All rights reserved.
	7	*
	8	* Redistribution and use in source and binary forms, with or
	9	* without modification, are permitted provided that the following
	10	* conditions are met:
	11	*
	12	* * Redistributions of source code must retain the above copyright notice,
	13	* this list of conditions and the following disclaimer.
	14	*
	15	* * Redistributions in binary form must reproduce the above copyright notice,
	16	* this list of conditions and the following disclaimer in the documentation
	17	* and/or other materials provided with the distribution.
	18	*
	19	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	20	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	21	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	22	* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
	23	* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
	24	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
	25	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
	26	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
	27	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
	28	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
	29	* THE POSSIBILITY OF SUCH DAMAGE.
	30	*/
a1bb33af	31
fed16f06	32	#include <assert.h>
c1aae900	33	#include <libsigrok/libsigrok.h>
6d116114	34	#include "libsigrok-internal.h"
a1bb33af UH	35	#include "analyzer.h"
a1bb33af UH	36	#include "gl_usb.h"
6d116114	37	#include "protocol.h"
a1bb33af UH	38
a1bb33af UH	39	enum {
fed16f06	40	HARD_DATA_CHECK_SUM = 0x00,
a1bb33af UH	41	PASS_WORD,
a1bb33af UH	42
bb7ef793 UH	43	DEV_ID0 = 0x10,
bb7ef793 UH	44	DEV_ID1,
a1bb33af	45
fed16f06	46	START_STATUS = 0x20,
bb7ef793	47	DEV_STATUS = 0x21,
fed16f06	48	FREQUENCY_REG0 = 0x30,
a1bb33af UH	49	FREQUENCY_REG1,
	50	FREQUENCY_REG2,
	51	FREQUENCY_REG3,
	52	FREQUENCY_REG4,
	53	MEMORY_LENGTH,
	54	CLOCK_SOURCE,
	55
fed16f06	56	TRIGGER_STATUS0 = 0x40,
a1bb33af UH	57	TRIGGER_STATUS1,
	58	TRIGGER_STATUS2,
	59	TRIGGER_STATUS3,
	60	TRIGGER_STATUS4,
	61	TRIGGER_STATUS5,
	62	TRIGGER_STATUS6,
	63	TRIGGER_STATUS7,
	64	TRIGGER_STATUS8,
	65
fed16f06	66	TRIGGER_COUNT0 = 0x50,
a1bb33af UH	67	TRIGGER_COUNT1,
a1bb33af UH	68
fed16f06	69	TRIGGER_LEVEL0 = 0x55,
a1bb33af UH	70	TRIGGER_LEVEL1,
	71	TRIGGER_LEVEL2,
	72	TRIGGER_LEVEL3,
	73
	74	RAMSIZE_TRIGGERBAR_ADDRESS0 = 0x60,
	75	RAMSIZE_TRIGGERBAR_ADDRESS1,
	76	RAMSIZE_TRIGGERBAR_ADDRESS2,
	77	TRIGGERBAR_ADDRESS0,
	78	TRIGGERBAR_ADDRESS1,
	79	TRIGGERBAR_ADDRESS2,
	80	DONT_CARE_TRIGGERBAR,
	81
	82	FILTER_ENABLE = 0x70,
	83	FILTER_STATUS,
	84
fed16f06	85	ENABLE_DELAY_TIME0 = 0x7a,
a1bb33af UH	86	ENABLE_DELAY_TIME1,
a1bb33af UH	87
fed16f06	88	ENABLE_INSERT_DATA0 = 0x80,
a1bb33af UH	89	ENABLE_INSERT_DATA1,
	90	ENABLE_INSERT_DATA2,
	91	ENABLE_INSERT_DATA3,
	92	COMPRESSION_TYPE0,
	93	COMPRESSION_TYPE1,
	94
fed16f06	95	TRIGGER_ADDRESS0 = 0x90,
a1bb33af UH	96	TRIGGER_ADDRESS1,
	97	TRIGGER_ADDRESS2,
	98
fed16f06	99	NOW_ADDRESS0 = 0x96,
a1bb33af UH	100	NOW_ADDRESS1,
	101	NOW_ADDRESS2,
	102
fed16f06	103	STOP_ADDRESS0 = 0x9b,
a1bb33af UH	104	STOP_ADDRESS1,
	105	STOP_ADDRESS2,
	106
fed16f06	107	READ_RAM_STATUS = 0xa0,
a1bb33af UH	108	};
a1bb33af UH	109
fed16f06	110	static int g_trigger_status[9] = { 0 };
a1bb33af	111	static int g_trigger_count = 1;
fed16f06	112	static int g_filter_status[8] = { 0 };
a1bb33af UH	113	static int g_filter_enable = 0;
a1bb33af UH	114
0ab0cb94	115	static int g_freq_value = 1;
a1bb33af	116	static int g_freq_scale = FREQ_SCALE_MHZ;
0ab0cb94 TY	117	static int g_memory_size = MEMORY_SIZE_8K;
	118	static int g_ramsize_triggerbar_addr = 2 * 1024;
	119	static int g_triggerbar_addr = 0;
a1bb33af	120	static int g_compression = COMPRESSION_NONE;
7142d6b9	121	static int g_thresh = 0x31; /* 1.5V */
a1bb33af	122
fed16f06 UH	123	/* Maybe unk specifies an "endpoint" or "register" of sorts. */
	124	static int analyzer_write_status(libusb_device_handle *devh, unsigned char unk,
	125	unsigned char flags)
a1bb33af UH	126	{
	127	assert(unk <= 3);
	128	return gl_reg_write(devh, START_STATUS, unk << 6 \| flags);
	129	}
	130
0ab0cb94	131	#if 0
a1bb33af UH	132	static int __analyzer_set_freq(libusb_device_handle *devh, int freq, int scale)
a1bb33af UH	133	{
fed16f06 UH	134	int reg0 = 0, divisor = 0, reg2 = 0;
fed16f06 UH	135
a1bb33af	136	switch (scale) {
fed16f06 UH	137	case FREQ_SCALE_MHZ: /* MHz */
	138	if (freq >= 100 && freq <= 200) {
	139	reg0 = freq * 0.1;
	140	divisor = 1;
	141	reg2 = 0;
	142	break;
	143	}
	144	if (freq >= 50 && freq < 100) {
	145	reg0 = freq * 0.2;
	146	divisor = 2;
	147	reg2 = 0;
	148	break;
	149	}
	150	if (freq >= 10 && freq < 50) {
	151	if (freq == 25) {
	152	reg0 = 25;
a1bb33af	153	divisor = 5;
fed16f06	154	reg2 = 1;
a1bb33af	155	break;
fed16f06 UH	156	} else {
fed16f06 UH	157	reg0 = freq * 0.5;
a1bb33af	158	divisor = 5;
fed16f06	159	reg2 = 1;
a1bb33af UH	160	break;
a1bb33af UH	161	}
fed16f06 UH	162	}
fed16f06 UH	163	if (freq >= 2 && freq < 10) {
a1bb33af	164	divisor = 5;
fed16f06 UH	165	reg0 = freq * 2;
fed16f06 UH	166	reg2 = 2;
a1bb33af	167	break;
fed16f06 UH	168	}
fed16f06 UH	169	if (freq == 1) {
a1bb33af	170	divisor = 5;
fed16f06	171	reg2 = 16;
a1bb33af	172	reg0 = 5;
fed16f06 UH	173	break;
	174	}
	175	divisor = 5;
	176	reg0 = 5;
	177	reg2 = 64;
	178	break;
	179	case FREQ_SCALE_HZ: /* Hz */
	180	if (freq >= 500 && freq < 1000) {
	181	reg0 = freq * 0.01;
	182	divisor = 10;
a1bb33af UH	183	reg2 = 64;
a1bb33af UH	184	break;
fed16f06 UH	185	}
	186	if (freq >= 300 && freq < 500) {
	187	reg0 = freq * 0.005 * 8;
	188	divisor = 5;
	189	reg2 = 67;
	190	break;
	191	}
	192	if (freq >= 100 && freq < 300) {
	193	reg0 = freq * 0.005 * 16;
	194	divisor = 5;
	195	reg2 = 68;
	196	break;
	197	}
	198	divisor = 5;
	199	reg0 = 5;
	200	reg2 = 64;
	201	break;
38ba2522	202	case FREQ_SCALE_KHZ: /* kHz */
fed16f06 UH	203	if (freq >= 500 && freq < 1000) {
	204	reg0 = freq * 0.01;
	205	divisor = 5;
	206	reg2 = 17;
	207	break;
	208	}
	209	if (freq >= 100 && freq < 500) {
	210	reg0 = freq * 0.05;
	211	divisor = 5;
	212	reg2 = 32;
	213	break;
	214	}
	215	if (freq >= 50 && freq < 100) {
	216	reg0 = freq * 0.1;
	217	divisor = 5;
	218	reg2 = 33;
	219	break;
	220	}
	221	if (freq >= 10 && freq < 50) {
	222	if (freq == 25) {
	223	reg0 = 25;
a1bb33af	224	divisor = 5;
fed16f06	225	reg2 = 49;
a1bb33af UH	226	break;
a1bb33af UH	227	}
fed16f06	228	reg0 = freq * 0.5;
a1bb33af	229	divisor = 5;
fed16f06	230	reg2 = 48;
a1bb33af	231	break;
fed16f06 UH	232	}
fed16f06 UH	233	if (freq >= 2 && freq < 10) {
a1bb33af	234	divisor = 5;
fed16f06 UH	235	reg0 = freq * 2;
fed16f06 UH	236	reg2 = 50;
a1bb33af	237	break;
fed16f06 UH	238	}
	239	divisor = 5;
	240	reg0 = 5;
	241	reg2 = 64;
	242	break;
	243	default:
	244	divisor = 5;
	245	reg0 = 5;
	246	reg2 = 64;
	247	break;
a1bb33af	248	}
c13536fa	249
6d116114	250	sr_dbg("Setting samplerate regs (freq=%d, scale=%d): "
c13536fa UH	251	"reg0: %d, reg1: %d, reg2: %d, reg3: %d.",
	252	freq, scale, divisor, reg0, 0x02, reg2);
	253
a1bb33af	254	if (gl_reg_write(devh, FREQUENCY_REG0, divisor) < 0)
fed16f06	255	return -1; /* Divisor maybe? */
a1bb33af UH	256
a1bb33af UH	257	if (gl_reg_write(devh, FREQUENCY_REG1, reg0) < 0)
fed16f06	258	return -1; /* 10 / 0.2 */
a1bb33af UH	259
a1bb33af UH	260	if (gl_reg_write(devh, FREQUENCY_REG2, 0x02) < 0)
fed16f06	261	return -1; /* Always 2 */
a1bb33af UH	262
	263	if (gl_reg_write(devh, FREQUENCY_REG4, reg2) < 0)
	264	return -1;
	265
	266	return 0;
	267	}
0ab0cb94 TY	268	#endif
	269
	270	/*
	271	* It seems that ...
	272	* FREQUENCT_REG0 - division factor (?)
	273	* FREQUENCT_REG1 - multiplication factor (?)
	274	* FREQUENCT_REG4 - clock selection (?)
	275	*
	276	* clock selection
	277	* 0 10MHz 16 1MHz 32 100kHz 48 10kHz 64 1kHz
	278	* 1 5MHz 17 500kHz 33 50kHz 49 5kHz 65 500Hz
	279	* 2 2.5MHz . . 50 2.5kHz 66 250Hz
	280	* . . . . 67 125Hz
	281	* . . . . 68 62.5Hz
	282	*/
	283	static int __analyzer_set_freq(libusb_device_handle *devh, int freq, int scale)
	284	{
	285	struct freq_factor {
	286	int freq;
	287	int scale;
	288	int sel;
	289	int div;
	290	int mul;
	291	};
	292
	293	static const struct freq_factor f[] = {
	294	{ 200, FREQ_SCALE_MHZ, 0, 1, 20 },
	295	{ 150, FREQ_SCALE_MHZ, 0, 1, 15 },
	296	{ 100, FREQ_SCALE_MHZ, 0, 1, 10 },
	297	{ 80, FREQ_SCALE_MHZ, 0, 2, 16 },
	298	{ 50, FREQ_SCALE_MHZ, 0, 2, 10 },
	299	{ 25, FREQ_SCALE_MHZ, 1, 5, 25 },
	300	{ 10, FREQ_SCALE_MHZ, 1, 5, 10 },
	301	{ 1, FREQ_SCALE_MHZ, 16, 5, 5 },
	302	{ 800, FREQ_SCALE_KHZ, 17, 5, 8 },
	303	{ 400, FREQ_SCALE_KHZ, 32, 5, 20 },
	304	{ 200, FREQ_SCALE_KHZ, 32, 5, 10 },
	305	{ 100, FREQ_SCALE_KHZ, 32, 5, 5 },
	306	{ 50, FREQ_SCALE_KHZ, 33, 5, 5 },
	307	{ 25, FREQ_SCALE_KHZ, 49, 5, 25 },
	308	{ 5, FREQ_SCALE_KHZ, 50, 5, 10 },
	309	{ 1, FREQ_SCALE_KHZ, 64, 5, 5 },
	310	{ 500, FREQ_SCALE_HZ, 64, 10, 5 },
	311	{ 100, FREQ_SCALE_HZ, 68, 5, 8 },
	312	{ 0, 0, 0, 0, 0 }
	313	};
	314
	315	int i;
	316
	317	for (i = 0; f[i].freq; i++) {
	318	if (scale == f[i].scale && freq == f[i].freq)
	319	break;
	320	}
	321	if (!f[i].freq)
	322	return -1;
	323
6d116114	324	sr_dbg("Setting samplerate regs (freq=%d, scale=%d): "
0ab0cb94 TY	325	"reg0: %d, reg1: %d, reg2: %d, reg3: %d.",
	326	freq, scale, f[i].div, f[i].mul, 0x02, f[i].sel);
	327
	328	if (gl_reg_write(devh, FREQUENCY_REG0, f[i].div) < 0)
	329	return -1;
	330
	331	if (gl_reg_write(devh, FREQUENCY_REG1, f[i].mul) < 0)
	332	return -1;
	333
	334	if (gl_reg_write(devh, FREQUENCY_REG2, 0x02) < 0)
	335	return -1;
	336
	337	if (gl_reg_write(devh, FREQUENCY_REG4, f[i].sel) < 0)
	338	return -1;
	339
	340	return 0;
	341	}
a1bb33af	342
fed16f06 UH	343	static void __analyzer_set_ramsize_trigger_address(libusb_device_handle *devh,
fed16f06 UH	344	unsigned int address)
a1bb33af	345	{
fed16f06 UH	346	gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
fed16f06 UH	347	gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
a1bb33af UH	348	gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
	349	}
	350
fed16f06 UH	351	static void __analyzer_set_triggerbar_address(libusb_device_handle *devh,
fed16f06 UH	352	unsigned int address)
a1bb33af	353	{
fed16f06 UH	354	gl_reg_write(devh, TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
fed16f06 UH	355	gl_reg_write(devh, TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
a1bb33af UH	356	gl_reg_write(devh, TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
	357	}
	358
fed16f06 UH	359	static void __analyzer_set_compression(libusb_device_handle *devh,
fed16f06 UH	360	unsigned int type)
a1bb33af UH	361	{
	362	gl_reg_write(devh, COMPRESSION_TYPE0, (type >> 0) & 0xFF);
	363	gl_reg_write(devh, COMPRESSION_TYPE1, (type >> 8) & 0xFF);
	364	}
	365
fed16f06 UH	366	static void __analyzer_set_trigger_count(libusb_device_handle *devh,
fed16f06 UH	367	unsigned int count)
a1bb33af UH	368	{
	369	gl_reg_write(devh, TRIGGER_COUNT0, (count >> 0) & 0xFF);
	370	gl_reg_write(devh, TRIGGER_COUNT1, (count >> 8) & 0xFF);
	371	}
	372
	373	static void analyzer_write_enable_insert_data(libusb_device_handle *devh)
	374	{
	375	gl_reg_write(devh, ENABLE_INSERT_DATA0, 0x12);
	376	gl_reg_write(devh, ENABLE_INSERT_DATA1, 0x34);
	377	gl_reg_write(devh, ENABLE_INSERT_DATA2, 0x56);
	378	gl_reg_write(devh, ENABLE_INSERT_DATA3, 0x78);
	379	}
	380
	381	static void analyzer_set_filter(libusb_device_handle *devh)
	382	{
	383	int i;
	384	gl_reg_write(devh, FILTER_ENABLE, g_filter_enable);
	385	for (i = 0; i < 8; i++)
	386	gl_reg_write(devh, FILTER_STATUS + i, g_filter_status[i]);
	387	}
	388
ca070ed9	389	SR_PRIV void analyzer_reset(libusb_device_handle *devh)
a1bb33af	390	{
fed16f06 UH	391	analyzer_write_status(devh, 3, STATUS_FLAG_NONE); // reset device
fed16f06 UH	392	analyzer_write_status(devh, 3, STATUS_FLAG_RESET); // reset device
a1bb33af UH	393	}
a1bb33af UH	394
ca070ed9	395	SR_PRIV void analyzer_initialize(libusb_device_handle *devh)
a1bb33af UH	396	{
	397	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	398	analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
	399	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	400	}
	401
ca070ed9	402	SR_PRIV void analyzer_wait(libusb_device_handle *devh, int set, int unset)
a1bb33af UH	403	{
a1bb33af UH	404	int status;
6d116114	405
fed16f06	406	while (1) {
bb7ef793	407	status = gl_reg_read(devh, DEV_STATUS);
d20844e2	408	if ((!set \|\| (status & set)) && ((status & unset) == 0))
a1bb33af UH	409	return;
	410	}
	411	}
	412
ca070ed9	413	SR_PRIV void analyzer_read_start(libusb_device_handle *devh)
a1bb33af	414	{
a1bb33af UH	415	analyzer_write_status(devh, 3, STATUS_FLAG_20 \| STATUS_FLAG_READ);
a1bb33af UH	416
aad03192 RD	417	/* Prep for bulk reads */
aad03192 RD	418	gl_reg_read_buf(devh, READ_RAM_STATUS, NULL, 0);
a1bb33af UH	419	}
a1bb33af UH	420
ca070ed9	421	SR_PRIV int analyzer_read_data(libusb_device_handle devh, void buffer,
fed16f06	422	unsigned int size)
a1bb33af UH	423	{
	424	return gl_read_bulk(devh, buffer, size);
	425	}
	426
ca070ed9	427	SR_PRIV void analyzer_read_stop(libusb_device_handle *devh)
a1bb33af UH	428	{
	429	analyzer_write_status(devh, 3, STATUS_FLAG_20);
	430	analyzer_write_status(devh, 3, STATUS_FLAG_NONE);
	431	}
	432
ca070ed9	433	SR_PRIV void analyzer_start(libusb_device_handle *devh)
a1bb33af UH	434	{
	435	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	436	analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
	437	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	438	analyzer_write_status(devh, 1, STATUS_FLAG_GO);
	439	}
	440
ca070ed9	441	SR_PRIV void analyzer_configure(libusb_device_handle *devh)
a1bb33af	442	{
fed16f06 UH	443	int i;
	444
	445	/* Write_Start_Status */
a1bb33af UH	446	analyzer_write_status(devh, 1, STATUS_FLAG_RESET);
	447	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	448
fed16f06	449	/* Start_Config_Outside_Device ? */
a1bb33af UH	450	analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
	451	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	452
fed16f06	453	/* SetData_To_Frequence_Reg */
a1bb33af UH	454	__analyzer_set_freq(devh, g_freq_value, g_freq_scale);
a1bb33af UH	455
fed16f06	456	/* SetMemory_Length */
a1bb33af UH	457	gl_reg_write(devh, MEMORY_LENGTH, g_memory_size);
a1bb33af UH	458
fed16f06	459	/* Sele_Inside_Outside_Clock */
a1bb33af UH	460	gl_reg_write(devh, CLOCK_SOURCE, 0x03);
a1bb33af UH	461
fed16f06	462	/* Set_Trigger_Status */
a1bb33af UH	463	for (i = 0; i < 9; i++)
	464	gl_reg_write(devh, TRIGGER_STATUS0 + i, g_trigger_status[i]);
	465
	466	__analyzer_set_trigger_count(devh, g_trigger_count);
	467
fed16f06	468	/* Set_Trigger_Level */
7142d6b9 RD	469	gl_reg_write(devh, TRIGGER_LEVEL0, g_thresh);
	470	gl_reg_write(devh, TRIGGER_LEVEL1, g_thresh);
	471	gl_reg_write(devh, TRIGGER_LEVEL2, g_thresh);
	472	gl_reg_write(devh, TRIGGER_LEVEL3, g_thresh);
a1bb33af	473
fed16f06 UH	474	/* Size of actual memory >> 2 */
fed16f06 UH	475	__analyzer_set_ramsize_trigger_address(devh, g_ramsize_triggerbar_addr);
a1bb33af UH	476	__analyzer_set_triggerbar_address(devh, g_triggerbar_addr);
a1bb33af UH	477
fed16f06	478	/* Set_Dont_Care_TriggerBar */
bc059b42	479	gl_reg_write(devh, DONT_CARE_TRIGGERBAR, 0x01);
a1bb33af	480
fed16f06	481	/* Enable_Status */
a1bb33af UH	482	analyzer_set_filter(devh);
a1bb33af UH	483
fed16f06	484	/* Set_Enable_Delay_Time */
a1bb33af UH	485	gl_reg_write(devh, 0x7a, 0x00);
	486	gl_reg_write(devh, 0x7b, 0x00);
	487	analyzer_write_enable_insert_data(devh);
fed16f06	488	__analyzer_set_compression(devh, g_compression);
a1bb33af UH	489	}
a1bb33af UH	490
28731bab	491	SR_PRIV int analyzer_add_triggers(const struct sr_dev_inst *sdi)
a1bb33af	492	{
28731bab BV	493	struct dev_context *devc;
	494	struct sr_trigger *trigger;
	495	struct sr_trigger_stage *stage;
	496	struct sr_trigger_match *match;
	497	GSList l, m;
	498	int channel;
	499
	500	devc = sdi->priv;
	501
0812c40e	502	if (!(trigger = sr_session_trigger_get(sdi->session)))
28731bab BV	503	return SR_OK;
	504
	505	for (l = trigger->stages; l; l = l->next) {
	506	stage = l->data;
	507	for (m = stage->matches; m; m = m->next) {
	508	match = m->data;
	509	devc->trigger = 1;
	510	if (!match->channel->enabled)
	511	/* Ignore disabled channels with a trigger. */
	512	continue;
	513	channel = match->channel->index;
	514	switch (match->match) {
	515	case SR_TRIGGER_ZERO:
	516	g_trigger_status[channel / 4] \|= 2 << (channel % 4 * 2);
72d69b7c	517	break;
28731bab BV	518	case SR_TRIGGER_ONE:
	519	g_trigger_status[channel / 4] \|= 1 << (channel % 4 * 2);
	520	break;
	521	default:
	522	sr_err("Unsupported match %d", match->match);
	523	return SR_ERR;
	524	}
	525	}
a1bb33af	526	}
28731bab BV	527
28731bab BV	528	return SR_OK;
a1bb33af UH	529	}
a1bb33af UH	530
ca070ed9	531	SR_PRIV void analyzer_add_filter(int channel, int type)
a1bb33af	532	{
fed16f06 UH	533	int i;
fed16f06 UH	534
a1bb33af UH	535	if (type != FILTER_HIGH && type != FILTER_LOW)
	536	return;
	537	if ((channel & 0xf) >= 8)
	538	return;
	539
a1bb33af UH	540	if (channel & CHANNEL_A)
	541	i = 0;
	542	else if (channel & CHANNEL_B)
	543	i = 2;
	544	else if (channel & CHANNEL_C)
	545	i = 4;
	546	else if (channel & CHANNEL_D)
	547	i = 6;
	548	else
	549	return;
fed16f06	550
a1bb33af UH	551	if ((channel & 0xf) >= 4) {
	552	i++;
	553	channel -= 4;
	554	}
fed16f06 UH	555
	556	g_filter_status[i] \|=
	557	1 << ((2 * channel) + (type == FILTER_LOW ? 1 : 0));
	558
a1bb33af UH	559	g_filter_enable = 1;
	560	}
	561
ca070ed9	562	SR_PRIV void analyzer_set_trigger_count(int count)
a1bb33af UH	563	{
	564	g_trigger_count = count;
	565	}
	566
ca070ed9	567	SR_PRIV void analyzer_set_freq(int freq, int scale)
a1bb33af UH	568	{
	569	g_freq_value = freq;
	570	g_freq_scale = scale;
	571	}
	572
ca070ed9	573	SR_PRIV void analyzer_set_memory_size(unsigned int size)
a1bb33af UH	574	{
	575	g_memory_size = size;
	576	}
	577
ca070ed9	578	SR_PRIV void analyzer_set_ramsize_trigger_address(unsigned int address)
a1bb33af UH	579	{
	580	g_ramsize_triggerbar_addr = address;
	581	}
	582
a864a05b RD	583	SR_PRIV unsigned int analyzer_get_ramsize_trigger_address(void)
	584	{
	585	return g_ramsize_triggerbar_addr;
	586	}
	587
ca070ed9	588	SR_PRIV void analyzer_set_triggerbar_address(unsigned int address)
a1bb33af UH	589	{
	590	g_triggerbar_addr = address;
	591	}
	592
a864a05b RD	593	SR_PRIV unsigned int analyzer_get_triggerbar_address(void)
	594	{
	595	return g_triggerbar_addr;
	596	}
	597
0ab0cb94 TY	598	SR_PRIV unsigned int analyzer_read_status(libusb_device_handle *devh)
	599	{
	600	return gl_reg_read(devh, DEV_STATUS);
	601	}
	602
ca070ed9	603	SR_PRIV unsigned int analyzer_read_id(libusb_device_handle *devh)
a1bb33af	604	{
bb7ef793	605	return gl_reg_read(devh, DEV_ID1) << 8 \| gl_reg_read(devh, DEV_ID0);
a1bb33af UH	606	}
a1bb33af UH	607
ca070ed9	608	SR_PRIV unsigned int analyzer_get_stop_address(libusb_device_handle *devh)
a1bb33af	609	{
fed16f06 UH	610	return gl_reg_read(devh, STOP_ADDRESS2) << 16 \| gl_reg_read(devh,
fed16f06 UH	611	STOP_ADDRESS1) << 8 \| gl_reg_read(devh, STOP_ADDRESS0);
a1bb33af UH	612	}
a1bb33af UH	613
ca070ed9	614	SR_PRIV unsigned int analyzer_get_now_address(libusb_device_handle *devh)
a1bb33af	615	{
fed16f06 UH	616	return gl_reg_read(devh, NOW_ADDRESS2) << 16 \| gl_reg_read(devh,
fed16f06 UH	617	NOW_ADDRESS1) << 8 \| gl_reg_read(devh, NOW_ADDRESS0);
a1bb33af UH	618	}
a1bb33af UH	619
ca070ed9	620	SR_PRIV unsigned int analyzer_get_trigger_address(libusb_device_handle *devh)
a1bb33af	621	{
fed16f06 UH	622	return gl_reg_read(devh, TRIGGER_ADDRESS2) << 16 \| gl_reg_read(devh,
fed16f06 UH	623	TRIGGER_ADDRESS1) << 8 \| gl_reg_read(devh, TRIGGER_ADDRESS0);
a1bb33af UH	624	}
a1bb33af UH	625
ca070ed9	626	SR_PRIV void analyzer_set_compression(unsigned int type)
a1bb33af UH	627	{
	628	g_compression = type;
	629	}
	630
7142d6b9 RD	631	SR_PRIV void analyzer_set_voltage_threshold(int thresh)
	632	{
	633	g_thresh = thresh;
	634	}
	635
ca070ed9	636	SR_PRIV void analyzer_wait_button(libusb_device_handle *devh)
a1bb33af UH	637	{
	638	analyzer_wait(devh, STATUS_BUTTON_PRESSED, 0);
	639	}
	640
ca070ed9	641	SR_PRIV void analyzer_wait_data(libusb_device_handle *devh)
a1bb33af	642	{
d20844e2	643	analyzer_wait(devh, 0, STATUS_BUSY);
a1bb33af UH	644	}
a1bb33af UH	645
ca070ed9 UH	646	SR_PRIV int analyzer_decompress(void *input, unsigned int input_len,
ca070ed9 UH	647	void *output, unsigned int output_len)
a1bb33af UH	648	{
	649	unsigned char *in = input;
	650	unsigned char *out = output;
	651	unsigned int A, B, C, count;
	652	unsigned int written = 0;
	653
	654	while (input_len > 0) {
	655	A = *in++;
	656	B = *in++;
	657	C = *in++;
	658	count = (*in++) + 1;
	659
	660	if (count > output_len)
	661	count = output_len;
	662	output_len -= count;
	663	written += count;
	664
	665	while (count--) {
	666	*out++ = A;
	667	*out++ = B;
	668	*out++ = C;
fed16f06	669	out++ = 0; / Channel D */
a1bb33af UH	670	}
	671
	672	input_len -= 4;
	673	if (output_len == 0)
	674	break;
	675	}
	676
	677	return written;
	678	}