[libsigrok.git] / hardware / zeroplus-logic-cube / analyzer.c

/*
 * This file is part of the sigrok project.
 *
 * Copyright (C) 2010 Sven Peter <sven@fail0verflow.com>
 * Copyright (C) 2010 Haxx Enterprises <bushing@gmail.com>
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or
 * without modification, are permitted provided that the following
 * conditions are met:
 *
 * * Redistributions of source code must retain the above copyright notice,
 *   this list of conditions and the following disclaimer.
 *
 * * Redistributions in binary form must reproduce the above copyright notice,
 *   this list of conditions and the following disclaimer in the documentation
 *   and/or other materials provided with the distribution.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 *  THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <assert.h>
#include "analyzer.h"
#include "gl_usb.h"

enum {
	HARD_DATA_CHECK_SUM		= 0x00,
	PASS_WORD,

	DEVICE_ID0			= 0x10,
	DEVICE_ID1,

	START_STATUS			= 0x20,
	DEVICE_STATUS			= 0x21,
	FREQUENCY_REG0			= 0x30,
	FREQUENCY_REG1,
	FREQUENCY_REG2,
	FREQUENCY_REG3,
	FREQUENCY_REG4,
	MEMORY_LENGTH,
	CLOCK_SOURCE,

	TRIGGER_STATUS0			= 0x40,
	TRIGGER_STATUS1,
	TRIGGER_STATUS2,
	TRIGGER_STATUS3,
	TRIGGER_STATUS4,
	TRIGGER_STATUS5,
	TRIGGER_STATUS6,
	TRIGGER_STATUS7,
	TRIGGER_STATUS8,

	TRIGGER_COUNT0			= 0x50,
	TRIGGER_COUNT1,

	TRIGGER_LEVEL0			= 0x55,
	TRIGGER_LEVEL1,
	TRIGGER_LEVEL2,
	TRIGGER_LEVEL3,

	RAMSIZE_TRIGGERBAR_ADDRESS0	= 0x60,
	RAMSIZE_TRIGGERBAR_ADDRESS1,
	RAMSIZE_TRIGGERBAR_ADDRESS2,
	TRIGGERBAR_ADDRESS0,
	TRIGGERBAR_ADDRESS1,
	TRIGGERBAR_ADDRESS2,
	DONT_CARE_TRIGGERBAR,

	FILTER_ENABLE			= 0x70,
	FILTER_STATUS,

	ENABLE_DELAY_TIME0		= 0x7a,
	ENABLE_DELAY_TIME1,

	ENABLE_INSERT_DATA0		= 0x80,
	ENABLE_INSERT_DATA1,
	ENABLE_INSERT_DATA2,
	ENABLE_INSERT_DATA3,
	COMPRESSION_TYPE0,
	COMPRESSION_TYPE1,

	TRIGGER_ADDRESS0		= 0x90,
	TRIGGER_ADDRESS1,
	TRIGGER_ADDRESS2,

	NOW_ADDRESS0			= 0x96,
	NOW_ADDRESS1,
	NOW_ADDRESS2,

	STOP_ADDRESS0			= 0x9b,
	STOP_ADDRESS1,
	STOP_ADDRESS2,

	READ_RAM_STATUS			= 0xa0,
};

static int g_trigger_status[9] = { 0 };
static int g_trigger_count = 1;
static int g_filter_status[8] = { 0 };
static int g_filter_enable = 0;

static int g_freq_value = 100;
static int g_freq_scale = FREQ_SCALE_MHZ;
static int g_memory_size = MEMORY_SIZE_512K;
static int g_ramsize_triggerbar_addr = 0x80000 >> 2;
static int g_triggerbar_addr = 0x3fe;
static int g_compression = COMPRESSION_NONE;

/* Maybe unk specifies an "endpoint" or "register" of sorts. */
static int analyzer_write_status(libusb_device_handle *devh, unsigned char unk,
				 unsigned char flags)
{
	assert(unk <= 3);
	return gl_reg_write(devh, START_STATUS, unk << 6 | flags);
}

static int __analyzer_set_freq(libusb_device_handle *devh, int freq, int scale)
{
	int reg0 = 0, divisor = 0, reg2 = 0;

	switch (scale) {
	case FREQ_SCALE_MHZ: /* MHz */
		if (freq >= 100 && freq <= 200) {
			reg0 = freq * 0.1;
			divisor = 1;
			reg2 = 0;
			break;
		}
		if (freq >= 50 && freq < 100) {
			reg0 = freq * 0.2;
			divisor = 2;
			reg2 = 0;
			break;
		}
		if (freq >= 10 && freq < 50) {
			if (freq == 25) {
				reg0 = 25;
				divisor = 5;
				reg2 = 1;
				break;
			} else {
				reg0 = freq * 0.5;
				divisor = 5;
				reg2 = 1;
				break;
			}
		}
		if (freq >= 2 && freq < 10) {
			divisor = 5;
			reg0 = freq * 2;
			reg2 = 2;
			break;
		}
		if (freq == 1) {
			divisor = 5;
			reg2 = 16;
			reg0 = 5;
			break;
		}
		divisor = 5;
		reg0 = 5;
		reg2 = 64;
		break;
	case FREQ_SCALE_HZ: /* Hz */
		if (freq >= 500 && freq < 1000) {
			reg0 = freq * 0.01;
			divisor = 10;
			reg2 = 64;
			break;
		}
		if (freq >= 300 && freq < 500) {
			reg0 = freq * 0.005 * 8;
			divisor = 5;
			reg2 = 67;
			break;
		}
		if (freq >= 100 && freq < 300) {
			reg0 = freq * 0.005 * 16;
			divisor = 5;
			reg2 = 68;
			break;
		}
		divisor = 5;
		reg0 = 5;
		reg2 = 64;
		break;
	case FREQ_SCALE_KHZ: /* kHz */
		if (freq >= 500 && freq < 1000) {
			reg0 = freq * 0.01;
			divisor = 5;
			reg2 = 17;
			break;
		}
		if (freq >= 100 && freq < 500) {
			reg0 = freq * 0.05;
			divisor = 5;
			reg2 = 32;
			break;
		}
		if (freq >= 50 && freq < 100) {
			reg0 = freq * 0.1;
			divisor = 5;
			reg2 = 33;
			break;
		}
		if (freq >= 10 && freq < 50) {
			if (freq == 25) {
				reg0 = 25;
				divisor = 5;
				reg2 = 49;
				break;
			}
			reg0 = freq * 0.5;
			divisor = 5;
			reg2 = 48;
			break;
		}
		if (freq >= 2 && freq < 10) {
			divisor = 5;
			reg0 = freq * 2;
			reg2 = 50;
			break;
		}
		divisor = 5;
		reg0 = 5;
		reg2 = 64;
		break;
	default:
		divisor = 5;
		reg0 = 5;
		reg2 = 64;
		break;
	}
	if (gl_reg_write(devh, FREQUENCY_REG0, divisor) < 0)
		return -1; /* Divisor maybe? */

	if (gl_reg_write(devh, FREQUENCY_REG1, reg0) < 0)
		return -1; /* 10 / 0.2 */

	if (gl_reg_write(devh, FREQUENCY_REG2, 0x02) < 0)
		return -1; /* Always 2 */

	if (gl_reg_write(devh, FREQUENCY_REG4, reg2) < 0)
		return -1;

	return 0;
}

static void __analyzer_set_ramsize_trigger_address(libusb_device_handle *devh,
						   unsigned int address)
{
	gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
	gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
	gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
}

static void __analyzer_set_triggerbar_address(libusb_device_handle *devh,
					      unsigned int address)
{
	gl_reg_write(devh, TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
	gl_reg_write(devh, TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
	gl_reg_write(devh, TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
}

static void __analyzer_set_compression(libusb_device_handle *devh,
				       unsigned int type)
{
	gl_reg_write(devh, COMPRESSION_TYPE0, (type >> 0) & 0xFF);
	gl_reg_write(devh, COMPRESSION_TYPE1, (type >> 8) & 0xFF);
}

static void __analyzer_set_trigger_count(libusb_device_handle *devh,
					 unsigned int count)
{
	gl_reg_write(devh, TRIGGER_COUNT0, (count >> 0) & 0xFF);
	gl_reg_write(devh, TRIGGER_COUNT1, (count >> 8) & 0xFF);
}

static void analyzer_write_enable_insert_data(libusb_device_handle *devh)
{
	gl_reg_write(devh, ENABLE_INSERT_DATA0, 0x12);
	gl_reg_write(devh, ENABLE_INSERT_DATA1, 0x34);
	gl_reg_write(devh, ENABLE_INSERT_DATA2, 0x56);
	gl_reg_write(devh, ENABLE_INSERT_DATA3, 0x78);
}

static void analyzer_set_filter(libusb_device_handle *devh)
{
	int i;
	gl_reg_write(devh, FILTER_ENABLE, g_filter_enable);
	for (i = 0; i < 8; i++)
		gl_reg_write(devh, FILTER_STATUS + i, g_filter_status[i]);
}

SR_PRIV void analyzer_reset(libusb_device_handle *devh)
{
	analyzer_write_status(devh, 3, STATUS_FLAG_NONE);	// reset device
	analyzer_write_status(devh, 3, STATUS_FLAG_RESET);	// reset device
}

SR_PRIV void analyzer_initialize(libusb_device_handle *devh)
{
	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
}

SR_PRIV void analyzer_wait(libusb_device_handle *devh, int set, int unset)
{
	int status;
	while (1) {
		status = gl_reg_read(devh, DEVICE_STATUS);
		if ((status & set) && ((status & unset) == 0))
			return;
	}
}

SR_PRIV void analyzer_read_start(libusb_device_handle *devh)
{
	int i;

	analyzer_write_status(devh, 3, STATUS_FLAG_20 | STATUS_FLAG_READ);

	for (i = 0; i < 8; i++)
		(void)gl_reg_read(devh, READ_RAM_STATUS);
}

SR_PRIV int analyzer_read_data(libusb_device_handle *devh, void *buffer,
		       unsigned int size)
{
	return gl_read_bulk(devh, buffer, size);
}

SR_PRIV void analyzer_read_stop(libusb_device_handle *devh)
{
	analyzer_write_status(devh, 3, STATUS_FLAG_20);
	analyzer_write_status(devh, 3, STATUS_FLAG_NONE);
}

SR_PRIV void analyzer_start(libusb_device_handle *devh)
{
	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	analyzer_write_status(devh, 1, STATUS_FLAG_GO);
}

SR_PRIV void analyzer_configure(libusb_device_handle *devh)
{
	int i;

	/* Write_Start_Status */
	analyzer_write_status(devh, 1, STATUS_FLAG_RESET);
	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);

	/* Start_Config_Outside_Device ? */
	analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);

	/* SetData_To_Frequence_Reg */
	__analyzer_set_freq(devh, g_freq_value, g_freq_scale);

	/* SetMemory_Length */
	gl_reg_write(devh, MEMORY_LENGTH, g_memory_size);

	/* Sele_Inside_Outside_Clock */
	gl_reg_write(devh, CLOCK_SOURCE, 0x03);

	/* Set_Trigger_Status */
	for (i = 0; i < 9; i++)
		gl_reg_write(devh, TRIGGER_STATUS0 + i, g_trigger_status[i]);

	__analyzer_set_trigger_count(devh, g_trigger_count);

	/* Set_Trigger_Level */
	gl_reg_write(devh, TRIGGER_LEVEL0, 0x31);
	gl_reg_write(devh, TRIGGER_LEVEL1, 0x31);
	gl_reg_write(devh, TRIGGER_LEVEL2, 0x31);
	gl_reg_write(devh, TRIGGER_LEVEL3, 0x31);

	/* Size of actual memory >> 2 */
	__analyzer_set_ramsize_trigger_address(devh, g_ramsize_triggerbar_addr);
	__analyzer_set_triggerbar_address(devh, g_triggerbar_addr);

	/* Set_Dont_Care_TriggerBar */
	gl_reg_write(devh, DONT_CARE_TRIGGERBAR, 0x01);

	/* Enable_Status */
	analyzer_set_filter(devh);

	/* Set_Enable_Delay_Time */
	gl_reg_write(devh, 0x7a, 0x00);
	gl_reg_write(devh, 0x7b, 0x00);
	analyzer_write_enable_insert_data(devh);
	__analyzer_set_compression(devh, g_compression);
}

SR_PRIV void analyzer_add_trigger(int channel, int type)
{
	int i;

	if ((channel & 0xf) >= 8)
		return;

	if (type == TRIGGER_HIGH || type == TRIGGER_LOW) {
		if (channel & CHANNEL_A)
			i = 0;
		else if (channel & CHANNEL_B)
			i = 2;
		else if (channel & CHANNEL_C)
			i = 4;
		else if (channel & CHANNEL_D)
			i = 6;
		else
			return;
		if ((channel & 0xf) >= 4) {
			i++;
			channel -= 4;
		}
		g_trigger_status[i] |=
		    1 << ((2 * channel) + (type == TRIGGER_LOW ? 1 : 0));
	} else {
		if (type == TRIGGER_POSEDGE)
			g_trigger_status[8] = 0x40;
		else if (type == TRIGGER_NEGEDGE)
			g_trigger_status[8] = 0x80;
		else
			g_trigger_status[8] = 0xc0;

		/* FIXME: Just guessed the index; need to verify. */
		if (channel & CHANNEL_B)
			g_trigger_status[8] += 8;
		else if (channel & CHANNEL_C)
			g_trigger_status[8] += 16;
		else if (channel & CHANNEL_D)
			g_trigger_status[8] += 24;
		g_trigger_status[8] += channel % 8;
	}
}

SR_PRIV void analyzer_add_filter(int channel, int type)
{
	int i;

	if (type != FILTER_HIGH && type != FILTER_LOW)
		return;
	if ((channel & 0xf) >= 8)
		return;

	if (channel & CHANNEL_A)
		i = 0;
	else if (channel & CHANNEL_B)
		i = 2;
	else if (channel & CHANNEL_C)
		i = 4;
	else if (channel & CHANNEL_D)
		i = 6;
	else
		return;

	if ((channel & 0xf) >= 4) {
		i++;
		channel -= 4;
	}

	g_filter_status[i] |=
	    1 << ((2 * channel) + (type == FILTER_LOW ? 1 : 0));

	g_filter_enable = 1;
}

SR_PRIV void analyzer_set_trigger_count(int count)
{
	g_trigger_count = count;
}

SR_PRIV void analyzer_set_freq(int freq, int scale)
{
	g_freq_value = freq;
	g_freq_scale = scale;
}

SR_PRIV void analyzer_set_memory_size(unsigned int size)
{
	g_memory_size = size;
}

SR_PRIV void analyzer_set_ramsize_trigger_address(unsigned int address)
{
	g_ramsize_triggerbar_addr = address;
}

SR_PRIV void analyzer_set_triggerbar_address(unsigned int address)
{
	g_triggerbar_addr = address;
}

SR_PRIV unsigned int analyzer_read_id(libusb_device_handle *devh)
{
	return gl_reg_read(devh, DEVICE_ID1) << 8 | gl_reg_read(devh,
								DEVICE_ID0);
}

SR_PRIV unsigned int analyzer_get_stop_address(libusb_device_handle *devh)
{
	return gl_reg_read(devh, STOP_ADDRESS2) << 16 | gl_reg_read(devh,
			STOP_ADDRESS1) << 8 | gl_reg_read(devh, STOP_ADDRESS0);
}

SR_PRIV unsigned int analyzer_get_now_address(libusb_device_handle *devh)
{
	return gl_reg_read(devh, NOW_ADDRESS2) << 16 | gl_reg_read(devh,
			NOW_ADDRESS1) << 8 | gl_reg_read(devh, NOW_ADDRESS0);
}

SR_PRIV unsigned int analyzer_get_trigger_address(libusb_device_handle *devh)
{
	return gl_reg_read(devh, TRIGGER_ADDRESS2) << 16 | gl_reg_read(devh,
		TRIGGER_ADDRESS1) << 8 | gl_reg_read(devh, TRIGGER_ADDRESS0);
}

SR_PRIV void analyzer_set_compression(unsigned int type)
{
	g_compression = type;
}

SR_PRIV void analyzer_wait_button(libusb_device_handle *devh)
{
	analyzer_wait(devh, STATUS_BUTTON_PRESSED, 0);
}

SR_PRIV void analyzer_wait_data(libusb_device_handle *devh)
{
	analyzer_wait(devh, STATUS_READY | 8, STATUS_BUSY);
}

SR_PRIV int analyzer_decompress(void *input, unsigned int input_len,
				void *output, unsigned int output_len)
{
	unsigned char *in = input;
	unsigned char *out = output;
	unsigned int A, B, C, count;
	unsigned int written = 0;

	while (input_len > 0) {
		A = *in++;
		B = *in++;
		C = *in++;
		count = (*in++) + 1;

		if (count > output_len)
			count = output_len;
		output_len -= count;
		written += count;

		while (count--) {
			*out++ = A;
			*out++ = B;
			*out++ = C;
			*out++ = 0; /* Channel D */
		}

		input_len -= 4;
		if (output_len == 0)
			break;
	}

	return written;
}
Commit	Line	Data
a1bb33af	1	/*
fed16f06 UH	2	* This file is part of the sigrok project.
	3	*
	4	* Copyright (C) 2010 Sven Peter <sven@fail0verflow.com>
	5	* Copyright (C) 2010 Haxx Enterprises <bushing@gmail.com>
	6	* All rights reserved.
	7	*
	8	* Redistribution and use in source and binary forms, with or
	9	* without modification, are permitted provided that the following
	10	* conditions are met:
	11	*
	12	* * Redistributions of source code must retain the above copyright notice,
	13	* this list of conditions and the following disclaimer.
	14	*
	15	* * Redistributions in binary form must reproduce the above copyright notice,
	16	* this list of conditions and the following disclaimer in the documentation
	17	* and/or other materials provided with the distribution.
	18	*
	19	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	20	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	21	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	22	* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
	23	* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
	24	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
	25	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
	26	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
	27	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
	28	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
	29	* THE POSSIBILITY OF SUCH DAMAGE.
	30	*/
a1bb33af	31
fed16f06	32	#include <assert.h>
a1bb33af UH	33	#include "analyzer.h"
	34	#include "gl_usb.h"
	35
	36	enum {
fed16f06	37	HARD_DATA_CHECK_SUM = 0x00,
a1bb33af UH	38	PASS_WORD,
a1bb33af UH	39
fed16f06	40	DEVICE_ID0 = 0x10,
a1bb33af UH	41	DEVICE_ID1,
a1bb33af UH	42
fed16f06 UH	43	START_STATUS = 0x20,
	44	DEVICE_STATUS = 0x21,
	45	FREQUENCY_REG0 = 0x30,
a1bb33af UH	46	FREQUENCY_REG1,
	47	FREQUENCY_REG2,
	48	FREQUENCY_REG3,
	49	FREQUENCY_REG4,
	50	MEMORY_LENGTH,
	51	CLOCK_SOURCE,
	52
fed16f06	53	TRIGGER_STATUS0 = 0x40,
a1bb33af UH	54	TRIGGER_STATUS1,
	55	TRIGGER_STATUS2,
	56	TRIGGER_STATUS3,
	57	TRIGGER_STATUS4,
	58	TRIGGER_STATUS5,
	59	TRIGGER_STATUS6,
	60	TRIGGER_STATUS7,
	61	TRIGGER_STATUS8,
	62
fed16f06	63	TRIGGER_COUNT0 = 0x50,
a1bb33af UH	64	TRIGGER_COUNT1,
a1bb33af UH	65
fed16f06	66	TRIGGER_LEVEL0 = 0x55,
a1bb33af UH	67	TRIGGER_LEVEL1,
	68	TRIGGER_LEVEL2,
	69	TRIGGER_LEVEL3,
	70
	71	RAMSIZE_TRIGGERBAR_ADDRESS0 = 0x60,
	72	RAMSIZE_TRIGGERBAR_ADDRESS1,
	73	RAMSIZE_TRIGGERBAR_ADDRESS2,
	74	TRIGGERBAR_ADDRESS0,
	75	TRIGGERBAR_ADDRESS1,
	76	TRIGGERBAR_ADDRESS2,
	77	DONT_CARE_TRIGGERBAR,
	78
	79	FILTER_ENABLE = 0x70,
	80	FILTER_STATUS,
	81
fed16f06	82	ENABLE_DELAY_TIME0 = 0x7a,
a1bb33af UH	83	ENABLE_DELAY_TIME1,
a1bb33af UH	84
fed16f06	85	ENABLE_INSERT_DATA0 = 0x80,
a1bb33af UH	86	ENABLE_INSERT_DATA1,
	87	ENABLE_INSERT_DATA2,
	88	ENABLE_INSERT_DATA3,
	89	COMPRESSION_TYPE0,
	90	COMPRESSION_TYPE1,
	91
fed16f06	92	TRIGGER_ADDRESS0 = 0x90,
a1bb33af UH	93	TRIGGER_ADDRESS1,
	94	TRIGGER_ADDRESS2,
	95
fed16f06	96	NOW_ADDRESS0 = 0x96,
a1bb33af UH	97	NOW_ADDRESS1,
	98	NOW_ADDRESS2,
	99
fed16f06	100	STOP_ADDRESS0 = 0x9b,
a1bb33af UH	101	STOP_ADDRESS1,
	102	STOP_ADDRESS2,
	103
fed16f06	104	READ_RAM_STATUS = 0xa0,
a1bb33af UH	105	};
a1bb33af UH	106
fed16f06	107	static int g_trigger_status[9] = { 0 };
a1bb33af	108	static int g_trigger_count = 1;
fed16f06	109	static int g_filter_status[8] = { 0 };
a1bb33af UH	110	static int g_filter_enable = 0;
	111
	112	static int g_freq_value = 100;
	113	static int g_freq_scale = FREQ_SCALE_MHZ;
	114	static int g_memory_size = MEMORY_SIZE_512K;
fed16f06	115	static int g_ramsize_triggerbar_addr = 0x80000 >> 2;
a1bb33af UH	116	static int g_triggerbar_addr = 0x3fe;
	117	static int g_compression = COMPRESSION_NONE;
	118
fed16f06 UH	119	/* Maybe unk specifies an "endpoint" or "register" of sorts. */
	120	static int analyzer_write_status(libusb_device_handle *devh, unsigned char unk,
	121	unsigned char flags)
a1bb33af UH	122	{
	123	assert(unk <= 3);
	124	return gl_reg_write(devh, START_STATUS, unk << 6 \| flags);
	125	}
	126
	127	static int __analyzer_set_freq(libusb_device_handle *devh, int freq, int scale)
	128	{
fed16f06 UH	129	int reg0 = 0, divisor = 0, reg2 = 0;
fed16f06 UH	130
a1bb33af	131	switch (scale) {
fed16f06 UH	132	case FREQ_SCALE_MHZ: /* MHz */
	133	if (freq >= 100 && freq <= 200) {
	134	reg0 = freq * 0.1;
	135	divisor = 1;
	136	reg2 = 0;
	137	break;
	138	}
	139	if (freq >= 50 && freq < 100) {
	140	reg0 = freq * 0.2;
	141	divisor = 2;
	142	reg2 = 0;
	143	break;
	144	}
	145	if (freq >= 10 && freq < 50) {
	146	if (freq == 25) {
	147	reg0 = 25;
a1bb33af	148	divisor = 5;
fed16f06	149	reg2 = 1;
a1bb33af	150	break;
fed16f06 UH	151	} else {
fed16f06 UH	152	reg0 = freq * 0.5;
a1bb33af	153	divisor = 5;
fed16f06	154	reg2 = 1;
a1bb33af UH	155	break;
a1bb33af UH	156	}
fed16f06 UH	157	}
fed16f06 UH	158	if (freq >= 2 && freq < 10) {
a1bb33af	159	divisor = 5;
fed16f06 UH	160	reg0 = freq * 2;
fed16f06 UH	161	reg2 = 2;
a1bb33af	162	break;
fed16f06 UH	163	}
fed16f06 UH	164	if (freq == 1) {
a1bb33af	165	divisor = 5;
fed16f06	166	reg2 = 16;
a1bb33af	167	reg0 = 5;
fed16f06 UH	168	break;
	169	}
	170	divisor = 5;
	171	reg0 = 5;
	172	reg2 = 64;
	173	break;
	174	case FREQ_SCALE_HZ: /* Hz */
	175	if (freq >= 500 && freq < 1000) {
	176	reg0 = freq * 0.01;
	177	divisor = 10;
a1bb33af UH	178	reg2 = 64;
a1bb33af UH	179	break;
fed16f06 UH	180	}
	181	if (freq >= 300 && freq < 500) {
	182	reg0 = freq * 0.005 * 8;
	183	divisor = 5;
	184	reg2 = 67;
	185	break;
	186	}
	187	if (freq >= 100 && freq < 300) {
	188	reg0 = freq * 0.005 * 16;
	189	divisor = 5;
	190	reg2 = 68;
	191	break;
	192	}
	193	divisor = 5;
	194	reg0 = 5;
	195	reg2 = 64;
	196	break;
38ba2522	197	case FREQ_SCALE_KHZ: /* kHz */
fed16f06 UH	198	if (freq >= 500 && freq < 1000) {
	199	reg0 = freq * 0.01;
	200	divisor = 5;
	201	reg2 = 17;
	202	break;
	203	}
	204	if (freq >= 100 && freq < 500) {
	205	reg0 = freq * 0.05;
	206	divisor = 5;
	207	reg2 = 32;
	208	break;
	209	}
	210	if (freq >= 50 && freq < 100) {
	211	reg0 = freq * 0.1;
	212	divisor = 5;
	213	reg2 = 33;
	214	break;
	215	}
	216	if (freq >= 10 && freq < 50) {
	217	if (freq == 25) {
	218	reg0 = 25;
a1bb33af	219	divisor = 5;
fed16f06	220	reg2 = 49;
a1bb33af UH	221	break;
a1bb33af UH	222	}
fed16f06	223	reg0 = freq * 0.5;
a1bb33af	224	divisor = 5;
fed16f06	225	reg2 = 48;
a1bb33af	226	break;
fed16f06 UH	227	}
fed16f06 UH	228	if (freq >= 2 && freq < 10) {
a1bb33af	229	divisor = 5;
fed16f06 UH	230	reg0 = freq * 2;
fed16f06 UH	231	reg2 = 50;
a1bb33af	232	break;
fed16f06 UH	233	}
	234	divisor = 5;
	235	reg0 = 5;
	236	reg2 = 64;
	237	break;
	238	default:
	239	divisor = 5;
	240	reg0 = 5;
	241	reg2 = 64;
	242	break;
a1bb33af UH	243	}
a1bb33af UH	244	if (gl_reg_write(devh, FREQUENCY_REG0, divisor) < 0)
fed16f06	245	return -1; /* Divisor maybe? */
a1bb33af UH	246
a1bb33af UH	247	if (gl_reg_write(devh, FREQUENCY_REG1, reg0) < 0)
fed16f06	248	return -1; /* 10 / 0.2 */
a1bb33af UH	249
a1bb33af UH	250	if (gl_reg_write(devh, FREQUENCY_REG2, 0x02) < 0)
fed16f06	251	return -1; /* Always 2 */
a1bb33af UH	252
	253	if (gl_reg_write(devh, FREQUENCY_REG4, reg2) < 0)
	254	return -1;
	255
	256	return 0;
	257	}
	258
fed16f06 UH	259	static void __analyzer_set_ramsize_trigger_address(libusb_device_handle *devh,
fed16f06 UH	260	unsigned int address)
a1bb33af	261	{
fed16f06 UH	262	gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
fed16f06 UH	263	gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
a1bb33af UH	264	gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
	265	}
	266
fed16f06 UH	267	static void __analyzer_set_triggerbar_address(libusb_device_handle *devh,
fed16f06 UH	268	unsigned int address)
a1bb33af	269	{
fed16f06 UH	270	gl_reg_write(devh, TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
fed16f06 UH	271	gl_reg_write(devh, TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
a1bb33af UH	272	gl_reg_write(devh, TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
	273	}
	274
fed16f06 UH	275	static void __analyzer_set_compression(libusb_device_handle *devh,
fed16f06 UH	276	unsigned int type)
a1bb33af UH	277	{
	278	gl_reg_write(devh, COMPRESSION_TYPE0, (type >> 0) & 0xFF);
	279	gl_reg_write(devh, COMPRESSION_TYPE1, (type >> 8) & 0xFF);
	280	}
	281
fed16f06 UH	282	static void __analyzer_set_trigger_count(libusb_device_handle *devh,
fed16f06 UH	283	unsigned int count)
a1bb33af UH	284	{
	285	gl_reg_write(devh, TRIGGER_COUNT0, (count >> 0) & 0xFF);
	286	gl_reg_write(devh, TRIGGER_COUNT1, (count >> 8) & 0xFF);
	287	}
	288
	289	static void analyzer_write_enable_insert_data(libusb_device_handle *devh)
	290	{
	291	gl_reg_write(devh, ENABLE_INSERT_DATA0, 0x12);
	292	gl_reg_write(devh, ENABLE_INSERT_DATA1, 0x34);
	293	gl_reg_write(devh, ENABLE_INSERT_DATA2, 0x56);
	294	gl_reg_write(devh, ENABLE_INSERT_DATA3, 0x78);
	295	}
	296
	297	static void analyzer_set_filter(libusb_device_handle *devh)
	298	{
	299	int i;
	300	gl_reg_write(devh, FILTER_ENABLE, g_filter_enable);
	301	for (i = 0; i < 8; i++)
	302	gl_reg_write(devh, FILTER_STATUS + i, g_filter_status[i]);
	303	}
	304
ca070ed9	305	SR_PRIV void analyzer_reset(libusb_device_handle *devh)
a1bb33af	306	{
fed16f06 UH	307	analyzer_write_status(devh, 3, STATUS_FLAG_NONE); // reset device
fed16f06 UH	308	analyzer_write_status(devh, 3, STATUS_FLAG_RESET); // reset device
a1bb33af UH	309	}
a1bb33af UH	310
ca070ed9	311	SR_PRIV void analyzer_initialize(libusb_device_handle *devh)
a1bb33af UH	312	{
	313	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	314	analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
	315	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	316	}
	317
ca070ed9	318	SR_PRIV void analyzer_wait(libusb_device_handle *devh, int set, int unset)
a1bb33af UH	319	{
a1bb33af UH	320	int status;
fed16f06	321	while (1) {
a1bb33af UH	322	status = gl_reg_read(devh, DEVICE_STATUS);
	323	if ((status & set) && ((status & unset) == 0))
	324	return;
	325	}
	326	}
	327
ca070ed9	328	SR_PRIV void analyzer_read_start(libusb_device_handle *devh)
a1bb33af UH	329	{
	330	int i;
	331
	332	analyzer_write_status(devh, 3, STATUS_FLAG_20 \| STATUS_FLAG_READ);
	333
	334	for (i = 0; i < 8; i++)
	335	(void)gl_reg_read(devh, READ_RAM_STATUS);
	336	}
	337
ca070ed9	338	SR_PRIV int analyzer_read_data(libusb_device_handle devh, void buffer,
fed16f06	339	unsigned int size)
a1bb33af UH	340	{
	341	return gl_read_bulk(devh, buffer, size);
	342	}
	343
ca070ed9	344	SR_PRIV void analyzer_read_stop(libusb_device_handle *devh)
a1bb33af UH	345	{
	346	analyzer_write_status(devh, 3, STATUS_FLAG_20);
	347	analyzer_write_status(devh, 3, STATUS_FLAG_NONE);
	348	}
	349
ca070ed9	350	SR_PRIV void analyzer_start(libusb_device_handle *devh)
a1bb33af UH	351	{
	352	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	353	analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
	354	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	355	analyzer_write_status(devh, 1, STATUS_FLAG_GO);
	356	}
	357
ca070ed9	358	SR_PRIV void analyzer_configure(libusb_device_handle *devh)
a1bb33af	359	{
fed16f06 UH	360	int i;
	361
	362	/* Write_Start_Status */
a1bb33af UH	363	analyzer_write_status(devh, 1, STATUS_FLAG_RESET);
	364	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	365
fed16f06	366	/* Start_Config_Outside_Device ? */
a1bb33af UH	367	analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
	368	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	369
fed16f06	370	/* SetData_To_Frequence_Reg */
a1bb33af UH	371	__analyzer_set_freq(devh, g_freq_value, g_freq_scale);
a1bb33af UH	372
fed16f06	373	/* SetMemory_Length */
a1bb33af UH	374	gl_reg_write(devh, MEMORY_LENGTH, g_memory_size);
a1bb33af UH	375
fed16f06	376	/* Sele_Inside_Outside_Clock */
a1bb33af UH	377	gl_reg_write(devh, CLOCK_SOURCE, 0x03);
a1bb33af UH	378
fed16f06	379	/* Set_Trigger_Status */
a1bb33af UH	380	for (i = 0; i < 9; i++)
	381	gl_reg_write(devh, TRIGGER_STATUS0 + i, g_trigger_status[i]);
	382
	383	__analyzer_set_trigger_count(devh, g_trigger_count);
	384
fed16f06	385	/* Set_Trigger_Level */
a1bb33af UH	386	gl_reg_write(devh, TRIGGER_LEVEL0, 0x31);
	387	gl_reg_write(devh, TRIGGER_LEVEL1, 0x31);
	388	gl_reg_write(devh, TRIGGER_LEVEL2, 0x31);
	389	gl_reg_write(devh, TRIGGER_LEVEL3, 0x31);
	390
fed16f06 UH	391	/* Size of actual memory >> 2 */
fed16f06 UH	392	__analyzer_set_ramsize_trigger_address(devh, g_ramsize_triggerbar_addr);
a1bb33af UH	393	__analyzer_set_triggerbar_address(devh, g_triggerbar_addr);
a1bb33af UH	394
fed16f06	395	/* Set_Dont_Care_TriggerBar */
a1bb33af UH	396	gl_reg_write(devh, DONT_CARE_TRIGGERBAR, 0x01);
a1bb33af UH	397
fed16f06	398	/* Enable_Status */
a1bb33af UH	399	analyzer_set_filter(devh);
a1bb33af UH	400
fed16f06	401	/* Set_Enable_Delay_Time */
a1bb33af UH	402	gl_reg_write(devh, 0x7a, 0x00);
	403	gl_reg_write(devh, 0x7b, 0x00);
	404	analyzer_write_enable_insert_data(devh);
fed16f06	405	__analyzer_set_compression(devh, g_compression);
a1bb33af UH	406	}
a1bb33af UH	407
ca070ed9	408	SR_PRIV void analyzer_add_trigger(int channel, int type)
a1bb33af	409	{
fed16f06 UH	410	int i;
fed16f06 UH	411
a1bb33af UH	412	if ((channel & 0xf) >= 8)
	413	return;
	414
	415	if (type == TRIGGER_HIGH \|\| type == TRIGGER_LOW) {
a1bb33af UH	416	if (channel & CHANNEL_A)
	417	i = 0;
	418	else if (channel & CHANNEL_B)
	419	i = 2;
	420	else if (channel & CHANNEL_C)
	421	i = 4;
	422	else if (channel & CHANNEL_D)
	423	i = 6;
	424	else
	425	return;
	426	if ((channel & 0xf) >= 4) {
	427	i++;
	428	channel -= 4;
	429	}
fed16f06 UH	430	g_trigger_status[i] \|=
fed16f06 UH	431	1 << ((2 * channel) + (type == TRIGGER_LOW ? 1 : 0));
a1bb33af UH	432	} else {
	433	if (type == TRIGGER_POSEDGE)
	434	g_trigger_status[8] = 0x40;
fed16f06	435	else if (type == TRIGGER_NEGEDGE)
a1bb33af UH	436	g_trigger_status[8] = 0x80;
	437	else
	438	g_trigger_status[8] = 0xc0;
	439
fed16f06	440	/* FIXME: Just guessed the index; need to verify. */
a1bb33af UH	441	if (channel & CHANNEL_B)
	442	g_trigger_status[8] += 8;
	443	else if (channel & CHANNEL_C)
	444	g_trigger_status[8] += 16;
	445	else if (channel & CHANNEL_D)
	446	g_trigger_status[8] += 24;
	447	g_trigger_status[8] += channel % 8;
	448	}
	449	}
	450
ca070ed9	451	SR_PRIV void analyzer_add_filter(int channel, int type)
a1bb33af	452	{
fed16f06 UH	453	int i;
fed16f06 UH	454
a1bb33af UH	455	if (type != FILTER_HIGH && type != FILTER_LOW)
	456	return;
	457	if ((channel & 0xf) >= 8)
	458	return;
	459
a1bb33af UH	460	if (channel & CHANNEL_A)
	461	i = 0;
	462	else if (channel & CHANNEL_B)
	463	i = 2;
	464	else if (channel & CHANNEL_C)
	465	i = 4;
	466	else if (channel & CHANNEL_D)
	467	i = 6;
	468	else
	469	return;
fed16f06	470
a1bb33af UH	471	if ((channel & 0xf) >= 4) {
	472	i++;
	473	channel -= 4;
	474	}
fed16f06 UH	475
	476	g_filter_status[i] \|=
	477	1 << ((2 * channel) + (type == FILTER_LOW ? 1 : 0));
	478
a1bb33af UH	479	g_filter_enable = 1;
	480	}
	481
ca070ed9	482	SR_PRIV void analyzer_set_trigger_count(int count)
a1bb33af UH	483	{
	484	g_trigger_count = count;
	485	}
	486
ca070ed9	487	SR_PRIV void analyzer_set_freq(int freq, int scale)
a1bb33af UH	488	{
	489	g_freq_value = freq;
	490	g_freq_scale = scale;
	491	}
	492
ca070ed9	493	SR_PRIV void analyzer_set_memory_size(unsigned int size)
a1bb33af UH	494	{
	495	g_memory_size = size;
	496	}
	497
ca070ed9	498	SR_PRIV void analyzer_set_ramsize_trigger_address(unsigned int address)
a1bb33af UH	499	{
	500	g_ramsize_triggerbar_addr = address;
	501	}
	502
ca070ed9	503	SR_PRIV void analyzer_set_triggerbar_address(unsigned int address)
a1bb33af UH	504	{
	505	g_triggerbar_addr = address;
	506	}
	507
ca070ed9	508	SR_PRIV unsigned int analyzer_read_id(libusb_device_handle *devh)
a1bb33af	509	{
fed16f06 UH	510	return gl_reg_read(devh, DEVICE_ID1) << 8 \| gl_reg_read(devh,
fed16f06 UH	511	DEVICE_ID0);
a1bb33af UH	512	}
a1bb33af UH	513
ca070ed9	514	SR_PRIV unsigned int analyzer_get_stop_address(libusb_device_handle *devh)
a1bb33af	515	{
fed16f06 UH	516	return gl_reg_read(devh, STOP_ADDRESS2) << 16 \| gl_reg_read(devh,
fed16f06 UH	517	STOP_ADDRESS1) << 8 \| gl_reg_read(devh, STOP_ADDRESS0);
a1bb33af UH	518	}
a1bb33af UH	519
ca070ed9	520	SR_PRIV unsigned int analyzer_get_now_address(libusb_device_handle *devh)
a1bb33af	521	{
fed16f06 UH	522	return gl_reg_read(devh, NOW_ADDRESS2) << 16 \| gl_reg_read(devh,
fed16f06 UH	523	NOW_ADDRESS1) << 8 \| gl_reg_read(devh, NOW_ADDRESS0);
a1bb33af UH	524	}
a1bb33af UH	525
ca070ed9	526	SR_PRIV unsigned int analyzer_get_trigger_address(libusb_device_handle *devh)
a1bb33af	527	{
fed16f06 UH	528	return gl_reg_read(devh, TRIGGER_ADDRESS2) << 16 \| gl_reg_read(devh,
fed16f06 UH	529	TRIGGER_ADDRESS1) << 8 \| gl_reg_read(devh, TRIGGER_ADDRESS0);
a1bb33af UH	530	}
a1bb33af UH	531
ca070ed9	532	SR_PRIV void analyzer_set_compression(unsigned int type)
a1bb33af UH	533	{
	534	g_compression = type;
	535	}
	536
ca070ed9	537	SR_PRIV void analyzer_wait_button(libusb_device_handle *devh)
a1bb33af UH	538	{
	539	analyzer_wait(devh, STATUS_BUTTON_PRESSED, 0);
	540	}
	541
ca070ed9	542	SR_PRIV void analyzer_wait_data(libusb_device_handle *devh)
a1bb33af UH	543	{
	544	analyzer_wait(devh, STATUS_READY \| 8, STATUS_BUSY);
	545	}
	546
ca070ed9 UH	547	SR_PRIV int analyzer_decompress(void *input, unsigned int input_len,
ca070ed9 UH	548	void *output, unsigned int output_len)
a1bb33af UH	549	{
	550	unsigned char *in = input;
	551	unsigned char *out = output;
	552	unsigned int A, B, C, count;
	553	unsigned int written = 0;
	554
	555	while (input_len > 0) {
	556	A = *in++;
	557	B = *in++;
	558	C = *in++;
	559	count = (*in++) + 1;
	560
	561	if (count > output_len)
	562	count = output_len;
	563	output_len -= count;
	564	written += count;
	565
	566	while (count--) {
	567	*out++ = A;
	568	*out++ = B;
	569	*out++ = C;
fed16f06	570	out++ = 0; / Channel D */
a1bb33af UH	571	}
	572
	573	input_len -= 4;
	574	if (output_len == 0)
	575	break;
	576	}
	577
	578	return written;
	579	}