[libsigrok.git] / src / hardware / zeroplus-logic-cube / analyzer.c

/*
 * This file is part of the libsigrok project.
 *
 * Copyright (C) 2010 Sven Peter <sven@fail0verflow.com>
 * Copyright (C) 2010 Haxx Enterprises <bushing@gmail.com>
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or
 * without modification, are permitted provided that the following
 * conditions are met:
 *
 * * Redistributions of source code must retain the above copyright notice,
 *   this list of conditions and the following disclaimer.
 *
 * * Redistributions in binary form must reproduce the above copyright notice,
 *   this list of conditions and the following disclaimer in the documentation
 *   and/or other materials provided with the distribution.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 *  THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <config.h>
#include <assert.h>
#include <libsigrok/libsigrok.h>
#include "libsigrok-internal.h"
#include "analyzer.h"
#include "gl_usb.h"
#include "protocol.h"

enum {
	HARD_DATA_CHECK_SUM		= 0x00,
	PASS_WORD,

	DEV_ID0				= 0x10,
	DEV_ID1,

	START_STATUS			= 0x20,
	DEV_STATUS			= 0x21,
	FREQUENCY_REG0			= 0x30,
	FREQUENCY_REG1,
	FREQUENCY_REG2,
	FREQUENCY_REG3,
	FREQUENCY_REG4,
	MEMORY_LENGTH,
	CLOCK_SOURCE,

	TRIGGER_STATUS0			= 0x40,
	TRIGGER_STATUS1,
	TRIGGER_STATUS2,
	TRIGGER_STATUS3,
	TRIGGER_STATUS4,
	TRIGGER_STATUS5,
	TRIGGER_STATUS6,
	TRIGGER_STATUS7,
	TRIGGER_STATUS8,

	TRIGGER_COUNT0			= 0x50,
	TRIGGER_COUNT1,

	TRIGGER_LEVEL0			= 0x55,
	TRIGGER_LEVEL1,
	TRIGGER_LEVEL2,
	TRIGGER_LEVEL3,

	RAMSIZE_TRIGGERBAR_ADDRESS0	= 0x60,
	RAMSIZE_TRIGGERBAR_ADDRESS1,
	RAMSIZE_TRIGGERBAR_ADDRESS2,
	TRIGGERBAR_ADDRESS0,
	TRIGGERBAR_ADDRESS1,
	TRIGGERBAR_ADDRESS2,
	DONT_CARE_TRIGGERBAR,

	FILTER_ENABLE			= 0x70,
	FILTER_STATUS,

	ENABLE_DELAY_TIME0		= 0x7a,
	ENABLE_DELAY_TIME1,

	ENABLE_INSERT_DATA0		= 0x80,
	ENABLE_INSERT_DATA1,
	ENABLE_INSERT_DATA2,
	ENABLE_INSERT_DATA3,
	COMPRESSION_TYPE0,
	COMPRESSION_TYPE1,

	TRIGGER_ADDRESS0		= 0x90,
	TRIGGER_ADDRESS1,
	TRIGGER_ADDRESS2,

	NOW_ADDRESS0			= 0x96,
	NOW_ADDRESS1,
	NOW_ADDRESS2,

	STOP_ADDRESS0			= 0x9b,
	STOP_ADDRESS1,
	STOP_ADDRESS2,

	READ_RAM_STATUS			= 0xa0,
};

static int g_trigger_status[9] = { 0 };
static int g_trigger_count = 1;
static int g_filter_status[8] = { 0 };
static int g_filter_enable = 0;

static int g_freq_value = 1;
static int g_freq_scale = FREQ_SCALE_MHZ;
static int g_memory_size = MEMORY_SIZE_8K;
static int g_ramsize_triggerbar_addr = 2 * 1024;
static int g_triggerbar_addr = 0;
static int g_compression = COMPRESSION_NONE;
static int g_thresh = 0x31; /* 1.5V */

/* Maybe unk specifies an "endpoint" or "register" of sorts. */
static int analyzer_write_status(libusb_device_handle *devh, unsigned char unk,
				 unsigned char flags)
{
	assert(unk <= 3);
	return gl_reg_write(devh, START_STATUS, unk << 6 | flags);
}

#if 0
static int __analyzer_set_freq(libusb_device_handle *devh, int freq, int scale)
{
	int reg0 = 0, divisor = 0, reg2 = 0;

	switch (scale) {
	case FREQ_SCALE_MHZ: /* MHz */
		if (freq >= 100 && freq <= 200) {
			reg0 = freq * 0.1;
			divisor = 1;
			reg2 = 0;
			break;
		}
		if (freq >= 50 && freq < 100) {
			reg0 = freq * 0.2;
			divisor = 2;
			reg2 = 0;
			break;
		}
		if (freq >= 10 && freq < 50) {
			if (freq == 25) {
				reg0 = 25;
				divisor = 5;
				reg2 = 1;
				break;
			} else {
				reg0 = freq * 0.5;
				divisor = 5;
				reg2 = 1;
				break;
			}
		}
		if (freq >= 2 && freq < 10) {
			divisor = 5;
			reg0 = freq * 2;
			reg2 = 2;
			break;
		}
		if (freq == 1) {
			divisor = 5;
			reg2 = 16;
			reg0 = 5;
			break;
		}
		divisor = 5;
		reg0 = 5;
		reg2 = 64;
		break;
	case FREQ_SCALE_HZ: /* Hz */
		if (freq >= 500 && freq < 1000) {
			reg0 = freq * 0.01;
			divisor = 10;
			reg2 = 64;
			break;
		}
		if (freq >= 300 && freq < 500) {
			reg0 = freq * 0.005 * 8;
			divisor = 5;
			reg2 = 67;
			break;
		}
		if (freq >= 100 && freq < 300) {
			reg0 = freq * 0.005 * 16;
			divisor = 5;
			reg2 = 68;
			break;
		}
		divisor = 5;
		reg0 = 5;
		reg2 = 64;
		break;
	case FREQ_SCALE_KHZ: /* kHz */
		if (freq >= 500 && freq < 1000) {
			reg0 = freq * 0.01;
			divisor = 5;
			reg2 = 17;
			break;
		}
		if (freq >= 100 && freq < 500) {
			reg0 = freq * 0.05;
			divisor = 5;
			reg2 = 32;
			break;
		}
		if (freq >= 50 && freq < 100) {
			reg0 = freq * 0.1;
			divisor = 5;
			reg2 = 33;
			break;
		}
		if (freq >= 10 && freq < 50) {
			if (freq == 25) {
				reg0 = 25;
				divisor = 5;
				reg2 = 49;
				break;
			}
			reg0 = freq * 0.5;
			divisor = 5;
			reg2 = 48;
			break;
		}
		if (freq >= 2 && freq < 10) {
			divisor = 5;
			reg0 = freq * 2;
			reg2 = 50;
			break;
		}
		divisor = 5;
		reg0 = 5;
		reg2 = 64;
		break;
	default:
		divisor = 5;
		reg0 = 5;
		reg2 = 64;
		break;
	}

	sr_dbg("Setting samplerate regs (freq=%d, scale=%d): "
	       "reg0: %d, reg1: %d, reg2: %d, reg3: %d.",
	       freq, scale, divisor, reg0, 0x02, reg2);

	if (gl_reg_write(devh, FREQUENCY_REG0, divisor) < 0)
		return -1; /* Divisor maybe? */

	if (gl_reg_write(devh, FREQUENCY_REG1, reg0) < 0)
		return -1; /* 10 / 0.2 */

	if (gl_reg_write(devh, FREQUENCY_REG2, 0x02) < 0)
		return -1; /* Always 2 */

	if (gl_reg_write(devh, FREQUENCY_REG4, reg2) < 0)
		return -1;

	return 0;
}
#endif

/*
 * It seems that ...
 *	FREQUENCT_REG0 - division factor (?)
 *	FREQUENCT_REG1 - multiplication factor (?)
 *	FREQUENCT_REG4 - clock selection (?)
 *
 *	clock selection
 *	0  10MHz  16   1MHz  32 100kHz  48  10kHz  64   1kHz
 *	1   5MHz  17 500kHz  33  50kHz  49   5kHz  65  500Hz
 *	2 2.5MHz   .          .         50 2.5kHz  66  250Hz
 *	.          .          .          .         67  125Hz
 *	.          .          .          .         68 62.5Hz
 */
static int __analyzer_set_freq(libusb_device_handle *devh, int freq, int scale)
{
	struct freq_factor {
		int freq;
		int scale;
		int sel;
		int div;
		int mul;
	};

	static const struct freq_factor f[] = {
		{ 200, FREQ_SCALE_MHZ,  0,  1, 20 },
		{ 150, FREQ_SCALE_MHZ,  0,  1, 15 },
		{ 100, FREQ_SCALE_MHZ,  0,  1, 10 },
		{  80, FREQ_SCALE_MHZ,  0,  2, 16 },
		{  50, FREQ_SCALE_MHZ,  0,  2, 10 },
		{  25, FREQ_SCALE_MHZ,  1,  5, 25 },
		{  10, FREQ_SCALE_MHZ,  1,  5, 10 },
		{   1, FREQ_SCALE_MHZ, 16,  5,  5 },
		{ 800, FREQ_SCALE_KHZ, 17,  5,  8 },
		{ 400, FREQ_SCALE_KHZ, 32,  5, 20 },
		{ 200, FREQ_SCALE_KHZ, 32,  5, 10 },
		{ 100, FREQ_SCALE_KHZ, 32,  5,  5 },
		{  50, FREQ_SCALE_KHZ, 33,  5,  5 },
		{  25, FREQ_SCALE_KHZ, 49,  5, 25 },
		{   5, FREQ_SCALE_KHZ, 50,  5, 10 },
		{   1, FREQ_SCALE_KHZ, 64,  5,  5 },
		{ 500, FREQ_SCALE_HZ,  64, 10,  5 },
		{ 100, FREQ_SCALE_HZ,  68,  5,  8 },
		ALL_ZERO
	};

	int i;

	for (i = 0; f[i].freq; i++) {
		if (scale == f[i].scale && freq == f[i].freq)
			break;
	}
	if (!f[i].freq)
		return -1;

	sr_dbg("Setting samplerate regs (freq=%d, scale=%d): "
	       "reg0: %d, reg1: %d, reg2: %d, reg3: %d.",
	       freq, scale, f[i].div, f[i].mul, 0x02, f[i].sel);

	if (gl_reg_write(devh, FREQUENCY_REG0, f[i].div) < 0)
		return -1;

	if (gl_reg_write(devh, FREQUENCY_REG1, f[i].mul) < 0)
		return -1;

	if (gl_reg_write(devh, FREQUENCY_REG2, 0x02) < 0)
		return -1;

	if (gl_reg_write(devh, FREQUENCY_REG4, f[i].sel) < 0)
		return -1;

	return 0;
}

static void __analyzer_set_ramsize_trigger_address(libusb_device_handle *devh,
						   unsigned int address)
{
	gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
	gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
	gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
}

static void __analyzer_set_triggerbar_address(libusb_device_handle *devh,
					      unsigned int address)
{
	gl_reg_write(devh, TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
	gl_reg_write(devh, TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
	gl_reg_write(devh, TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
}

static void __analyzer_set_compression(libusb_device_handle *devh,
				       unsigned int type)
{
	gl_reg_write(devh, COMPRESSION_TYPE0, (type >> 0) & 0xFF);
	gl_reg_write(devh, COMPRESSION_TYPE1, (type >> 8) & 0xFF);
}

static void __analyzer_set_trigger_count(libusb_device_handle *devh,
					 unsigned int count)
{
	gl_reg_write(devh, TRIGGER_COUNT0, (count >> 0) & 0xFF);
	gl_reg_write(devh, TRIGGER_COUNT1, (count >> 8) & 0xFF);
}

static void analyzer_write_enable_insert_data(libusb_device_handle *devh)
{
	gl_reg_write(devh, ENABLE_INSERT_DATA0, 0x12);
	gl_reg_write(devh, ENABLE_INSERT_DATA1, 0x34);
	gl_reg_write(devh, ENABLE_INSERT_DATA2, 0x56);
	gl_reg_write(devh, ENABLE_INSERT_DATA3, 0x78);
}

static void analyzer_set_filter(libusb_device_handle *devh)
{
	int i;
	gl_reg_write(devh, FILTER_ENABLE, g_filter_enable);
	for (i = 0; i < 8; i++)
		gl_reg_write(devh, FILTER_STATUS + i, g_filter_status[i]);
}

SR_PRIV void analyzer_reset(libusb_device_handle *devh)
{
	analyzer_write_status(devh, 3, STATUS_FLAG_NONE);	// reset device
	analyzer_write_status(devh, 3, STATUS_FLAG_RESET);	// reset device
}

SR_PRIV void analyzer_initialize(libusb_device_handle *devh)
{
	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
}

SR_PRIV void analyzer_wait(libusb_device_handle *devh, int set, int unset)
{
	int status;

	while (1) {
		status = gl_reg_read(devh, DEV_STATUS);
		if ((!set || (status & set)) && ((status & unset) == 0))
			return;
	}
}

SR_PRIV void analyzer_read_start(libusb_device_handle *devh)
{
	analyzer_write_status(devh, 3, STATUS_FLAG_20 | STATUS_FLAG_READ);

	/* Prep for bulk reads */
	gl_reg_read_buf(devh, READ_RAM_STATUS, NULL, 0);
}

SR_PRIV int analyzer_read_data(libusb_device_handle *devh, void *buffer,
		       unsigned int size)
{
	return gl_read_bulk(devh, buffer, size);
}

SR_PRIV void analyzer_read_stop(libusb_device_handle *devh)
{
	analyzer_write_status(devh, 3, STATUS_FLAG_20);
	analyzer_write_status(devh, 3, STATUS_FLAG_NONE);
}

SR_PRIV void analyzer_start(libusb_device_handle *devh)
{
	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	analyzer_write_status(devh, 1, STATUS_FLAG_GO);
}

SR_PRIV void analyzer_configure(libusb_device_handle *devh)
{
	int i;

	/* Write_Start_Status */
	analyzer_write_status(devh, 1, STATUS_FLAG_RESET);
	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);

	/* Start_Config_Outside_Device ? */
	analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);

	/* SetData_To_Frequence_Reg */
	__analyzer_set_freq(devh, g_freq_value, g_freq_scale);

	/* SetMemory_Length */
	gl_reg_write(devh, MEMORY_LENGTH, g_memory_size);

	/* Sele_Inside_Outside_Clock */
	gl_reg_write(devh, CLOCK_SOURCE, 0x03);

	/* Set_Trigger_Status */
	for (i = 0; i < 9; i++)
		gl_reg_write(devh, TRIGGER_STATUS0 + i, g_trigger_status[i]);

	__analyzer_set_trigger_count(devh, g_trigger_count);

	/* Set_Trigger_Level */
	gl_reg_write(devh, TRIGGER_LEVEL0, g_thresh);
	gl_reg_write(devh, TRIGGER_LEVEL1, g_thresh);
	gl_reg_write(devh, TRIGGER_LEVEL2, g_thresh);
	gl_reg_write(devh, TRIGGER_LEVEL3, g_thresh);

	/* Size of actual memory >> 2 */
	__analyzer_set_ramsize_trigger_address(devh, g_ramsize_triggerbar_addr);
	__analyzer_set_triggerbar_address(devh, g_triggerbar_addr);

	/* Set_Dont_Care_TriggerBar */
	gl_reg_write(devh, DONT_CARE_TRIGGERBAR, 0x01);

	/* Enable_Status */
	analyzer_set_filter(devh);

	/* Set_Enable_Delay_Time */
	gl_reg_write(devh, 0x7a, 0x00);
	gl_reg_write(devh, 0x7b, 0x00);
	analyzer_write_enable_insert_data(devh);
	__analyzer_set_compression(devh, g_compression);
}

SR_PRIV int analyzer_add_triggers(const struct sr_dev_inst *sdi)
{
	struct dev_context *devc;
	struct sr_trigger *trigger;
	struct sr_trigger_stage *stage;
	struct sr_trigger_match *match;
	GSList *l, *m;
	int channel;

	devc = sdi->priv;

	if (!(trigger = sr_session_trigger_get(sdi->session)))
		return SR_OK;

	for (l = trigger->stages; l; l = l->next) {
		stage = l->data;
		for (m = stage->matches; m; m = m->next) {
			match = m->data;
			devc->trigger = 1;
			if (!match->channel->enabled)
				/* Ignore disabled channels with a trigger. */
				continue;
			channel = match->channel->index;
			switch (match->match) {
			case SR_TRIGGER_ZERO:
				g_trigger_status[channel / 4] |= 2 << (channel % 4 * 2);
				break;
			case SR_TRIGGER_ONE:
				g_trigger_status[channel / 4] |= 1 << (channel % 4 * 2);
				break;
			default:
				sr_err("Unsupported match %d", match->match);
				return SR_ERR;
			}
		}
	}

	return SR_OK;
}

SR_PRIV void analyzer_add_filter(int channel, int type)
{
	int i;

	if (type != FILTER_HIGH && type != FILTER_LOW)
		return;
	if ((channel & 0xf) >= 8)
		return;

	if (channel & CHANNEL_A)
		i = 0;
	else if (channel & CHANNEL_B)
		i = 2;
	else if (channel & CHANNEL_C)
		i = 4;
	else if (channel & CHANNEL_D)
		i = 6;
	else
		return;

	if ((channel & 0xf) >= 4) {
		i++;
		channel -= 4;
	}

	g_filter_status[i] |=
	    1 << ((2 * channel) + (type == FILTER_LOW ? 1 : 0));

	g_filter_enable = 1;
}

SR_PRIV void analyzer_set_trigger_count(int count)
{
	g_trigger_count = count;
}

SR_PRIV void analyzer_set_freq(int freq, int scale)
{
	g_freq_value = freq;
	g_freq_scale = scale;
}

SR_PRIV void analyzer_set_memory_size(unsigned int size)
{
	g_memory_size = size;
}

SR_PRIV void analyzer_set_ramsize_trigger_address(unsigned int address)
{
	g_ramsize_triggerbar_addr = address;
}

SR_PRIV unsigned int analyzer_get_ramsize_trigger_address(void)
{
	return g_ramsize_triggerbar_addr;
}

SR_PRIV void analyzer_set_triggerbar_address(unsigned int address)
{
	g_triggerbar_addr = address;
}

SR_PRIV unsigned int analyzer_get_triggerbar_address(void)
{
	return g_triggerbar_addr;
}

SR_PRIV unsigned int analyzer_read_status(libusb_device_handle *devh)
{
	return gl_reg_read(devh, DEV_STATUS);
}

SR_PRIV unsigned int analyzer_read_id(libusb_device_handle *devh)
{
	return gl_reg_read(devh, DEV_ID1) << 8 | gl_reg_read(devh, DEV_ID0);
}

SR_PRIV unsigned int analyzer_get_stop_address(libusb_device_handle *devh)
{
	return gl_reg_read(devh, STOP_ADDRESS2) << 16 | gl_reg_read(devh,
			STOP_ADDRESS1) << 8 | gl_reg_read(devh, STOP_ADDRESS0);
}

SR_PRIV unsigned int analyzer_get_now_address(libusb_device_handle *devh)
{
	return gl_reg_read(devh, NOW_ADDRESS2) << 16 | gl_reg_read(devh,
			NOW_ADDRESS1) << 8 | gl_reg_read(devh, NOW_ADDRESS0);
}

SR_PRIV unsigned int analyzer_get_trigger_address(libusb_device_handle *devh)
{
	return gl_reg_read(devh, TRIGGER_ADDRESS2) << 16 | gl_reg_read(devh,
		TRIGGER_ADDRESS1) << 8 | gl_reg_read(devh, TRIGGER_ADDRESS0);
}

SR_PRIV void analyzer_set_compression(unsigned int type)
{
	g_compression = type;
}

SR_PRIV void analyzer_set_voltage_threshold(int thresh)
{
	g_thresh = thresh;
}

SR_PRIV void analyzer_wait_button(libusb_device_handle *devh)
{
	analyzer_wait(devh, STATUS_BUTTON_PRESSED, 0);
}

SR_PRIV void analyzer_wait_data(libusb_device_handle *devh)
{
	analyzer_wait(devh, 0, STATUS_BUSY);
}

SR_PRIV int analyzer_decompress(void *input, unsigned int input_len,
				void *output, unsigned int output_len)
{
	unsigned char *in = input;
	unsigned char *out = output;
	unsigned int A, B, C, count;
	unsigned int written = 0;

	while (input_len > 0) {
		A = *in++;
		B = *in++;
		C = *in++;
		count = (*in++) + 1;

		if (count > output_len)
			count = output_len;
		output_len -= count;
		written += count;

		while (count--) {
			*out++ = A;
			*out++ = B;
			*out++ = C;
			*out++ = 0; /* Channel D */
		}

		input_len -= 4;
		if (output_len == 0)
			break;
	}

	return written;
}
Commit	Line	Data
a1bb33af	1	/*
50985c20	2	* This file is part of the libsigrok project.
fed16f06 UH	3	*
	4	* Copyright (C) 2010 Sven Peter <sven@fail0verflow.com>
	5	* Copyright (C) 2010 Haxx Enterprises <bushing@gmail.com>
	6	* All rights reserved.
	7	*
	8	* Redistribution and use in source and binary forms, with or
	9	* without modification, are permitted provided that the following
	10	* conditions are met:
	11	*
	12	* * Redistributions of source code must retain the above copyright notice,
	13	* this list of conditions and the following disclaimer.
	14	*
	15	* * Redistributions in binary form must reproduce the above copyright notice,
	16	* this list of conditions and the following disclaimer in the documentation
	17	* and/or other materials provided with the distribution.
	18	*
	19	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	20	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	21	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	22	* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
	23	* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
	24	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
	25	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
	26	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
	27	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
	28	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
	29	* THE POSSIBILITY OF SUCH DAMAGE.
	30	*/
a1bb33af	31
6ec6c43b	32	#include <config.h>
fed16f06	33	#include <assert.h>
c1aae900	34	#include <libsigrok/libsigrok.h>
6d116114	35	#include "libsigrok-internal.h"
a1bb33af UH	36	#include "analyzer.h"
a1bb33af UH	37	#include "gl_usb.h"
6d116114	38	#include "protocol.h"
a1bb33af UH	39
a1bb33af UH	40	enum {
fed16f06	41	HARD_DATA_CHECK_SUM = 0x00,
a1bb33af UH	42	PASS_WORD,
a1bb33af UH	43
bb7ef793 UH	44	DEV_ID0 = 0x10,
bb7ef793 UH	45	DEV_ID1,
a1bb33af	46
fed16f06	47	START_STATUS = 0x20,
bb7ef793	48	DEV_STATUS = 0x21,
fed16f06	49	FREQUENCY_REG0 = 0x30,
a1bb33af UH	50	FREQUENCY_REG1,
	51	FREQUENCY_REG2,
	52	FREQUENCY_REG3,
	53	FREQUENCY_REG4,
	54	MEMORY_LENGTH,
	55	CLOCK_SOURCE,
	56
fed16f06	57	TRIGGER_STATUS0 = 0x40,
a1bb33af UH	58	TRIGGER_STATUS1,
	59	TRIGGER_STATUS2,
	60	TRIGGER_STATUS3,
	61	TRIGGER_STATUS4,
	62	TRIGGER_STATUS5,
	63	TRIGGER_STATUS6,
	64	TRIGGER_STATUS7,
	65	TRIGGER_STATUS8,
	66
fed16f06	67	TRIGGER_COUNT0 = 0x50,
a1bb33af UH	68	TRIGGER_COUNT1,
a1bb33af UH	69
fed16f06	70	TRIGGER_LEVEL0 = 0x55,
a1bb33af UH	71	TRIGGER_LEVEL1,
	72	TRIGGER_LEVEL2,
	73	TRIGGER_LEVEL3,
	74
	75	RAMSIZE_TRIGGERBAR_ADDRESS0 = 0x60,
	76	RAMSIZE_TRIGGERBAR_ADDRESS1,
	77	RAMSIZE_TRIGGERBAR_ADDRESS2,
	78	TRIGGERBAR_ADDRESS0,
	79	TRIGGERBAR_ADDRESS1,
	80	TRIGGERBAR_ADDRESS2,
	81	DONT_CARE_TRIGGERBAR,
	82
	83	FILTER_ENABLE = 0x70,
	84	FILTER_STATUS,
	85
fed16f06	86	ENABLE_DELAY_TIME0 = 0x7a,
a1bb33af UH	87	ENABLE_DELAY_TIME1,
a1bb33af UH	88
fed16f06	89	ENABLE_INSERT_DATA0 = 0x80,
a1bb33af UH	90	ENABLE_INSERT_DATA1,
	91	ENABLE_INSERT_DATA2,
	92	ENABLE_INSERT_DATA3,
	93	COMPRESSION_TYPE0,
	94	COMPRESSION_TYPE1,
	95
fed16f06	96	TRIGGER_ADDRESS0 = 0x90,
a1bb33af UH	97	TRIGGER_ADDRESS1,
	98	TRIGGER_ADDRESS2,
	99
fed16f06	100	NOW_ADDRESS0 = 0x96,
a1bb33af UH	101	NOW_ADDRESS1,
	102	NOW_ADDRESS2,
	103
fed16f06	104	STOP_ADDRESS0 = 0x9b,
a1bb33af UH	105	STOP_ADDRESS1,
	106	STOP_ADDRESS2,
	107
fed16f06	108	READ_RAM_STATUS = 0xa0,
a1bb33af UH	109	};
a1bb33af UH	110
fed16f06	111	static int g_trigger_status[9] = { 0 };
a1bb33af	112	static int g_trigger_count = 1;
fed16f06	113	static int g_filter_status[8] = { 0 };
a1bb33af UH	114	static int g_filter_enable = 0;
a1bb33af UH	115
0ab0cb94	116	static int g_freq_value = 1;
a1bb33af	117	static int g_freq_scale = FREQ_SCALE_MHZ;
0ab0cb94 TY	118	static int g_memory_size = MEMORY_SIZE_8K;
	119	static int g_ramsize_triggerbar_addr = 2 * 1024;
	120	static int g_triggerbar_addr = 0;
a1bb33af	121	static int g_compression = COMPRESSION_NONE;
7142d6b9	122	static int g_thresh = 0x31; /* 1.5V */
a1bb33af	123
fed16f06 UH	124	/* Maybe unk specifies an "endpoint" or "register" of sorts. */
	125	static int analyzer_write_status(libusb_device_handle *devh, unsigned char unk,
	126	unsigned char flags)
a1bb33af UH	127	{
	128	assert(unk <= 3);
	129	return gl_reg_write(devh, START_STATUS, unk << 6 \| flags);
	130	}
	131
0ab0cb94	132	#if 0
a1bb33af UH	133	static int __analyzer_set_freq(libusb_device_handle *devh, int freq, int scale)
a1bb33af UH	134	{
fed16f06 UH	135	int reg0 = 0, divisor = 0, reg2 = 0;
fed16f06 UH	136
a1bb33af	137	switch (scale) {
fed16f06 UH	138	case FREQ_SCALE_MHZ: /* MHz */
	139	if (freq >= 100 && freq <= 200) {
	140	reg0 = freq * 0.1;
	141	divisor = 1;
	142	reg2 = 0;
	143	break;
	144	}
	145	if (freq >= 50 && freq < 100) {
	146	reg0 = freq * 0.2;
	147	divisor = 2;
	148	reg2 = 0;
	149	break;
	150	}
	151	if (freq >= 10 && freq < 50) {
	152	if (freq == 25) {
	153	reg0 = 25;
a1bb33af	154	divisor = 5;
fed16f06	155	reg2 = 1;
a1bb33af	156	break;
fed16f06 UH	157	} else {
fed16f06 UH	158	reg0 = freq * 0.5;
a1bb33af	159	divisor = 5;
fed16f06	160	reg2 = 1;
a1bb33af UH	161	break;
a1bb33af UH	162	}
fed16f06 UH	163	}
fed16f06 UH	164	if (freq >= 2 && freq < 10) {
a1bb33af	165	divisor = 5;
fed16f06 UH	166	reg0 = freq * 2;
fed16f06 UH	167	reg2 = 2;
a1bb33af	168	break;
fed16f06 UH	169	}
fed16f06 UH	170	if (freq == 1) {
a1bb33af	171	divisor = 5;
fed16f06	172	reg2 = 16;
a1bb33af	173	reg0 = 5;
fed16f06 UH	174	break;
	175	}
	176	divisor = 5;
	177	reg0 = 5;
	178	reg2 = 64;
	179	break;
	180	case FREQ_SCALE_HZ: /* Hz */
	181	if (freq >= 500 && freq < 1000) {
	182	reg0 = freq * 0.01;
	183	divisor = 10;
a1bb33af UH	184	reg2 = 64;
a1bb33af UH	185	break;
fed16f06 UH	186	}
	187	if (freq >= 300 && freq < 500) {
	188	reg0 = freq * 0.005 * 8;
	189	divisor = 5;
	190	reg2 = 67;
	191	break;
	192	}
	193	if (freq >= 100 && freq < 300) {
	194	reg0 = freq * 0.005 * 16;
	195	divisor = 5;
	196	reg2 = 68;
	197	break;
	198	}
	199	divisor = 5;
	200	reg0 = 5;
	201	reg2 = 64;
	202	break;
38ba2522	203	case FREQ_SCALE_KHZ: /* kHz */
fed16f06 UH	204	if (freq >= 500 && freq < 1000) {
	205	reg0 = freq * 0.01;
	206	divisor = 5;
	207	reg2 = 17;
	208	break;
	209	}
	210	if (freq >= 100 && freq < 500) {
	211	reg0 = freq * 0.05;
	212	divisor = 5;
	213	reg2 = 32;
	214	break;
	215	}
	216	if (freq >= 50 && freq < 100) {
	217	reg0 = freq * 0.1;
	218	divisor = 5;
	219	reg2 = 33;
	220	break;
	221	}
	222	if (freq >= 10 && freq < 50) {
	223	if (freq == 25) {
	224	reg0 = 25;
a1bb33af	225	divisor = 5;
fed16f06	226	reg2 = 49;
a1bb33af UH	227	break;
a1bb33af UH	228	}
fed16f06	229	reg0 = freq * 0.5;
a1bb33af	230	divisor = 5;
fed16f06	231	reg2 = 48;
a1bb33af	232	break;
fed16f06 UH	233	}
fed16f06 UH	234	if (freq >= 2 && freq < 10) {
a1bb33af	235	divisor = 5;
fed16f06 UH	236	reg0 = freq * 2;
fed16f06 UH	237	reg2 = 50;
a1bb33af	238	break;
fed16f06 UH	239	}
	240	divisor = 5;
	241	reg0 = 5;
	242	reg2 = 64;
	243	break;
	244	default:
	245	divisor = 5;
	246	reg0 = 5;
	247	reg2 = 64;
	248	break;
a1bb33af	249	}
c13536fa	250
6d116114	251	sr_dbg("Setting samplerate regs (freq=%d, scale=%d): "
c13536fa UH	252	"reg0: %d, reg1: %d, reg2: %d, reg3: %d.",
	253	freq, scale, divisor, reg0, 0x02, reg2);
	254
a1bb33af	255	if (gl_reg_write(devh, FREQUENCY_REG0, divisor) < 0)
fed16f06	256	return -1; /* Divisor maybe? */
a1bb33af UH	257
a1bb33af UH	258	if (gl_reg_write(devh, FREQUENCY_REG1, reg0) < 0)
fed16f06	259	return -1; /* 10 / 0.2 */
a1bb33af UH	260
a1bb33af UH	261	if (gl_reg_write(devh, FREQUENCY_REG2, 0x02) < 0)
fed16f06	262	return -1; /* Always 2 */
a1bb33af UH	263
	264	if (gl_reg_write(devh, FREQUENCY_REG4, reg2) < 0)
	265	return -1;
	266
	267	return 0;
	268	}
0ab0cb94 TY	269	#endif
	270
	271	/*
	272	* It seems that ...
	273	* FREQUENCT_REG0 - division factor (?)
	274	* FREQUENCT_REG1 - multiplication factor (?)
	275	* FREQUENCT_REG4 - clock selection (?)
	276	*
	277	* clock selection
	278	* 0 10MHz 16 1MHz 32 100kHz 48 10kHz 64 1kHz
	279	* 1 5MHz 17 500kHz 33 50kHz 49 5kHz 65 500Hz
	280	* 2 2.5MHz . . 50 2.5kHz 66 250Hz
	281	* . . . . 67 125Hz
	282	* . . . . 68 62.5Hz
	283	*/
	284	static int __analyzer_set_freq(libusb_device_handle *devh, int freq, int scale)
	285	{
	286	struct freq_factor {
	287	int freq;
	288	int scale;
	289	int sel;
	290	int div;
	291	int mul;
	292	};
	293
	294	static const struct freq_factor f[] = {
	295	{ 200, FREQ_SCALE_MHZ, 0, 1, 20 },
	296	{ 150, FREQ_SCALE_MHZ, 0, 1, 15 },
	297	{ 100, FREQ_SCALE_MHZ, 0, 1, 10 },
	298	{ 80, FREQ_SCALE_MHZ, 0, 2, 16 },
	299	{ 50, FREQ_SCALE_MHZ, 0, 2, 10 },
	300	{ 25, FREQ_SCALE_MHZ, 1, 5, 25 },
	301	{ 10, FREQ_SCALE_MHZ, 1, 5, 10 },
	302	{ 1, FREQ_SCALE_MHZ, 16, 5, 5 },
	303	{ 800, FREQ_SCALE_KHZ, 17, 5, 8 },
	304	{ 400, FREQ_SCALE_KHZ, 32, 5, 20 },
	305	{ 200, FREQ_SCALE_KHZ, 32, 5, 10 },
	306	{ 100, FREQ_SCALE_KHZ, 32, 5, 5 },
	307	{ 50, FREQ_SCALE_KHZ, 33, 5, 5 },
	308	{ 25, FREQ_SCALE_KHZ, 49, 5, 25 },
	309	{ 5, FREQ_SCALE_KHZ, 50, 5, 10 },
	310	{ 1, FREQ_SCALE_KHZ, 64, 5, 5 },
	311	{ 500, FREQ_SCALE_HZ, 64, 10, 5 },
	312	{ 100, FREQ_SCALE_HZ, 68, 5, 8 },
1b4aedc0	313	ALL_ZERO
0ab0cb94 TY	314	};
	315
	316	int i;
	317
	318	for (i = 0; f[i].freq; i++) {
	319	if (scale == f[i].scale && freq == f[i].freq)
	320	break;
	321	}
	322	if (!f[i].freq)
	323	return -1;
	324
6d116114	325	sr_dbg("Setting samplerate regs (freq=%d, scale=%d): "
0ab0cb94 TY	326	"reg0: %d, reg1: %d, reg2: %d, reg3: %d.",
	327	freq, scale, f[i].div, f[i].mul, 0x02, f[i].sel);
	328
	329	if (gl_reg_write(devh, FREQUENCY_REG0, f[i].div) < 0)
	330	return -1;
	331
	332	if (gl_reg_write(devh, FREQUENCY_REG1, f[i].mul) < 0)
	333	return -1;
	334
	335	if (gl_reg_write(devh, FREQUENCY_REG2, 0x02) < 0)
	336	return -1;
	337
	338	if (gl_reg_write(devh, FREQUENCY_REG4, f[i].sel) < 0)
	339	return -1;
	340
	341	return 0;
	342	}
a1bb33af	343
fed16f06 UH	344	static void __analyzer_set_ramsize_trigger_address(libusb_device_handle *devh,
fed16f06 UH	345	unsigned int address)
a1bb33af	346	{
fed16f06 UH	347	gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
fed16f06 UH	348	gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
a1bb33af UH	349	gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
	350	}
	351
fed16f06 UH	352	static void __analyzer_set_triggerbar_address(libusb_device_handle *devh,
fed16f06 UH	353	unsigned int address)
a1bb33af	354	{
fed16f06 UH	355	gl_reg_write(devh, TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
fed16f06 UH	356	gl_reg_write(devh, TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
a1bb33af UH	357	gl_reg_write(devh, TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
	358	}
	359
fed16f06 UH	360	static void __analyzer_set_compression(libusb_device_handle *devh,
fed16f06 UH	361	unsigned int type)
a1bb33af UH	362	{
	363	gl_reg_write(devh, COMPRESSION_TYPE0, (type >> 0) & 0xFF);
	364	gl_reg_write(devh, COMPRESSION_TYPE1, (type >> 8) & 0xFF);
	365	}
	366
fed16f06 UH	367	static void __analyzer_set_trigger_count(libusb_device_handle *devh,
fed16f06 UH	368	unsigned int count)
a1bb33af UH	369	{
	370	gl_reg_write(devh, TRIGGER_COUNT0, (count >> 0) & 0xFF);
	371	gl_reg_write(devh, TRIGGER_COUNT1, (count >> 8) & 0xFF);
	372	}
	373
	374	static void analyzer_write_enable_insert_data(libusb_device_handle *devh)
	375	{
	376	gl_reg_write(devh, ENABLE_INSERT_DATA0, 0x12);
	377	gl_reg_write(devh, ENABLE_INSERT_DATA1, 0x34);
	378	gl_reg_write(devh, ENABLE_INSERT_DATA2, 0x56);
	379	gl_reg_write(devh, ENABLE_INSERT_DATA3, 0x78);
	380	}
	381
	382	static void analyzer_set_filter(libusb_device_handle *devh)
	383	{
	384	int i;
	385	gl_reg_write(devh, FILTER_ENABLE, g_filter_enable);
	386	for (i = 0; i < 8; i++)
	387	gl_reg_write(devh, FILTER_STATUS + i, g_filter_status[i]);
	388	}
	389
ca070ed9	390	SR_PRIV void analyzer_reset(libusb_device_handle *devh)
a1bb33af	391	{
fed16f06 UH	392	analyzer_write_status(devh, 3, STATUS_FLAG_NONE); // reset device
fed16f06 UH	393	analyzer_write_status(devh, 3, STATUS_FLAG_RESET); // reset device
a1bb33af UH	394	}
a1bb33af UH	395
ca070ed9	396	SR_PRIV void analyzer_initialize(libusb_device_handle *devh)
a1bb33af UH	397	{
	398	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	399	analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
	400	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	401	}
	402
ca070ed9	403	SR_PRIV void analyzer_wait(libusb_device_handle *devh, int set, int unset)
a1bb33af UH	404	{
a1bb33af UH	405	int status;
6d116114	406
fed16f06	407	while (1) {
bb7ef793	408	status = gl_reg_read(devh, DEV_STATUS);
d20844e2	409	if ((!set \|\| (status & set)) && ((status & unset) == 0))
a1bb33af UH	410	return;
	411	}
	412	}
	413
ca070ed9	414	SR_PRIV void analyzer_read_start(libusb_device_handle *devh)
a1bb33af	415	{
a1bb33af UH	416	analyzer_write_status(devh, 3, STATUS_FLAG_20 \| STATUS_FLAG_READ);
a1bb33af UH	417
aad03192 RD	418	/* Prep for bulk reads */
aad03192 RD	419	gl_reg_read_buf(devh, READ_RAM_STATUS, NULL, 0);
a1bb33af UH	420	}
a1bb33af UH	421
ca070ed9	422	SR_PRIV int analyzer_read_data(libusb_device_handle devh, void buffer,
fed16f06	423	unsigned int size)
a1bb33af UH	424	{
	425	return gl_read_bulk(devh, buffer, size);
	426	}
	427
ca070ed9	428	SR_PRIV void analyzer_read_stop(libusb_device_handle *devh)
a1bb33af UH	429	{
	430	analyzer_write_status(devh, 3, STATUS_FLAG_20);
	431	analyzer_write_status(devh, 3, STATUS_FLAG_NONE);
	432	}
	433
ca070ed9	434	SR_PRIV void analyzer_start(libusb_device_handle *devh)
a1bb33af UH	435	{
	436	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	437	analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
	438	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	439	analyzer_write_status(devh, 1, STATUS_FLAG_GO);
	440	}
	441
ca070ed9	442	SR_PRIV void analyzer_configure(libusb_device_handle *devh)
a1bb33af	443	{
fed16f06 UH	444	int i;
	445
	446	/* Write_Start_Status */
a1bb33af UH	447	analyzer_write_status(devh, 1, STATUS_FLAG_RESET);
	448	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	449
fed16f06	450	/* Start_Config_Outside_Device ? */
a1bb33af UH	451	analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
	452	analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
	453
fed16f06	454	/* SetData_To_Frequence_Reg */
a1bb33af UH	455	__analyzer_set_freq(devh, g_freq_value, g_freq_scale);
a1bb33af UH	456
fed16f06	457	/* SetMemory_Length */
a1bb33af UH	458	gl_reg_write(devh, MEMORY_LENGTH, g_memory_size);
a1bb33af UH	459
fed16f06	460	/* Sele_Inside_Outside_Clock */
a1bb33af UH	461	gl_reg_write(devh, CLOCK_SOURCE, 0x03);
a1bb33af UH	462
fed16f06	463	/* Set_Trigger_Status */
a1bb33af UH	464	for (i = 0; i < 9; i++)
	465	gl_reg_write(devh, TRIGGER_STATUS0 + i, g_trigger_status[i]);
	466
	467	__analyzer_set_trigger_count(devh, g_trigger_count);
	468
fed16f06	469	/* Set_Trigger_Level */
7142d6b9 RD	470	gl_reg_write(devh, TRIGGER_LEVEL0, g_thresh);
	471	gl_reg_write(devh, TRIGGER_LEVEL1, g_thresh);
	472	gl_reg_write(devh, TRIGGER_LEVEL2, g_thresh);
	473	gl_reg_write(devh, TRIGGER_LEVEL3, g_thresh);
a1bb33af	474
fed16f06 UH	475	/* Size of actual memory >> 2 */
fed16f06 UH	476	__analyzer_set_ramsize_trigger_address(devh, g_ramsize_triggerbar_addr);
a1bb33af UH	477	__analyzer_set_triggerbar_address(devh, g_triggerbar_addr);
a1bb33af UH	478
fed16f06	479	/* Set_Dont_Care_TriggerBar */
bc059b42	480	gl_reg_write(devh, DONT_CARE_TRIGGERBAR, 0x01);
a1bb33af	481
fed16f06	482	/* Enable_Status */
a1bb33af UH	483	analyzer_set_filter(devh);
a1bb33af UH	484
fed16f06	485	/* Set_Enable_Delay_Time */
a1bb33af UH	486	gl_reg_write(devh, 0x7a, 0x00);
	487	gl_reg_write(devh, 0x7b, 0x00);
	488	analyzer_write_enable_insert_data(devh);
fed16f06	489	__analyzer_set_compression(devh, g_compression);
a1bb33af UH	490	}
a1bb33af UH	491
28731bab	492	SR_PRIV int analyzer_add_triggers(const struct sr_dev_inst *sdi)
a1bb33af	493	{
28731bab BV	494	struct dev_context *devc;
	495	struct sr_trigger *trigger;
	496	struct sr_trigger_stage *stage;
	497	struct sr_trigger_match *match;
	498	GSList l, m;
	499	int channel;
	500
	501	devc = sdi->priv;
	502
0812c40e	503	if (!(trigger = sr_session_trigger_get(sdi->session)))
28731bab BV	504	return SR_OK;
	505
	506	for (l = trigger->stages; l; l = l->next) {
	507	stage = l->data;
	508	for (m = stage->matches; m; m = m->next) {
	509	match = m->data;
	510	devc->trigger = 1;
	511	if (!match->channel->enabled)
	512	/* Ignore disabled channels with a trigger. */
	513	continue;
	514	channel = match->channel->index;
	515	switch (match->match) {
	516	case SR_TRIGGER_ZERO:
	517	g_trigger_status[channel / 4] \|= 2 << (channel % 4 * 2);
72d69b7c	518	break;
28731bab BV	519	case SR_TRIGGER_ONE:
	520	g_trigger_status[channel / 4] \|= 1 << (channel % 4 * 2);
	521	break;
	522	default:
	523	sr_err("Unsupported match %d", match->match);
	524	return SR_ERR;
	525	}
	526	}
a1bb33af	527	}
28731bab BV	528
28731bab BV	529	return SR_OK;
a1bb33af UH	530	}
a1bb33af UH	531
ca070ed9	532	SR_PRIV void analyzer_add_filter(int channel, int type)
a1bb33af	533	{
fed16f06 UH	534	int i;
fed16f06 UH	535
a1bb33af UH	536	if (type != FILTER_HIGH && type != FILTER_LOW)
	537	return;
	538	if ((channel & 0xf) >= 8)
	539	return;
	540
a1bb33af UH	541	if (channel & CHANNEL_A)
	542	i = 0;
	543	else if (channel & CHANNEL_B)
	544	i = 2;
	545	else if (channel & CHANNEL_C)
	546	i = 4;
	547	else if (channel & CHANNEL_D)
	548	i = 6;
	549	else
	550	return;
fed16f06	551
a1bb33af UH	552	if ((channel & 0xf) >= 4) {
	553	i++;
	554	channel -= 4;
	555	}
fed16f06 UH	556
	557	g_filter_status[i] \|=
	558	1 << ((2 * channel) + (type == FILTER_LOW ? 1 : 0));
	559
a1bb33af UH	560	g_filter_enable = 1;
	561	}
	562
ca070ed9	563	SR_PRIV void analyzer_set_trigger_count(int count)
a1bb33af UH	564	{
	565	g_trigger_count = count;
	566	}
	567
ca070ed9	568	SR_PRIV void analyzer_set_freq(int freq, int scale)
a1bb33af UH	569	{
	570	g_freq_value = freq;
	571	g_freq_scale = scale;
	572	}
	573
ca070ed9	574	SR_PRIV void analyzer_set_memory_size(unsigned int size)
a1bb33af UH	575	{
	576	g_memory_size = size;
	577	}
	578
ca070ed9	579	SR_PRIV void analyzer_set_ramsize_trigger_address(unsigned int address)
a1bb33af UH	580	{
	581	g_ramsize_triggerbar_addr = address;
	582	}
	583
a864a05b RD	584	SR_PRIV unsigned int analyzer_get_ramsize_trigger_address(void)
	585	{
	586	return g_ramsize_triggerbar_addr;
	587	}
	588
ca070ed9	589	SR_PRIV void analyzer_set_triggerbar_address(unsigned int address)
a1bb33af UH	590	{
	591	g_triggerbar_addr = address;
	592	}
	593
a864a05b RD	594	SR_PRIV unsigned int analyzer_get_triggerbar_address(void)
	595	{
	596	return g_triggerbar_addr;
	597	}
	598
0ab0cb94 TY	599	SR_PRIV unsigned int analyzer_read_status(libusb_device_handle *devh)
	600	{
	601	return gl_reg_read(devh, DEV_STATUS);
	602	}
	603
ca070ed9	604	SR_PRIV unsigned int analyzer_read_id(libusb_device_handle *devh)
a1bb33af	605	{
bb7ef793	606	return gl_reg_read(devh, DEV_ID1) << 8 \| gl_reg_read(devh, DEV_ID0);
a1bb33af UH	607	}
a1bb33af UH	608
ca070ed9	609	SR_PRIV unsigned int analyzer_get_stop_address(libusb_device_handle *devh)
a1bb33af	610	{
fed16f06 UH	611	return gl_reg_read(devh, STOP_ADDRESS2) << 16 \| gl_reg_read(devh,
fed16f06 UH	612	STOP_ADDRESS1) << 8 \| gl_reg_read(devh, STOP_ADDRESS0);
a1bb33af UH	613	}
a1bb33af UH	614
ca070ed9	615	SR_PRIV unsigned int analyzer_get_now_address(libusb_device_handle *devh)
a1bb33af	616	{
fed16f06 UH	617	return gl_reg_read(devh, NOW_ADDRESS2) << 16 \| gl_reg_read(devh,
fed16f06 UH	618	NOW_ADDRESS1) << 8 \| gl_reg_read(devh, NOW_ADDRESS0);
a1bb33af UH	619	}
a1bb33af UH	620
ca070ed9	621	SR_PRIV unsigned int analyzer_get_trigger_address(libusb_device_handle *devh)
a1bb33af	622	{
fed16f06 UH	623	return gl_reg_read(devh, TRIGGER_ADDRESS2) << 16 \| gl_reg_read(devh,
fed16f06 UH	624	TRIGGER_ADDRESS1) << 8 \| gl_reg_read(devh, TRIGGER_ADDRESS0);
a1bb33af UH	625	}
a1bb33af UH	626
ca070ed9	627	SR_PRIV void analyzer_set_compression(unsigned int type)
a1bb33af UH	628	{
	629	g_compression = type;
	630	}
	631
7142d6b9 RD	632	SR_PRIV void analyzer_set_voltage_threshold(int thresh)
	633	{
	634	g_thresh = thresh;
	635	}
	636
ca070ed9	637	SR_PRIV void analyzer_wait_button(libusb_device_handle *devh)
a1bb33af UH	638	{
	639	analyzer_wait(devh, STATUS_BUTTON_PRESSED, 0);
	640	}
	641
ca070ed9	642	SR_PRIV void analyzer_wait_data(libusb_device_handle *devh)
a1bb33af	643	{
d20844e2	644	analyzer_wait(devh, 0, STATUS_BUSY);
a1bb33af UH	645	}
a1bb33af UH	646
ca070ed9 UH	647	SR_PRIV int analyzer_decompress(void *input, unsigned int input_len,
ca070ed9 UH	648	void *output, unsigned int output_len)
a1bb33af UH	649	{
	650	unsigned char *in = input;
	651	unsigned char *out = output;
	652	unsigned int A, B, C, count;
	653	unsigned int written = 0;
	654
	655	while (input_len > 0) {
	656	A = *in++;
	657	B = *in++;
	658	C = *in++;
	659	count = (*in++) + 1;
	660
	661	if (count > output_len)
	662	count = output_len;
	663	output_len -= count;
	664	written += count;
	665
	666	while (count--) {
	667	*out++ = A;
	668	*out++ = B;
	669	*out++ = C;
fed16f06	670	out++ = 0; / Channel D */
a1bb33af UH	671	}
	672
	673	input_len -= 4;
	674	if (output_len == 0)
	675	break;
	676	}
	677
	678	return written;
	679	}