[libsigrok.git] / src / hardware / sysclk-sla5032 / sla5032.c

/*
 * This file is part of the libsigrok project.
 *
 * Copyright (C) 2019 Vitaliy Vorobyov
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <config.h>
#include "sla5032.h"
#include "protocol.h"

/*
 * Register description (all registers are 32bit):
 *
 * Rx - means register with index x (register address is x*4)
 *
 * R0(wr): trigger sel0 (low/high)
 * R0(rd): n*256 samples (post trigger) captured
 *
 * R1(wr): trigger sel1 (level/edge)
 * R1(rd): current sampled value
 *
 * R2(wr): trigger enable mask
 *
 * R2(rd): (status register)
 * b0: 1 - keys entered
 * b1: 1 - triggered
 * b3: 1 - capture done
 *
 * not configured: B6FF9C97, 12FF9C97, 92FF9C97, 16FF9C97, ...
 * configured: A5A5A5A0, after enter keys A5A5A5A1
 *
 * sel1 (one bit per channel):
 *  0 - level triggered
 *  1 - edge triggered
 *
 * sel0 (one bit per channel):
 *  0 - (low level trigger, sel1=0), (falling edge, sel1=1)
 *  1 - (high level trigger, sel1=0), (raising edge, sel1=1)
 *
 * mask (one bit per channel):
 *  0 - disable trigger on channel n
 *  1 - enable trigger on channel n
 *
 * R3: upload base address or num samples (0x300000)
 *
 * R4: pll divisor - 1
 *  0 - div 1 (no division)
 *  1 - div 2
 *  2 - div 3
 *  ...
 *  n-1 - div n
 *
 * R5(rd/wr):
 * b0: 1 - enable pll mul 2, 0 - disable pll mul 2
 * b1: ??
 * b2: ??
 * b3: ??
 * b4:
 * b5: ->0->1 upload next data chunk (to pc)
 * b6: ??
 * b7: 0 - enable pll mul 1.25, 1 - disable pll mul 1.25
 * b8: ??
 *
 * R6: post trigger depth, value x means (x+1)*256 (samples), min value is 1
 * R7: pre trigger depth, value y means (y+1)*256 (samples), min value is 1
 * (x+1)*256 + (y+1)*256 <= 64M
 *
 * R9:  PWM1 HI (1 width-1)
 * R10: PWM1 LO (0 width-1)
 *
 * R11: PWM2 HI (1 width-1)
 * R12: PWM2 LO (0 width-1)
 *
 * R14:
 * 1 - start sample?
 * 0 - upload done?
 *
 * R16: rom key 0
 * R17: rom key 1
 *
 * key0 is F6 81 13 64
 * key1 is 00 00 00 00
 *
 * start sample:
 * r5 <= b2 <= 0
 * r5 <= b3 <= 0
 * r5 <= b5 <= 0
 *
 * r5 <= b6 <= 1
 * r5 <= b1 <= 1
 * r5 <= b1 <= 0
 *
 * r5 <= b8 <= 1
 * r5 <= b8 <= 0
 *
 * r5 <= b6 <= 1
 * r5 <= b2 <= 1
 *
 * read back:
 * r5 <= 0x08  (b3)
 * r5 <= 0x28  (b5,b3)
 */

#define BITSTREAM_NAME "sysclk-sla5032.bit"
#define BITSTREAM_MAX_SIZE (512 * 1024) /* Bitstream size limit for safety */
#define BITSTREAM_HEADER_SIZE 0x69
#define FW_CHUNK_SIZE 250
#define XILINX_SYNC_WORD 0xAA995566

static int la_write_cmd_buf(const struct sr_usb_dev_inst *usb, uint8_t cmd,
		unsigned int addr, unsigned int len, const void *data)
{
	uint8_t *cmd_pkt;
	int ret, xfer_len;
	int cmd_len;

	cmd_pkt = g_try_malloc(len + 10);
	if (!cmd_pkt) {
		ret = SR_ERR_MALLOC;
		goto exit;
	}

	cmd_pkt[0] = cmd;
	cmd_len = 1;
	xfer_len = 0;

	switch(cmd) {
	case CMD_INIT_FW_UPLOAD: /* init firmware upload */
		break;
	case CMD_UPLOAD_FW_CHUNK:
		cmd_pkt[1] = len;
		cmd_len += 1 + len;
		memcpy(&cmd_pkt[2], data, len);
		break;
	case CMD_READ_REG: /* read register */
		cmd_pkt[1] = addr;
		cmd_pkt[2] = len;
		cmd_len += 2;
		break;
	case CMD_WRITE_REG: /* write register */
		cmd_pkt[1] = addr;
		cmd_pkt[2] = len;
		cmd_len += 2 + len;
		memcpy(&cmd_pkt[3], data, len);
		break;
	case CMD_READ_MEM: /* read mem */
		cmd_pkt[1] = (addr >> 8) & 0xFF;
		cmd_pkt[2] = addr & 0xFF;
		cmd_pkt[3] = len;
		cmd_len += 3;
		break;
	case CMD_READ_DATA: /* read samples */
		cmd_pkt[1] = addr;
		cmd_len += 1;
		break;
	}

	ret = libusb_bulk_transfer(usb->devhdl, EP_COMMAND, cmd_pkt, cmd_len,
			&xfer_len, USB_CMD_TIMEOUT_MS);
	if (ret != 0) {
		sr_dbg("Failed to send command %d: %s.",
			   cmd, libusb_error_name(ret));
		return SR_ERR;
	}

	if (xfer_len != cmd_len) {
		sr_dbg("Invalid send command response of length %d.", xfer_len);
		return SR_ERR;
	}

exit:
	g_free(cmd_pkt);
	return ret;
}

static int la_read_reg(const struct sr_usb_dev_inst *usb, unsigned int reg, uint32_t *val)
{
	int ret, xfer_len;
	uint32_t reply;

	ret = la_write_cmd_buf(usb, CMD_READ_REG, reg * sizeof(uint32_t),
			sizeof(reply), NULL); /* rd reg */
	if (ret != SR_OK)
		return ret;

	ret = libusb_bulk_transfer(usb->devhdl, EP_REPLY, (uint8_t *)&reply,
			sizeof(reply), &xfer_len, USB_REPLY_TIMEOUT_MS);
	if (ret != SR_OK)
		return ret;

	if (xfer_len != sizeof(uint32_t)) {
		sr_dbg("Invalid register read response of length %d.", xfer_len);
		return SR_ERR;
	}

	*val = GUINT32_FROM_BE(reply);

	return ret;
}

static int la_write_reg(const struct sr_usb_dev_inst *usb, unsigned int reg, uint32_t val)
{
	uint32_t val_be;

	val_be = GUINT32_TO_BE(val);

	return la_write_cmd_buf(usb, CMD_WRITE_REG, reg * sizeof(uint32_t),
			sizeof(val_be), &val_be); /* wr reg */
}

static int la_read_mem(const struct sr_usb_dev_inst *usb, unsigned int addr, unsigned int len, void *data)
{
	int ret, xfer_len;

	ret = la_write_cmd_buf(usb, CMD_READ_MEM, addr, len, NULL); /* rd mem */
	if (ret != SR_OK)
		return ret;

	xfer_len = 0;
	ret = libusb_bulk_transfer(usb->devhdl, EP_REPLY, (uint8_t *)data,
			len, &xfer_len, USB_REPLY_TIMEOUT_MS);
	if (xfer_len != (int)len) {
		sr_dbg("Invalid memory read response of length %d.", xfer_len);
		return SR_ERR;
	}

	return ret;
}

static int la_read_samples(const struct sr_usb_dev_inst *usb, unsigned int addr)
{
	return la_write_cmd_buf(usb, CMD_READ_DATA, addr, 0, NULL); /* rd samples */
}

SR_PRIV int sla5032_set_depth(const struct sr_usb_dev_inst *usb, uint32_t pre, uint32_t post)
{
	int ret;

	/* (pre + 1)*256 + (post + 1)*256 <= 64*1024*1024 */
	ret = la_write_reg(usb, 7, pre);
	if (ret != SR_OK)
		return ret;

	return la_write_reg(usb, 6, post);
}

SR_PRIV int sla5032_set_triggers(const struct sr_usb_dev_inst *usb,
		uint32_t trg_value, uint32_t trg_edge_mask, uint32_t trg_mask)
{
	int ret;

	sr_dbg("set trigger: val: %08X, e_mask: %08X, mask: %08X.", trg_value,
		trg_edge_mask, trg_mask);

	ret = la_write_reg(usb, 0, trg_value);
	if (ret != SR_OK)
		return ret;

	ret = la_write_reg(usb, 1, trg_edge_mask);
	if (ret != SR_OK)
		return ret;

	return la_write_reg(usb, 2, trg_mask);
}

static int la_set_res_reg_bit(const struct sr_usb_dev_inst *usb,
		unsigned int reg, unsigned int bit, unsigned int set_bit)
{
	int ret;
	uint32_t v;

	v = 0;
	ret = la_read_reg(usb, reg, &v);
	if (ret != SR_OK)
		return ret;

	if (set_bit)
		v |= (1u << bit);
	else
		v &= ~(1u << bit);

	return la_write_reg(usb, reg, v);
}

struct pll_tbl_entry_t
{
	unsigned int sr;
	uint32_t pll_div_minus_1;
	unsigned int pll_mul_flags;
};

enum {
	PLL_MUL2 = 1, /* x2 */
	PLL_MUL1_25 = 2, /* x1.25 */
};

static const struct pll_tbl_entry_t pll_tbl[] = {
	{ 500000000,     0, PLL_MUL2 | PLL_MUL1_25 }, /* 500M = f*2*1.25/1 */
	{ 400000000,     0, PLL_MUL2               }, /* 400M = f*2/1      */
	{ 250000000,     0, PLL_MUL1_25            }, /* 250M = f*1.25/1   */
	{ 200000000,     0, 0                      }, /* 200M = f/1        */
	{ 100000000,     1, 0                      }, /* 100M = f/2        */
	{  50000000,     3, 0                      }, /*  50M = f/4        */
	{  25000000,     7, 0                      }, /*  25M = f/8        */
	{  20000000,     9, 0                      }, /*  20M = f/10       */
	{  10000000,    19, 0                      }, /*  10M = f/20       */
	{   5000000,    39, 0                      }, /*   5M = f/40       */
	{   2000000,    99, 0                      }, /*   2M = f/100      */
	{   1000000,   199, 0                      }, /*   1M = f/200      */
	{    500000,   399, 0                      }, /* 500k = f/400      */
	{    200000,   999, 0                      }, /* 200k = f/1000     */
	{    100000,  1999, 0                      }, /* 100k = f/2000     */
	{     50000,  3999, 0                      }, /*  50k = f/4000     */
	{     20000,  9999, 0                      }, /*  20k = f/10000    */
	{     10000, 19999, 0                      }, /*  10k = f/20000    */
	{      5000, 39999, 0                      }, /*   5k = f/40000    */
	{      2000, 99999, 0                      }, /*   2k = f/100000   */
};

SR_PRIV int sla5032_set_samplerate(const struct sr_usb_dev_inst *usb, unsigned int sr)
{
	int i, ret;
	const struct pll_tbl_entry_t *e;

	e = NULL;
	for (i = 0; i < (int)ARRAY_SIZE(pll_tbl); i++) {
		if (sr == pll_tbl[i].sr) {
			e = &pll_tbl[i];
			break;
		}
	}

	if (!e)
		return SR_ERR_SAMPLERATE;

	sr_dbg("set sample rate: %u.", e->sr);

	ret = la_write_reg(usb, 4, e->pll_div_minus_1);
	if (ret != SR_OK)
		return ret;

	ret = la_set_res_reg_bit(usb, 5, 0,
		(e->pll_mul_flags & PLL_MUL2) ? 1 : 0); /* bit0 (1=en_mul2) */
	if (ret != SR_OK)
		return ret;

	return la_set_res_reg_bit(usb, 5, 7,
		(e->pll_mul_flags & PLL_MUL1_25) ? 0 : 1); /* bit7 (0=en_mul_1.25) */
}

SR_PRIV int sla5032_start_sample(const struct sr_usb_dev_inst *usb)
{
	int ret;

	ret = la_write_reg(usb, 14, 1);
	if (ret != SR_OK)
		return ret;

	ret = la_set_res_reg_bit(usb, 5, 2, 0);
	if (ret != SR_OK)
		return ret;

	ret = la_set_res_reg_bit(usb, 5, 3, 0);
	if (ret != SR_OK)
		return ret;

	ret = la_set_res_reg_bit(usb, 5, 5, 0);
	if (ret != SR_OK)
		return ret;

	ret = la_set_res_reg_bit(usb, 5, 6, 1);
	if (ret != SR_OK)
		return ret;

	ret = la_set_res_reg_bit(usb, 5, 1, 1);
	if (ret != SR_OK)
		return ret;

	ret = la_set_res_reg_bit(usb, 5, 1, 0);
	if (ret != SR_OK)
		return ret;

	ret = la_set_res_reg_bit(usb, 5, 8, 1);
	if (ret != SR_OK)
		return ret;

	ret = la_set_res_reg_bit(usb, 5, 8, 0);
	if (ret != SR_OK)
		return ret;

	ret = la_set_res_reg_bit(usb, 5, 6, 1);
	if (ret != SR_OK)
		return ret;

	return la_set_res_reg_bit(usb, 5, 2, 1);
}

SR_PRIV int sla5032_get_status(const struct sr_usb_dev_inst *usb, uint32_t status[3])
{
	int ret;
	uint32_t v;

	ret = la_read_reg(usb, 1, &status[0]);
	if (ret != SR_OK)
		return ret;

	status[1] = 1; /* wait trigger */

	ret = la_read_reg(usb, 0, &status[2]);
	if (ret != SR_OK)
		return ret;

	v = 0;
	ret = la_read_reg(usb, 2, &v);
	if (ret != SR_OK)
		return ret;

	if (v & 8) {
		status[1] = 3; /* sample done */
		sr_dbg("get status, reg2: %08X.", v);
	} else if (v & 2) {
		status[1] = 2; /* triggered */
	}

	return ret;
}

static int la_read_samples_data(const struct sr_usb_dev_inst *usb, void *buf,
		unsigned int len, int *xfer_len)
{
	return libusb_bulk_transfer(usb->devhdl, EP_DATA, (uint8_t *)buf, len,
			xfer_len, USB_DATA_TIMEOUT_MS);
}

SR_PRIV int sla5032_read_data_chunk(const struct sr_usb_dev_inst *usb,
		void *buf, unsigned int len, int *xfer_len)
{
	int ret;

	ret = la_read_samples(usb, 3);
	if (ret != SR_OK)
		return ret;

	ret = la_write_reg(usb, 3, 0x300000);
	if (ret != SR_OK)
		return ret;

	ret = la_set_res_reg_bit(usb, 5, 4, 0);
	if (ret != SR_OK)
		return ret;

	ret = la_set_res_reg_bit(usb, 5, 4, 1);
	if (ret != SR_OK)
		return ret;

	return la_read_samples_data(usb, buf, len, xfer_len);
}

SR_PRIV int sla5032_set_read_back(const struct sr_usb_dev_inst *usb)
{
	int ret;

	ret = la_write_reg(usb, 5, 0x08);
	if (ret != SR_OK)
		return ret;

	return la_write_reg(usb, 5, 0x28);
}

SR_PRIV int sla5032_set_pwm1(const struct sr_usb_dev_inst* usb, uint32_t hi, uint32_t lo)
{
	int ret;

	ret = la_write_reg(usb, 9, hi);
	if (ret != SR_OK)
		return ret;

	return la_write_reg(usb, 10, lo);
}

SR_PRIV int sla5032_set_pwm2(const struct sr_usb_dev_inst* usb, uint32_t hi, uint32_t lo)
{
	int ret;

	ret = la_write_reg(usb, 11, hi);
	if (ret != SR_OK)
		return ret;

	return la_write_reg(usb, 12, lo);
}

SR_PRIV int sla5032_write_reg14_zero(const struct sr_usb_dev_inst* usb)
{
	return la_write_reg(usb, 14, 0);
}

static int la_cfg_fpga_done(const struct sr_usb_dev_inst *usb, unsigned int addr)
{
	uint8_t done_key[8];
	uint32_t k0, k1;
	unsigned int reg2;
	int ret;

	memset(done_key, 0, sizeof(done_key));

	ret = la_read_mem(usb, addr, sizeof(done_key), done_key); /* read key from eeprom */
	if (ret != SR_OK)
		return ret;

	k0 = RL32(done_key);	 /* 0x641381F6 */
	k1 = RL32(done_key + 4); /* 0x00000000 */

	sr_dbg("cfg fpga done, k0: %08X, k1: %08X.", k0, k1);

	ret = la_write_reg(usb, 16, k0);
	if (ret != SR_OK)
		return ret;

	ret = la_write_reg(usb, 17, k1);
	if (ret != SR_OK)
		return ret;

	reg2 = 0;
	ret = la_read_reg(usb, 2, &reg2);

	sr_dbg("cfg fpga done, reg2: %08X.", reg2);

	return ret;
}

/*
 * Load a bitstream file into memory. Returns a newly allocated array
 * consisting of a 32-bit length field followed by the bitstream data.
 */
static unsigned char *load_bitstream(struct sr_context *ctx,
					const char *name, int *length_p)
{
	struct sr_resource fw;
	unsigned char *stream, *fw_data;
	ssize_t length, count;

	if (sr_resource_open(ctx, &fw, SR_RESOURCE_FIRMWARE, name) != SR_OK)
		return NULL;

	if (fw.size <= BITSTREAM_HEADER_SIZE || fw.size > BITSTREAM_MAX_SIZE) {
		sr_err("Refusing to load bitstream of unreasonable size "
			   "(%" PRIu64 " bytes).", fw.size);
		sr_resource_close(ctx, &fw);
		return NULL;
	}

	stream = g_try_malloc(fw.size);
	if (!stream) {
		sr_err("Failed to allocate bitstream buffer.");
		sr_resource_close(ctx, &fw);
		return NULL;
	}

	count = sr_resource_read(ctx, &fw, stream, fw.size);
	sr_resource_close(ctx, &fw);

	if (count != (ssize_t)fw.size) {
		sr_err("Failed to read bitstream '%s'.", name);
		g_free(stream);
		return NULL;
	}

	if (RB32(stream + BITSTREAM_HEADER_SIZE) != XILINX_SYNC_WORD) {
		sr_err("Invalid bitstream signature.");
		g_free(stream);
		return NULL;
	}

	length = fw.size - BITSTREAM_HEADER_SIZE + 0x100;
	fw_data = g_try_malloc(length);
	if (!fw_data) {
		sr_err("Failed to allocate bitstream aligned buffer.");
		return NULL;
	}

	memset(fw_data, 0xFF, 0x100);
	memcpy(fw_data + 0x100, stream + BITSTREAM_HEADER_SIZE,
			fw.size - BITSTREAM_HEADER_SIZE);
	g_free(stream);

	*length_p = length;

	return fw_data;
}

static int sla5032_is_configured(const struct sr_usb_dev_inst* usb, gboolean *is_configured)
{
	int ret;
	uint32_t reg2;

	reg2 = 0;
	ret = la_read_reg(usb, 2, &reg2);
	if (ret == SR_OK)
		*is_configured = (reg2 & 0xFFFFFFF1) == 0xA5A5A5A1 ? TRUE : FALSE;

	return ret;
}

/* Load a Binary File from the firmware directory, transfer it to the device. */
static int sla5032_send_bitstream(struct sr_context *ctx,
		const struct sr_usb_dev_inst *usb, const char *name)
{
	unsigned char *stream;
	int ret, length, i, n, m;
	uint32_t reg2;

	if (!ctx || !usb || !name)
		return SR_ERR_BUG;

	stream = load_bitstream(ctx, name, &length);
	if (!stream)
		return SR_ERR;

	sr_dbg("Downloading FPGA bitstream '%s'.", name);

	reg2 = 0;
	ret = la_read_reg(usb, 2, &reg2);
	sr_dbg("send bitstream, reg2: %08X.", reg2);

	/* Transfer the entire bitstream in one URB. */
	ret = la_write_cmd_buf(usb, CMD_INIT_FW_UPLOAD, 0, 0, NULL); /* init firmware upload */
	if (ret != SR_OK) {
		g_free(stream);
		return ret;
	}

	n = length / FW_CHUNK_SIZE;
	m = length % FW_CHUNK_SIZE;

	for (i = 0; i < n; i++) {
		/* upload firmware chunk */
		ret = la_write_cmd_buf(usb, CMD_UPLOAD_FW_CHUNK, 0,
				FW_CHUNK_SIZE, &stream[i * FW_CHUNK_SIZE]);

		if (ret != SR_OK) {
			g_free(stream);
			return ret;
		}
	}

	if (m != 0) {
		/* upload firmware last chunk */
		ret = la_write_cmd_buf(usb, CMD_UPLOAD_FW_CHUNK, 0, m,
				&stream[n * FW_CHUNK_SIZE]);

		if (ret != SR_OK) {
			g_free(stream);
			return ret;
		}
	}

	g_free(stream);

	la_cfg_fpga_done(usb, 4000);

	sla5032_write_reg14_zero(usb);

	sr_dbg("FPGA bitstream download of %d bytes done.", length);

	return SR_OK;
}

/* Select and transfer FPGA bitstream for the current configuration. */
SR_PRIV int sla5032_apply_fpga_config(const struct sr_dev_inst *sdi)
{
	struct dev_context *devc;
	struct drv_context *drvc;
	int ret;
	gboolean is_configured;

	devc = sdi->priv;
	drvc = sdi->driver->context;

	if (FPGA_NOCONF != devc->active_fpga_config)
		return SR_OK; /* No change. */

	is_configured = FALSE;
	ret = sla5032_is_configured(sdi->conn, &is_configured);
	if (ret != SR_OK)
		return ret;

	if (is_configured) {
		devc->active_fpga_config = FPGA_CONF;
		return ret;
	}

	sr_dbg("FPGA not configured, send bitstream.");
	ret = sla5032_send_bitstream(drvc->sr_ctx, sdi->conn, BITSTREAM_NAME);
	devc->active_fpga_config = (ret == SR_OK) ? FPGA_CONF : FPGA_NOCONF;

	return ret;
}
Commit	Line	Data
8da8c826 VV	1	/*
	2	* This file is part of the libsigrok project.
	3	*
	4	* Copyright (C) 2019 Vitaliy Vorobyov
	5	*
	6	* This program is free software: you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation, either version 3 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include <config.h>
	21	#include "sla5032.h"
	22	#include "protocol.h"
	23
	24	/*
	25	* Register description (all registers are 32bit):
	26	*
	27	* Rx - means register with index x (register address is x*4)
	28	*
	29	* R0(wr): trigger sel0 (low/high)
	30	* R0(rd): n*256 samples (post trigger) captured
	31	*
	32	* R1(wr): trigger sel1 (level/edge)
	33	* R1(rd): current sampled value
	34	*
	35	* R2(wr): trigger enable mask
	36	*
	37	* R2(rd): (status register)
	38	* b0: 1 - keys entered
	39	* b1: 1 - triggered
	40	* b3: 1 - capture done
	41	*
	42	* not configured: B6FF9C97, 12FF9C97, 92FF9C97, 16FF9C97, ...
	43	* configured: A5A5A5A0, after enter keys A5A5A5A1
	44	*
	45	* sel1 (one bit per channel):
	46	* 0 - level triggered
	47	* 1 - edge triggered
	48	*
	49	* sel0 (one bit per channel):
	50	* 0 - (low level trigger, sel1=0), (falling edge, sel1=1)
	51	* 1 - (high level trigger, sel1=0), (raising edge, sel1=1)
	52	*
	53	* mask (one bit per channel):
	54	* 0 - disable trigger on channel n
	55	* 1 - enable trigger on channel n
	56	*
	57	* R3: upload base address or num samples (0x300000)
	58	*
	59	* R4: pll divisor - 1
	60	* 0 - div 1 (no division)
	61	* 1 - div 2
	62	* 2 - div 3
	63	* ...
	64	* n-1 - div n
65	*
66	* R5(rd/wr):
67	* b0: 1 - enable pll mul 2, 0 - disable pll mul 2
68	* b1: ??
69	* b2: ??
70	* b3: ??
71	* b4:
72	* b5: ->0->1 upload next data chunk (to pc)
73	* b6: ??
74	* b7: 0 - enable pll mul 1.25, 1 - disable pll mul 1.25
75	* b8: ??
76	*
77	* R6: post trigger depth, value x means (x+1)*256 (samples), min value is 1
78	* R7: pre trigger depth, value y means (y+1)*256 (samples), min value is 1
79	* (x+1)256 + (y+1)256 <= 64M
80	*
81	* R9: PWM1 HI (1 width-1)
82	* R10: PWM1 LO (0 width-1)
83	*
84	* R11: PWM2 HI (1 width-1)
85	* R12: PWM2 LO (0 width-1)
86	*
87	* R14:
88	* 1 - start sample?
89	* 0 - upload done?
90	*
91	* R16: rom key 0
92	* R17: rom key 1
93	*
94	* key0 is F6 81 13 64
95	* key1 is 00 00 00 00
96	*
97	* start sample:
98	* r5 <= b2 <= 0
99	* r5 <= b3 <= 0
100	* r5 <= b5 <= 0
101	*
102	* r5 <= b6 <= 1
103	* r5 <= b1 <= 1
104	* r5 <= b1 <= 0
105	*
106	* r5 <= b8 <= 1
107	* r5 <= b8 <= 0
108	*
109	* r5 <= b6 <= 1
110	* r5 <= b2 <= 1
111	*
112	* read back:
113	* r5 <= 0x08 (b3)
114	* r5 <= 0x28 (b5,b3)
115	*/
116
117	#define BITSTREAM_NAME "sysclk-sla5032.bit"
118	#define BITSTREAM_MAX_SIZE (512 * 1024) /* Bitstream size limit for safety */
119	#define BITSTREAM_HEADER_SIZE 0x69
120	#define FW_CHUNK_SIZE 250
121	#define XILINX_SYNC_WORD 0xAA995566
122
123	static int la_write_cmd_buf(const struct sr_usb_dev_inst *usb, uint8_t cmd,
124	unsigned int addr, unsigned int len, const void *data)
125	{
126	uint8_t *cmd_pkt;
127	int ret, xfer_len;
128	int cmd_len;
129
130	cmd_pkt = g_try_malloc(len + 10);
131	if (!cmd_pkt) {
132	ret = SR_ERR_MALLOC;
133	goto exit;
134	}
135
136	cmd_pkt[0] = cmd;
137	cmd_len = 1;
138	xfer_len = 0;
139
140	switch(cmd) {
141	case CMD_INIT_FW_UPLOAD: /* init firmware upload */
142	break;
143	case CMD_UPLOAD_FW_CHUNK:
144	cmd_pkt[1] = len;
145	cmd_len += 1 + len;
146	memcpy(&cmd_pkt[2], data, len);
147	break;
148	case CMD_READ_REG: /* read register */
149	cmd_pkt[1] = addr;
150	cmd_pkt[2] = len;
151	cmd_len += 2;
152	break;
153	case CMD_WRITE_REG: /* write register */
154	cmd_pkt[1] = addr;
155	cmd_pkt[2] = len;
156	cmd_len += 2 + len;
157	memcpy(&cmd_pkt[3], data, len);
158	break;
159	case CMD_READ_MEM: /* read mem */
160	cmd_pkt[1] = (addr >> 8) & 0xFF;
161	cmd_pkt[2] = addr & 0xFF;
162	cmd_pkt[3] = len;
163	cmd_len += 3;
164	break;
165	case CMD_READ_DATA: /* read samples */
166	cmd_pkt[1] = addr;
167	cmd_len += 1;
168	break;
169	}
170
171	ret = libusb_bulk_transfer(usb->devhdl, EP_COMMAND, cmd_pkt, cmd_len,
172	&xfer_len, USB_CMD_TIMEOUT_MS);
173	if (ret != 0) {
174	sr_dbg("Failed to send command %d: %s.",
175	cmd, libusb_error_name(ret));
176	return SR_ERR;
177	}
178
179	if (xfer_len != cmd_len) {
180	sr_dbg("Invalid send command response of length %d.", xfer_len);
181	return SR_ERR;
182	}
183
184	exit:
185	g_free(cmd_pkt);
186	return ret;
187	}
188
189	static int la_read_reg(const struct sr_usb_dev_inst usb, unsigned int reg, uint32_t val)
190	{
191	int ret, xfer_len;
192	uint32_t reply;
193
194	ret = la_write_cmd_buf(usb, CMD_READ_REG, reg * sizeof(uint32_t),
195	sizeof(reply), NULL); /* rd reg */
196	if (ret != SR_OK)
197	return ret;
198
199	ret = libusb_bulk_transfer(usb->devhdl, EP_REPLY, (uint8_t *)&reply,
200	sizeof(reply), &xfer_len, USB_REPLY_TIMEOUT_MS);
201	if (ret != SR_OK)
202	return ret;
203
204	if (xfer_len != sizeof(uint32_t)) {
205	sr_dbg("Invalid register read response of length %d.", xfer_len);
206	return SR_ERR;
207	}
208
209	*val = GUINT32_FROM_BE(reply);
210
211	return ret;
212	}
213
214	static int la_write_reg(const struct sr_usb_dev_inst *usb, unsigned int reg, uint32_t val)
215	{
8da8c826 VV	216	uint32_t val_be;
	217
	218	val_be = GUINT32_TO_BE(val);
	219
d57a1143	220	return la_write_cmd_buf(usb, CMD_WRITE_REG, reg * sizeof(uint32_t),
8da8c826	221	sizeof(val_be), &val_be); /* wr reg */
8da8c826 VV	222	}
	223
	224	static int la_read_mem(const struct sr_usb_dev_inst usb, unsigned int addr, unsigned int len, void data)
	225	{
	226	int ret, xfer_len;
	227
	228	ret = la_write_cmd_buf(usb, CMD_READ_MEM, addr, len, NULL); /* rd mem */
	229	if (ret != SR_OK)
	230	return ret;
	231
	232	xfer_len = 0;
	233	ret = libusb_bulk_transfer(usb->devhdl, EP_REPLY, (uint8_t *)data,
	234	len, &xfer_len, USB_REPLY_TIMEOUT_MS);
	235	if (xfer_len != (int)len) {
	236	sr_dbg("Invalid memory read response of length %d.", xfer_len);
	237	return SR_ERR;
	238	}
	239
	240	return ret;
	241	}
	242
	243	static int la_read_samples(const struct sr_usb_dev_inst *usb, unsigned int addr)
	244	{
d57a1143	245	return la_write_cmd_buf(usb, CMD_READ_DATA, addr, 0, NULL); /* rd samples */
8da8c826 VV	246	}
	247
	248	SR_PRIV int sla5032_set_depth(const struct sr_usb_dev_inst *usb, uint32_t pre, uint32_t post)
	249	{
	250	int ret;
	251
	252	/* (pre + 1)256 + (post + 1)256 <= 6410241024 */
	253	ret = la_write_reg(usb, 7, pre);
	254	if (ret != SR_OK)
	255	return ret;
	256
d57a1143	257	return la_write_reg(usb, 6, post);
8da8c826 VV	258	}
	259
	260	SR_PRIV int sla5032_set_triggers(const struct sr_usb_dev_inst *usb,
	261	uint32_t trg_value, uint32_t trg_edge_mask, uint32_t trg_mask)
	262	{
	263	int ret;
	264
	265	sr_dbg("set trigger: val: %08X, e_mask: %08X, mask: %08X.", trg_value,
	266	trg_edge_mask, trg_mask);
	267
	268	ret = la_write_reg(usb, 0, trg_value);
	269	if (ret != SR_OK)
	270	return ret;
	271
	272	ret = la_write_reg(usb, 1, trg_edge_mask);
	273	if (ret != SR_OK)
	274	return ret;
	275
d57a1143	276	return la_write_reg(usb, 2, trg_mask);
8da8c826 VV	277	}
	278
	279	static int la_set_res_reg_bit(const struct sr_usb_dev_inst *usb,
	280	unsigned int reg, unsigned int bit, unsigned int set_bit)
	281	{
	282	int ret;
	283	uint32_t v;
	284
	285	v = 0;
	286	ret = la_read_reg(usb, reg, &v);
	287	if (ret != SR_OK)
	288	return ret;
	289
	290	if (set_bit)
	291	v \|= (1u << bit);
	292	else
	293	v &= ~(1u << bit);
	294
d57a1143	295	return la_write_reg(usb, reg, v);
8da8c826 VV	296	}
	297
	298	struct pll_tbl_entry_t
	299	{
	300	unsigned int sr;
	301	uint32_t pll_div_minus_1;
	302	unsigned int pll_mul_flags;
	303	};
	304
	305	enum {
	306	PLL_MUL2 = 1, /* x2 */
	307	PLL_MUL1_25 = 2, /* x1.25 */
	308	};
	309
	310	static const struct pll_tbl_entry_t pll_tbl[] = {
	311	{ 500000000, 0, PLL_MUL2 \| PLL_MUL1_25 }, /* 500M = f21.25/1 */
	312	{ 400000000, 0, PLL_MUL2 }, /* 400M = f2/1 /
	313	{ 250000000, 0, PLL_MUL1_25 }, /* 250M = f1.25/1 /
	314	{ 200000000, 0, 0 }, /* 200M = f/1 */
	315	{ 100000000, 1, 0 }, /* 100M = f/2 */
	316	{ 50000000, 3, 0 }, /* 50M = f/4 */
	317	{ 25000000, 7, 0 }, /* 25M = f/8 */
	318	{ 20000000, 9, 0 }, /* 20M = f/10 */
	319	{ 10000000, 19, 0 }, /* 10M = f/20 */
	320	{ 5000000, 39, 0 }, /* 5M = f/40 */
	321	{ 2000000, 99, 0 }, /* 2M = f/100 */
	322	{ 1000000, 199, 0 }, /* 1M = f/200 */
	323	{ 500000, 399, 0 }, /* 500k = f/400 */
	324	{ 200000, 999, 0 }, /* 200k = f/1000 */
	325	{ 100000, 1999, 0 }, /* 100k = f/2000 */
	326	{ 50000, 3999, 0 }, /* 50k = f/4000 */
	327	{ 20000, 9999, 0 }, /* 20k = f/10000 */
	328	{ 10000, 19999, 0 }, /* 10k = f/20000 */
	329	{ 5000, 39999, 0 }, /* 5k = f/40000 */
	330	{ 2000, 99999, 0 }, /* 2k = f/100000 */
	331	};
	332
	333	SR_PRIV int sla5032_set_samplerate(const struct sr_usb_dev_inst *usb, unsigned int sr)
	334	{
	335	int i, ret;
	336	const struct pll_tbl_entry_t *e;
	337
	338	e = NULL;
	339	for (i = 0; i < (int)ARRAY_SIZE(pll_tbl); i++) {
	340	if (sr == pll_tbl[i].sr) {
	341	e = &pll_tbl[i];
	342	break;
	343	}
	344	}
	345
	346	if (!e)
	347	return SR_ERR_SAMPLERATE;
	348
	349	sr_dbg("set sample rate: %u.", e->sr);
	350
	351	ret = la_write_reg(usb, 4, e->pll_div_minus_1);
	352	if (ret != SR_OK)
	353	return ret;
	354
	355	ret = la_set_res_reg_bit(usb, 5, 0,
	356	(e->pll_mul_flags & PLL_MUL2) ? 1 : 0); /* bit0 (1=en_mul2) */
	357	if (ret != SR_OK)
	358	return ret;
	359
d57a1143	360	return la_set_res_reg_bit(usb, 5, 7,
8da8c826	361	(e->pll_mul_flags & PLL_MUL1_25) ? 0 : 1); /* bit7 (0=en_mul_1.25) */
8da8c826 VV	362	}
	363
	364	SR_PRIV int sla5032_start_sample(const struct sr_usb_dev_inst *usb)
	365	{
	366	int ret;
	367
	368	ret = la_write_reg(usb, 14, 1);
	369	if (ret != SR_OK)
	370	return ret;
	371
	372	ret = la_set_res_reg_bit(usb, 5, 2, 0);
	373	if (ret != SR_OK)
	374	return ret;
	375
	376	ret = la_set_res_reg_bit(usb, 5, 3, 0);
	377	if (ret != SR_OK)
	378	return ret;
	379
	380	ret = la_set_res_reg_bit(usb, 5, 5, 0);
	381	if (ret != SR_OK)
	382	return ret;
	383
	384	ret = la_set_res_reg_bit(usb, 5, 6, 1);
	385	if (ret != SR_OK)
	386	return ret;
	387
	388	ret = la_set_res_reg_bit(usb, 5, 1, 1);
	389	if (ret != SR_OK)
	390	return ret;
	391
	392	ret = la_set_res_reg_bit(usb, 5, 1, 0);
	393	if (ret != SR_OK)
	394	return ret;
	395
	396	ret = la_set_res_reg_bit(usb, 5, 8, 1);
	397	if (ret != SR_OK)
	398	return ret;
	399
	400	ret = la_set_res_reg_bit(usb, 5, 8, 0);
	401	if (ret != SR_OK)
	402	return ret;
	403
	404	ret = la_set_res_reg_bit(usb, 5, 6, 1);
	405	if (ret != SR_OK)
	406	return ret;
	407
d57a1143	408	return la_set_res_reg_bit(usb, 5, 2, 1);
8da8c826 VV	409	}
	410
	411	SR_PRIV int sla5032_get_status(const struct sr_usb_dev_inst *usb, uint32_t status[3])
	412	{
	413	int ret;
	414	uint32_t v;
	415
	416	ret = la_read_reg(usb, 1, &status[0]);
	417	if (ret != SR_OK)
	418	return ret;
	419
	420	status[1] = 1; /* wait trigger */
	421
	422	ret = la_read_reg(usb, 0, &status[2]);
	423	if (ret != SR_OK)
	424	return ret;
	425
	426	v = 0;
	427	ret = la_read_reg(usb, 2, &v);
	428	if (ret != SR_OK)
	429	return ret;
	430
	431	if (v & 8) {
	432	status[1] = 3; /* sample done */
	433	sr_dbg("get status, reg2: %08X.", v);
	434	} else if (v & 2) {
	435	status[1] = 2; /* triggered */
	436	}
	437
	438	return ret;
	439	}
	440
	441	static int la_read_samples_data(const struct sr_usb_dev_inst usb, void buf,
	442	unsigned int len, int *xfer_len)
	443	{
d57a1143	444	return libusb_bulk_transfer(usb->devhdl, EP_DATA, (uint8_t *)buf, len,
8da8c826	445	xfer_len, USB_DATA_TIMEOUT_MS);
8da8c826 VV	446	}
	447
	448	SR_PRIV int sla5032_read_data_chunk(const struct sr_usb_dev_inst *usb,
	449	void buf, unsigned int len, int xfer_len)
	450	{
	451	int ret;
	452
	453	ret = la_read_samples(usb, 3);
	454	if (ret != SR_OK)
	455	return ret;
	456
	457	ret = la_write_reg(usb, 3, 0x300000);
	458	if (ret != SR_OK)
	459	return ret;
	460
	461	ret = la_set_res_reg_bit(usb, 5, 4, 0);
	462	if (ret != SR_OK)
	463	return ret;
	464
	465	ret = la_set_res_reg_bit(usb, 5, 4, 1);
	466	if (ret != SR_OK)
	467	return ret;
	468
d57a1143	469	return la_read_samples_data(usb, buf, len, xfer_len);
8da8c826 VV	470	}
	471
	472	SR_PRIV int sla5032_set_read_back(const struct sr_usb_dev_inst *usb)
	473	{
	474	int ret;
	475
	476	ret = la_write_reg(usb, 5, 0x08);
	477	if (ret != SR_OK)
	478	return ret;
	479
d57a1143	480	return la_write_reg(usb, 5, 0x28);
8da8c826 VV	481	}
	482
	483	SR_PRIV int sla5032_set_pwm1(const struct sr_usb_dev_inst* usb, uint32_t hi, uint32_t lo)
	484	{
	485	int ret;
	486
	487	ret = la_write_reg(usb, 9, hi);
	488	if (ret != SR_OK)
	489	return ret;
	490
d57a1143	491	return la_write_reg(usb, 10, lo);
8da8c826 VV	492	}
	493
	494	SR_PRIV int sla5032_set_pwm2(const struct sr_usb_dev_inst* usb, uint32_t hi, uint32_t lo)
	495	{
	496	int ret;
	497
	498	ret = la_write_reg(usb, 11, hi);
	499	if (ret != SR_OK)
	500	return ret;
	501
d57a1143	502	return la_write_reg(usb, 12, lo);
8da8c826 VV	503	}
	504
	505	SR_PRIV int sla5032_write_reg14_zero(const struct sr_usb_dev_inst* usb)
	506	{
d57a1143	507	return la_write_reg(usb, 14, 0);
8da8c826 VV	508	}
	509
	510	static int la_cfg_fpga_done(const struct sr_usb_dev_inst *usb, unsigned int addr)
	511	{
	512	uint8_t done_key[8];
	513	uint32_t k0, k1;
	514	unsigned int reg2;
	515	int ret;
	516
	517	memset(done_key, 0, sizeof(done_key));
	518
	519	ret = la_read_mem(usb, addr, sizeof(done_key), done_key); /* read key from eeprom */
	520	if (ret != SR_OK)
	521	return ret;
	522
	523	k0 = RL32(done_key); /* 0x641381F6 */
	524	k1 = RL32(done_key + 4); /* 0x00000000 */
	525
	526	sr_dbg("cfg fpga done, k0: %08X, k1: %08X.", k0, k1);
	527
	528	ret = la_write_reg(usb, 16, k0);
	529	if (ret != SR_OK)
	530	return ret;
	531
	532	ret = la_write_reg(usb, 17, k1);
	533	if (ret != SR_OK)
	534	return ret;
	535
	536	reg2 = 0;
	537	ret = la_read_reg(usb, 2, &reg2);
	538
	539	sr_dbg("cfg fpga done, reg2: %08X.", reg2);
	540
	541	return ret;
	542	}
	543
	544	/*
	545	* Load a bitstream file into memory. Returns a newly allocated array
	546	* consisting of a 32-bit length field followed by the bitstream data.
	547	*/
	548	static unsigned char load_bitstream(struct sr_context ctx,
	549	const char name, int length_p)
	550	{
	551	struct sr_resource fw;
	552	unsigned char stream, fw_data;
	553	ssize_t length, count;
	554
	555	if (sr_resource_open(ctx, &fw, SR_RESOURCE_FIRMWARE, name) != SR_OK)
	556	return NULL;
	557
	558	if (fw.size <= BITSTREAM_HEADER_SIZE \|\| fw.size > BITSTREAM_MAX_SIZE) {
	559	sr_err("Refusing to load bitstream of unreasonable size "
	560	"(%" PRIu64 " bytes).", fw.size);
	561	sr_resource_close(ctx, &fw);
	562	return NULL;
	563	}
	564
	565	stream = g_try_malloc(fw.size);
	566	if (!stream) {
	567	sr_err("Failed to allocate bitstream buffer.");
	568	sr_resource_close(ctx, &fw);
	569	return NULL;
	570	}
	571
572	count = sr_resource_read(ctx, &fw, stream, fw.size);
573	sr_resource_close(ctx, &fw);
574
575	if (count != (ssize_t)fw.size) {
576	sr_err("Failed to read bitstream '%s'.", name);
577	g_free(stream);
578	return NULL;
579	}
580
581	if (RB32(stream + BITSTREAM_HEADER_SIZE) != XILINX_SYNC_WORD) {
582	sr_err("Invalid bitstream signature.");
583	g_free(stream);
584	return NULL;
585	}
586
587	length = fw.size - BITSTREAM_HEADER_SIZE + 0x100;
588	fw_data = g_try_malloc(length);
589	if (!fw_data) {
590	sr_err("Failed to allocate bitstream aligned buffer.");
591	return NULL;
592	}
593
594	memset(fw_data, 0xFF, 0x100);
595	memcpy(fw_data + 0x100, stream + BITSTREAM_HEADER_SIZE,
596	fw.size - BITSTREAM_HEADER_SIZE);
597	g_free(stream);
598
599	*length_p = length;
600
601	return fw_data;
602	}
603
604	static int sla5032_is_configured(const struct sr_usb_dev_inst* usb, gboolean *is_configured)
605	{
606	int ret;
607	uint32_t reg2;
608
609	reg2 = 0;
610	ret = la_read_reg(usb, 2, &reg2);
611	if (ret == SR_OK)
612	*is_configured = (reg2 & 0xFFFFFFF1) == 0xA5A5A5A1 ? TRUE : FALSE;
613
614	return ret;
615	}
616
617	/* Load a Binary File from the firmware directory, transfer it to the device. */
618	static int sla5032_send_bitstream(struct sr_context *ctx,
619	const struct sr_usb_dev_inst usb, const char name)
620	{
621	unsigned char *stream;
622	int ret, length, i, n, m;
623	uint32_t reg2;
624
625	if (!ctx \|\| !usb \|\| !name)
626	return SR_ERR_BUG;
627
628	stream = load_bitstream(ctx, name, &length);
629	if (!stream)
630	return SR_ERR;
631
632	sr_dbg("Downloading FPGA bitstream '%s'.", name);
633
634	reg2 = 0;
635	ret = la_read_reg(usb, 2, &reg2);
636	sr_dbg("send bitstream, reg2: %08X.", reg2);
637
638	/* Transfer the entire bitstream in one URB. */
639	ret = la_write_cmd_buf(usb, CMD_INIT_FW_UPLOAD, 0, 0, NULL); /* init firmware upload */
640	if (ret != SR_OK) {
641	g_free(stream);
642	return ret;
643	}
644
645	n = length / FW_CHUNK_SIZE;
646	m = length % FW_CHUNK_SIZE;
647
648	for (i = 0; i < n; i++) {
649	/* upload firmware chunk */
650	ret = la_write_cmd_buf(usb, CMD_UPLOAD_FW_CHUNK, 0,
651	FW_CHUNK_SIZE, &stream[i * FW_CHUNK_SIZE]);
652
653	if (ret != SR_OK) {
654	g_free(stream);
655	return ret;
656	}
657	}
658
659	if (m != 0) {
660	/* upload firmware last chunk */
661	ret = la_write_cmd_buf(usb, CMD_UPLOAD_FW_CHUNK, 0, m,
662	&stream[n * FW_CHUNK_SIZE]);
663
664	if (ret != SR_OK) {
665	g_free(stream);
666	return ret;
667	}
668	}
669
670	g_free(stream);
671
672	la_cfg_fpga_done(usb, 4000);
673
674	sla5032_write_reg14_zero(usb);
675
676	sr_dbg("FPGA bitstream download of %d bytes done.", length);
677
678	return SR_OK;
679	}
680
681	/* Select and transfer FPGA bitstream for the current configuration. */
682	SR_PRIV int sla5032_apply_fpga_config(const struct sr_dev_inst *sdi)
683	{
684	struct dev_context *devc;
685	struct drv_context *drvc;
686	int ret;
687	gboolean is_configured;
688
689	devc = sdi->priv;
690	drvc = sdi->driver->context;
691
692	if (FPGA_NOCONF != devc->active_fpga_config)
693	return SR_OK; /* No change. */
694
695	is_configured = FALSE;
696	ret = sla5032_is_configured(sdi->conn, &is_configured);
697	if (ret != SR_OK)
698	return ret;
699
700	if (is_configured) {
701	devc->active_fpga_config = FPGA_CONF;
702	return ret;
703	}
704
705	sr_dbg("FPGA not configured, send bitstream.");
706	ret = sla5032_send_bitstream(drvc->sr_ctx, sdi->conn, BITSTREAM_NAME);
707	devc->active_fpga_config = (ret == SR_OK) ? FPGA_CONF : FPGA_NOCONF;
708
709	return ret;
710	}