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sysclk-sla5032: Fix compiler warnings (max vs. MAX).
[libsigrok.git] / src / hardware / sysclk-sla5032 / sla5032.c
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8da8c826
VV		 1/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2019 Vitaliy Vorobyov
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include <config.h>
21#include "sla5032.h"
22#include "protocol.h"
23
24/*
25 * Register description (all registers are 32bit):
26 *
27 * Rx - means register with index x (register address is x*4)
28 *
29 * R0(wr): trigger sel0 (low/high)
30 * R0(rd): n*256 samples (post trigger) captured
31 *
32 * R1(wr): trigger sel1 (level/edge)
33 * R1(rd): current sampled value
34 *
35 * R2(wr): trigger enable mask
36 *
37 * R2(rd): (status register)
38 * b0: 1 - keys entered
39 * b1: 1 - triggered
40 * b3: 1 - capture done
41 *
42 * not configured: B6FF9C97, 12FF9C97, 92FF9C97, 16FF9C97, ...
43 * configured: A5A5A5A0, after enter keys A5A5A5A1
44 *
45 * sel1 (one bit per channel):
46 * 0 - level triggered
47 * 1 - edge triggered
48 *
49 * sel0 (one bit per channel):
50 * 0 - (low level trigger, sel1=0), (falling edge, sel1=1)
51 * 1 - (high level trigger, sel1=0), (raising edge, sel1=1)
52 *
53 * mask (one bit per channel):
54 * 0 - disable trigger on channel n
55 * 1 - enable trigger on channel n
56 *
57 * R3: upload base address or num samples (0x300000)
58 *
59 * R4: pll divisor - 1
60 * 0 - div 1 (no division)
61 * 1 - div 2
62 * 2 - div 3
63 * ...
64 * n-1 - div n
65 *
66 * R5(rd/wr):
67 * b0: 1 - enable pll mul 2, 0 - disable pll mul 2
68 * b1: ??
69 * b2: ??
70 * b3: ??
71 * b4:
72 * b5: ->0->1 upload next data chunk (to pc)
73 * b6: ??
74 * b7: 0 - enable pll mul 1.25, 1 - disable pll mul 1.25
75 * b8: ??
76 *
77 * R6: post trigger depth, value x means (x+1)*256 (samples), min value is 1
78 * R7: pre trigger depth, value y means (y+1)*256 (samples), min value is 1
79 * (x+1)*256 + (y+1)*256 <= 64M
80 *
81 * R9: PWM1 HI (1 width-1)
82 * R10: PWM1 LO (0 width-1)
83 *
84 * R11: PWM2 HI (1 width-1)
85 * R12: PWM2 LO (0 width-1)
86 *
87 * R14:
88 * 1 - start sample?
89 * 0 - upload done?
90 *
91 * R16: rom key 0
92 * R17: rom key 1
93 *
94 * key0 is F6 81 13 64
95 * key1 is 00 00 00 00
96 *
97 * start sample:
98 * r5 <= b2 <= 0
99 * r5 <= b3 <= 0
100 * r5 <= b5 <= 0
101 *
102 * r5 <= b6 <= 1
103 * r5 <= b1 <= 1
104 * r5 <= b1 <= 0
105 *
106 * r5 <= b8 <= 1
107 * r5 <= b8 <= 0
108 *
109 * r5 <= b6 <= 1
110 * r5 <= b2 <= 1
111 *
112 * read back:
113 * r5 <= 0x08 (b3)
114 * r5 <= 0x28 (b5,b3)
115 */
116
117#define BITSTREAM_NAME "sysclk-sla5032.bit"
118#define BITSTREAM_MAX_SIZE (512 * 1024) /* Bitstream size limit for safety */
119#define BITSTREAM_HEADER_SIZE 0x69
120#define FW_CHUNK_SIZE 250
121#define XILINX_SYNC_WORD 0xAA995566
122
123static int la_write_cmd_buf(const struct sr_usb_dev_inst *usb, uint8_t cmd,
124 unsigned int addr, unsigned int len, const void *data)
125{
126 uint8_t *cmd_pkt;
127 int ret, xfer_len;
128 int cmd_len;
129
130 cmd_pkt = g_try_malloc(len + 10);
131 if (!cmd_pkt) {
132 ret = SR_ERR_MALLOC;
133 goto exit;
134 }
135
136 cmd_pkt[0] = cmd;
137 cmd_len = 1;
138 xfer_len = 0;
139
140 switch(cmd) {
141 case CMD_INIT_FW_UPLOAD: /* init firmware upload */
142 break;
143 case CMD_UPLOAD_FW_CHUNK:
144 cmd_pkt[1] = len;
145 cmd_len += 1 + len;
146 memcpy(&cmd_pkt[2], data, len);
147 break;
148 case CMD_READ_REG: /* read register */
149 cmd_pkt[1] = addr;
150 cmd_pkt[2] = len;
151 cmd_len += 2;
152 break;
153 case CMD_WRITE_REG: /* write register */
154 cmd_pkt[1] = addr;
155 cmd_pkt[2] = len;
156 cmd_len += 2 + len;
157 memcpy(&cmd_pkt[3], data, len);
158 break;
159 case CMD_READ_MEM: /* read mem */
160 cmd_pkt[1] = (addr >> 8) & 0xFF;
161 cmd_pkt[2] = addr & 0xFF;
162 cmd_pkt[3] = len;
163 cmd_len += 3;
164 break;
165 case CMD_READ_DATA: /* read samples */
166 cmd_pkt[1] = addr;
167 cmd_len += 1;
168 break;
169 }
170
171 ret = libusb_bulk_transfer(usb->devhdl, EP_COMMAND, cmd_pkt, cmd_len,
172 &xfer_len, USB_CMD_TIMEOUT_MS);
173 if (ret != 0) {
174 sr_dbg("Failed to send command %d: %s.",
175 cmd, libusb_error_name(ret));
176 return SR_ERR;
177 }
178
179 if (xfer_len != cmd_len) {
180 sr_dbg("Invalid send command response of length %d.", xfer_len);
181 return SR_ERR;
182 }
183
184exit:
185 g_free(cmd_pkt);
186 return ret;
187}
188
189static int la_read_reg(const struct sr_usb_dev_inst *usb, unsigned int reg, uint32_t *val)
190{
191 int ret, xfer_len;
192 uint32_t reply;
193
194 ret = la_write_cmd_buf(usb, CMD_READ_REG, reg * sizeof(uint32_t),
195 sizeof(reply), NULL); /* rd reg */
196 if (ret != SR_OK)
197 return ret;
198
199 ret = libusb_bulk_transfer(usb->devhdl, EP_REPLY, (uint8_t *)&reply,
200 sizeof(reply), &xfer_len, USB_REPLY_TIMEOUT_MS);
201 if (ret != SR_OK)
202 return ret;
203
204 if (xfer_len != sizeof(uint32_t)) {
205 sr_dbg("Invalid register read response of length %d.", xfer_len);
206 return SR_ERR;
207 }
208
209 *val = GUINT32_FROM_BE(reply);
210
211 return ret;
212}
213
214static int la_write_reg(const struct sr_usb_dev_inst *usb, unsigned int reg, uint32_t val)
215{
216 int ret;
217 uint32_t val_be;
218
219 val_be = GUINT32_TO_BE(val);
220
221 ret = la_write_cmd_buf(usb, CMD_WRITE_REG, reg * sizeof(uint32_t),
222 sizeof(val_be), &val_be); /* wr reg */
223
224 return ret;
225}
226
227static int la_read_mem(const struct sr_usb_dev_inst *usb, unsigned int addr, unsigned int len, void *data)
228{
229 int ret, xfer_len;
230
231 ret = la_write_cmd_buf(usb, CMD_READ_MEM, addr, len, NULL); /* rd mem */
232 if (ret != SR_OK)
233 return ret;
234
235 xfer_len = 0;
236 ret = libusb_bulk_transfer(usb->devhdl, EP_REPLY, (uint8_t *)data,
237 len, &xfer_len, USB_REPLY_TIMEOUT_MS);
238 if (xfer_len != (int)len) {
239 sr_dbg("Invalid memory read response of length %d.", xfer_len);
240 return SR_ERR;
241 }
242
243 return ret;
244}
245
246static int la_read_samples(const struct sr_usb_dev_inst *usb, unsigned int addr)
247{
248 int ret;
249
250 ret = la_write_cmd_buf(usb, CMD_READ_DATA, addr, 0, NULL); /* rd samples */
251 return ret;
252}
253
254SR_PRIV int sla5032_set_depth(const struct sr_usb_dev_inst *usb, uint32_t pre, uint32_t post)
255{
256 int ret;
257
258 /* (pre + 1)*256 + (post + 1)*256 <= 64*1024*1024 */
259 ret = la_write_reg(usb, 7, pre);
260 if (ret != SR_OK)
261 return ret;
262
263 ret = la_write_reg(usb, 6, post);
264
265 return ret;
266}
267
268SR_PRIV int sla5032_set_triggers(const struct sr_usb_dev_inst *usb,
269 uint32_t trg_value, uint32_t trg_edge_mask, uint32_t trg_mask)
270{
271 int ret;
272
273 sr_dbg("set trigger: val: %08X, e_mask: %08X, mask: %08X.", trg_value,
274 trg_edge_mask, trg_mask);
275
276 ret = la_write_reg(usb, 0, trg_value);
277 if (ret != SR_OK)
278 return ret;
279
280 ret = la_write_reg(usb, 1, trg_edge_mask);
281 if (ret != SR_OK)
282 return ret;
283
284 ret = la_write_reg(usb, 2, trg_mask);
285
286 return ret;
287}
288
289static int la_set_res_reg_bit(const struct sr_usb_dev_inst *usb,
290 unsigned int reg, unsigned int bit, unsigned int set_bit)
291{
292 int ret;
293 uint32_t v;
294
295 v = 0;
296 ret = la_read_reg(usb, reg, &v);
297 if (ret != SR_OK)
298 return ret;
299
300 if (set_bit)
301 v |= (1u << bit);
302 else
303 v &= ~(1u << bit);
304
305 ret = la_write_reg(usb, reg, v);
306
307 return ret;
308}
309
310struct pll_tbl_entry_t
311{
312 unsigned int sr;
313 uint32_t pll_div_minus_1;
314 unsigned int pll_mul_flags;
315};
316
317enum {
318 PLL_MUL2 = 1, /* x2 */
319 PLL_MUL1_25 = 2, /* x1.25 */
320};
321
322static const struct pll_tbl_entry_t pll_tbl[] = {
323 { 500000000, 0, PLL_MUL2 | PLL_MUL1_25 }, /* 500M = f*2*1.25/1 */
324 { 400000000, 0, PLL_MUL2 }, /* 400M = f*2/1 */
325 { 250000000, 0, PLL_MUL1_25 }, /* 250M = f*1.25/1 */
326 { 200000000, 0, 0 }, /* 200M = f/1 */
327 { 100000000, 1, 0 }, /* 100M = f/2 */
328 { 50000000, 3, 0 }, /* 50M = f/4 */
329 { 25000000, 7, 0 }, /* 25M = f/8 */
330 { 20000000, 9, 0 }, /* 20M = f/10 */
331 { 10000000, 19, 0 }, /* 10M = f/20 */
332 { 5000000, 39, 0 }, /* 5M = f/40 */
333 { 2000000, 99, 0 }, /* 2M = f/100 */
334 { 1000000, 199, 0 }, /* 1M = f/200 */
335 { 500000, 399, 0 }, /* 500k = f/400 */
336 { 200000, 999, 0 }, /* 200k = f/1000 */
337 { 100000, 1999, 0 }, /* 100k = f/2000 */
338 { 50000, 3999, 0 }, /* 50k = f/4000 */
339 { 20000, 9999, 0 }, /* 20k = f/10000 */
340 { 10000, 19999, 0 }, /* 10k = f/20000 */
341 { 5000, 39999, 0 }, /* 5k = f/40000 */
342 { 2000, 99999, 0 }, /* 2k = f/100000 */
343};
344
345SR_PRIV int sla5032_set_samplerate(const struct sr_usb_dev_inst *usb, unsigned int sr)
346{
347 int i, ret;
348 const struct pll_tbl_entry_t *e;
349
350 e = NULL;
351 for (i = 0; i < (int)ARRAY_SIZE(pll_tbl); i++) {
352 if (sr == pll_tbl[i].sr) {
353 e = &pll_tbl[i];
354 break;
355 }
356 }
357
358 if (!e)
359 return SR_ERR_SAMPLERATE;
360
361 sr_dbg("set sample rate: %u.", e->sr);
362
363 ret = la_write_reg(usb, 4, e->pll_div_minus_1);
364 if (ret != SR_OK)
365 return ret;
366
367 ret = la_set_res_reg_bit(usb, 5, 0,
368 (e->pll_mul_flags & PLL_MUL2) ? 1 : 0); /* bit0 (1=en_mul2) */
369 if (ret != SR_OK)
370 return ret;
371
372 ret = la_set_res_reg_bit(usb, 5, 7,
373 (e->pll_mul_flags & PLL_MUL1_25) ? 0 : 1); /* bit7 (0=en_mul_1.25) */
374
375 return ret;
376}
377
378SR_PRIV int sla5032_start_sample(const struct sr_usb_dev_inst *usb)
379{
380 int ret;
381
382 ret = la_write_reg(usb, 14, 1);
383 if (ret != SR_OK)
384 return ret;
385
386 ret = la_set_res_reg_bit(usb, 5, 2, 0);
387 if (ret != SR_OK)
388 return ret;
389
390 ret = la_set_res_reg_bit(usb, 5, 3, 0);
391 if (ret != SR_OK)
392 return ret;
393
394 ret = la_set_res_reg_bit(usb, 5, 5, 0);
395 if (ret != SR_OK)
396 return ret;
397
398 ret = la_set_res_reg_bit(usb, 5, 6, 1);
399 if (ret != SR_OK)
400 return ret;
401
402 ret = la_set_res_reg_bit(usb, 5, 1, 1);
403 if (ret != SR_OK)
404 return ret;
405
406 ret = la_set_res_reg_bit(usb, 5, 1, 0);
407 if (ret != SR_OK)
408 return ret;
409
410 ret = la_set_res_reg_bit(usb, 5, 8, 1);
411 if (ret != SR_OK)
412 return ret;
413
414 ret = la_set_res_reg_bit(usb, 5, 8, 0);
415 if (ret != SR_OK)
416 return ret;
417
418 ret = la_set_res_reg_bit(usb, 5, 6, 1);
419 if (ret != SR_OK)
420 return ret;
421
422 ret = la_set_res_reg_bit(usb, 5, 2, 1);
423
424 return ret;
425}
426
427SR_PRIV int sla5032_get_status(const struct sr_usb_dev_inst *usb, uint32_t status[3])
428{
429 int ret;
430 uint32_t v;
431
432 ret = la_read_reg(usb, 1, &status[0]);
433 if (ret != SR_OK)
434 return ret;
435
436 status[1] = 1; /* wait trigger */
437
438 ret = la_read_reg(usb, 0, &status[2]);
439 if (ret != SR_OK)
440 return ret;
441
442 v = 0;
443 ret = la_read_reg(usb, 2, &v);
444 if (ret != SR_OK)
445 return ret;
446
447 if (v & 8) {
448 status[1] = 3; /* sample done */
449 sr_dbg("get status, reg2: %08X.", v);
450 } else if (v & 2) {
451 status[1] = 2; /* triggered */
452 }
453
454 return ret;
455}
456
457static int la_read_samples_data(const struct sr_usb_dev_inst *usb, void *buf,
458 unsigned int len, int *xfer_len)
459{
460 int ret;
461
462 ret = libusb_bulk_transfer(usb->devhdl, EP_DATA, (uint8_t *)buf, len,
463 xfer_len, USB_DATA_TIMEOUT_MS);
464
465 return ret;
466}
467
468SR_PRIV int sla5032_read_data_chunk(const struct sr_usb_dev_inst *usb,
469 void *buf, unsigned int len, int *xfer_len)
470{
471 int ret;
472
473 ret = la_read_samples(usb, 3);
474 if (ret != SR_OK)
475 return ret;
476
477 ret = la_write_reg(usb, 3, 0x300000);
478 if (ret != SR_OK)
479 return ret;
480
481 ret = la_set_res_reg_bit(usb, 5, 4, 0);
482 if (ret != SR_OK)
483 return ret;
484
485 ret = la_set_res_reg_bit(usb, 5, 4, 1);
486 if (ret != SR_OK)
487 return ret;
488
489 ret = la_read_samples_data(usb, buf, len, xfer_len);
490
491 return ret;
492}
493
494SR_PRIV int sla5032_set_read_back(const struct sr_usb_dev_inst *usb)
495{
496 int ret;
497
498 ret = la_write_reg(usb, 5, 0x08);
499 if (ret != SR_OK)
500 return ret;
501
502 ret = la_write_reg(usb, 5, 0x28);
503
504 return ret;
505}
506
507SR_PRIV int sla5032_set_pwm1(const struct sr_usb_dev_inst* usb, uint32_t hi, uint32_t lo)
508{
509 int ret;
510
511 ret = la_write_reg(usb, 9, hi);
512 if (ret != SR_OK)
513 return ret;
514
515 ret = la_write_reg(usb, 10, lo);
516
517 return ret;
518}
519
520SR_PRIV int sla5032_set_pwm2(const struct sr_usb_dev_inst* usb, uint32_t hi, uint32_t lo)
521{
522 int ret;
523
524 ret = la_write_reg(usb, 11, hi);
525 if (ret != SR_OK)
526 return ret;
527
528 ret = la_write_reg(usb, 12, lo);
529
530 return ret;
531}
532
533SR_PRIV int sla5032_write_reg14_zero(const struct sr_usb_dev_inst* usb)
534{
535 int ret;
536
537 ret = la_write_reg(usb, 14, 0);
538
539 return ret;
540}
541
542static int la_cfg_fpga_done(const struct sr_usb_dev_inst *usb, unsigned int addr)
543{
544 uint8_t done_key[8];
545 uint32_t k0, k1;
546 unsigned int reg2;
547 int ret;
548
549 memset(done_key, 0, sizeof(done_key));
550
551 ret = la_read_mem(usb, addr, sizeof(done_key), done_key); /* read key from eeprom */
552 if (ret != SR_OK)
553 return ret;
554
555 k0 = RL32(done_key); /* 0x641381F6 */
556 k1 = RL32(done_key + 4); /* 0x00000000 */
557
558 sr_dbg("cfg fpga done, k0: %08X, k1: %08X.", k0, k1);
559
560 ret = la_write_reg(usb, 16, k0);
561 if (ret != SR_OK)
562 return ret;
563
564 ret = la_write_reg(usb, 17, k1);
565 if (ret != SR_OK)
566 return ret;
567
568 reg2 = 0;
569 ret = la_read_reg(usb, 2, &reg2);
570
571 sr_dbg("cfg fpga done, reg2: %08X.", reg2);
572
573 return ret;
574}
575
576/*
577 * Load a bitstream file into memory. Returns a newly allocated array
578 * consisting of a 32-bit length field followed by the bitstream data.
579 */
580static unsigned char *load_bitstream(struct sr_context *ctx,
581 const char *name, int *length_p)
582{
583 struct sr_resource fw;
584 unsigned char *stream, *fw_data;
585 ssize_t length, count;
586
587 if (sr_resource_open(ctx, &fw, SR_RESOURCE_FIRMWARE, name) != SR_OK)
588 return NULL;
589
590 if (fw.size <= BITSTREAM_HEADER_SIZE || fw.size > BITSTREAM_MAX_SIZE) {
591 sr_err("Refusing to load bitstream of unreasonable size "
592 "(%" PRIu64 " bytes).", fw.size);
593 sr_resource_close(ctx, &fw);
594 return NULL;
595 }
596
597 stream = g_try_malloc(fw.size);
598 if (!stream) {
599 sr_err("Failed to allocate bitstream buffer.");
600 sr_resource_close(ctx, &fw);
601 return NULL;
602 }
603
604 count = sr_resource_read(ctx, &fw, stream, fw.size);
605 sr_resource_close(ctx, &fw);
606
607 if (count != (ssize_t)fw.size) {
608 sr_err("Failed to read bitstream '%s'.", name);
609 g_free(stream);
610 return NULL;
611 }
612
613 if (RB32(stream + BITSTREAM_HEADER_SIZE) != XILINX_SYNC_WORD) {
614 sr_err("Invalid bitstream signature.");
615 g_free(stream);
616 return NULL;
617 }
618
619 length = fw.size - BITSTREAM_HEADER_SIZE + 0x100;
620 fw_data = g_try_malloc(length);
621 if (!fw_data) {
622 sr_err("Failed to allocate bitstream aligned buffer.");
623 return NULL;
624 }
625
626 memset(fw_data, 0xFF, 0x100);
627 memcpy(fw_data + 0x100, stream + BITSTREAM_HEADER_SIZE,
628 fw.size - BITSTREAM_HEADER_SIZE);
629 g_free(stream);
630
631 *length_p = length;
632
633 return fw_data;
634}
635
636static int sla5032_is_configured(const struct sr_usb_dev_inst* usb, gboolean *is_configured)
637{
638 int ret;
639 uint32_t reg2;
640
641 reg2 = 0;
642 ret = la_read_reg(usb, 2, &reg2);
643 if (ret == SR_OK)
644 *is_configured = (reg2 & 0xFFFFFFF1) == 0xA5A5A5A1 ? TRUE : FALSE;
645
646 return ret;
647}
648
649/* Load a Binary File from the firmware directory, transfer it to the device. */
650static int sla5032_send_bitstream(struct sr_context *ctx,
651 const struct sr_usb_dev_inst *usb, const char *name)
652{
653 unsigned char *stream;
654 int ret, length, i, n, m;
655 uint32_t reg2;
656
657 if (!ctx || !usb || !name)
658 return SR_ERR_BUG;
659
660 stream = load_bitstream(ctx, name, &length);
661 if (!stream)
662 return SR_ERR;
663
664 sr_dbg("Downloading FPGA bitstream '%s'.", name);
665
666 reg2 = 0;
667 ret = la_read_reg(usb, 2, &reg2);
668 sr_dbg("send bitstream, reg2: %08X.", reg2);
669
670 /* Transfer the entire bitstream in one URB. */
671 ret = la_write_cmd_buf(usb, CMD_INIT_FW_UPLOAD, 0, 0, NULL); /* init firmware upload */
672 if (ret != SR_OK) {
673 g_free(stream);
674 return ret;
675 }
676
677 n = length / FW_CHUNK_SIZE;
678 m = length % FW_CHUNK_SIZE;
679
680 for (i = 0; i < n; i++) {
681 /* upload firmware chunk */
682 ret = la_write_cmd_buf(usb, CMD_UPLOAD_FW_CHUNK, 0,
683 FW_CHUNK_SIZE, &stream[i * FW_CHUNK_SIZE]);
684
685 if (ret != SR_OK) {
686 g_free(stream);
687 return ret;
688 }
689 }
690
691 if (m != 0) {
692 /* upload firmware last chunk */
693 ret = la_write_cmd_buf(usb, CMD_UPLOAD_FW_CHUNK, 0, m,
694 &stream[n * FW_CHUNK_SIZE]);
695
696 if (ret != SR_OK) {
697 g_free(stream);
698 return ret;
699 }
700 }
701
702 g_free(stream);
703
704 la_cfg_fpga_done(usb, 4000);
705
706 sla5032_write_reg14_zero(usb);
707
708 sr_dbg("FPGA bitstream download of %d bytes done.", length);
709
710 return SR_OK;
711}
712
713/* Select and transfer FPGA bitstream for the current configuration. */
714SR_PRIV int sla5032_apply_fpga_config(const struct sr_dev_inst *sdi)
715{
716 struct dev_context *devc;
717 struct drv_context *drvc;
718 int ret;
719 gboolean is_configured;
720
721 devc = sdi->priv;
722 drvc = sdi->driver->context;
723
724 if (FPGA_NOCONF != devc->active_fpga_config)
725 return SR_OK; /* No change. */
726
727 is_configured = FALSE;
728 ret = sla5032_is_configured(sdi->conn, &is_configured);
729 if (ret != SR_OK)
730 return ret;
731
732 if (is_configured) {
733 devc->active_fpga_config = FPGA_CONF;
734 return ret;
735 }
736
737 sr_dbg("FPGA not configured, send bitstream.");
738 ret = sla5032_send_bitstream(drvc->sr_ctx, sdi->conn, BITSTREAM_NAME);
739 devc->active_fpga_config = (ret == SR_OK) ? FPGA_CONF : FPGA_NOCONF;
740
741 return ret;
742}
Hardware access and backend lib