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be64f90b DE |
1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2015 Daniel Elstner <daniel.kitta@gmail.com> | |
5 | * | |
6 | * This program is free software: you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation, either version 3 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include <config.h> | |
21 | #include "lwla.h" | |
22 | #include "protocol.h" | |
23 | ||
24 | /* Number of logic channels. | |
25 | */ | |
26 | #define NUM_CHANNELS 34 | |
27 | ||
28 | /* Bit mask covering all logic channels. | |
29 | */ | |
30 | #define ALL_CHANNELS_MASK ((UINT64_C(1) << NUM_CHANNELS) - 1) | |
31 | ||
32 | /* Unit size for the sigrok logic datafeed. | |
33 | */ | |
34 | #define UNIT_SIZE ((NUM_CHANNELS + 7) / 8) | |
35 | ||
36 | /* Size of the acquisition buffer in device memory units. | |
37 | */ | |
38 | #define MEMORY_DEPTH (256 * 1024) /* 256k x 36 bit */ | |
39 | ||
40 | /* Capture memory read start address. | |
41 | */ | |
78648577 | 42 | #define READ_START_ADDR 4 |
be64f90b DE |
43 | |
44 | /* Number of device memory units (36 bit) to read at a time. Slices of 8 | |
45 | * consecutive 36-bit words are mapped to 9 32-bit words each, so the chunk | |
46 | * length should be a multiple of 8 to ensure alignment to slice boundaries. | |
47 | * | |
48 | * Experimentation has shown that reading chunks larger than about 1024 bytes | |
49 | * is unreliable. The threshold seems to relate to the buffer size on the FX2 | |
50 | * USB chip: The configured endpoint buffer size is 512, and with double or | |
51 | * triple buffering enabled a multiple of 512 bytes can be kept in fly. | |
52 | * | |
53 | * The vendor software limits reads to 120 words (15 slices, 540 bytes) at | |
54 | * a time. So far, it appears safe to increase this to 224 words (28 slices, | |
55 | * 1008 bytes), thus making the most of two 512 byte buffers. | |
56 | */ | |
78648577 | 57 | #define READ_CHUNK_LEN (28 * 8) |
be64f90b | 58 | |
940805ce DE |
59 | /* Bit mask for the RLE repeat-count-follows flag. |
60 | */ | |
be64f90b DE |
61 | #define RLE_FLAG_LEN_FOLLOWS (UINT64_C(1) << 35) |
62 | ||
940805ce DE |
63 | /* Start index and count for bulk long register reads. |
64 | * The first five long registers do not return useful values when read, | |
65 | * so skip over them to reduce the transfer size of status poll responses. | |
66 | */ | |
67 | #define READ_LREGS_START LREG_MEM_FILL | |
68 | #define READ_LREGS_COUNT (LREG_STATUS + 1 - READ_LREGS_START) | |
69 | ||
be64f90b DE |
70 | /** LWLA1034 register addresses. |
71 | */ | |
72 | enum reg_addr { | |
73 | REG_MEM_CTRL = 0x1074, /* capture buffer control */ | |
74 | REG_MEM_FILL = 0x1078, /* capture buffer fill level */ | |
75 | REG_MEM_START = 0x107C, /* capture buffer start address */ | |
76 | ||
77 | REG_CLK_BOOST = 0x1094, /* logic clock boost flag */ | |
78 | ||
79 | REG_LONG_STROBE = 0x10B0, /* long register read/write strobe */ | |
80 | REG_LONG_ADDR = 0x10B4, /* long register address */ | |
81 | REG_LONG_LOW = 0x10B8, /* long register low word */ | |
82 | REG_LONG_HIGH = 0x10BC, /* long register high word */ | |
83 | }; | |
84 | ||
85 | /** Flag bits for REG_MEM_CTRL. | |
86 | */ | |
87 | enum mem_ctrl_flag { | |
88 | MEM_CTRL_WRITE = 1 << 0, /* "wr1rd0" bit */ | |
89 | MEM_CTRL_CLR_IDX = 1 << 1, /* "clr_idx" bit */ | |
90 | }; | |
91 | ||
92 | /* LWLA1034 long register addresses. | |
93 | */ | |
94 | enum long_reg_addr { | |
95 | LREG_CHAN_MASK = 0, /* channel enable mask */ | |
96 | LREG_DIV_COUNT = 1, /* clock divider max count */ | |
97 | LREG_TRG_VALUE = 2, /* trigger level/slope bits */ | |
98 | LREG_TRG_TYPE = 3, /* trigger type bits (level or edge) */ | |
99 | LREG_TRG_ENABLE = 4, /* trigger enable mask */ | |
100 | LREG_MEM_FILL = 5, /* capture memory fill level or limit */ | |
101 | ||
102 | LREG_DURATION = 7, /* elapsed time in ms (0.8 ms at 125 MS/s) */ | |
103 | LREG_CHAN_STATE = 8, /* current logic levels at the inputs */ | |
104 | LREG_STATUS = 9, /* capture status flags */ | |
105 | ||
106 | LREG_CAP_CTRL = 10, /* capture control bits */ | |
107 | LREG_TEST_ID = 100, /* constant test ID */ | |
108 | }; | |
109 | ||
110 | /** Flag bits for LREG_CAP_CTRL. | |
111 | */ | |
112 | enum cap_ctrl_flag { | |
113 | CAP_CTRL_TRG_EN = 1 << 0, /* "trg_en" bit */ | |
114 | CAP_CTRL_CLR_TIMEBASE = 1 << 2, /* "do_clr_timebase" bit */ | |
115 | CAP_CTRL_FLUSH_FIFO = 1 << 4, /* "flush_fifo" bit */ | |
116 | CAP_CTRL_CLR_FIFOFULL = 1 << 5, /* "clr_fifo32_ful" bit */ | |
117 | CAP_CTRL_CLR_COUNTER = 1 << 6, /* "clr_cntr0" bit */ | |
118 | }; | |
119 | ||
120 | /* Available FPGA configurations. | |
121 | */ | |
122 | enum fpga_config { | |
123 | FPGA_OFF = 0, /* FPGA shutdown config */ | |
124 | FPGA_INT, /* internal clock config */ | |
125 | FPGA_EXTPOS, /* external clock, rising edge config */ | |
126 | FPGA_EXTNEG, /* external clock, falling edge config */ | |
127 | }; | |
128 | ||
129 | /* FPGA bitstream resource filenames. | |
130 | */ | |
131 | static const char bitstream_map[][32] = { | |
132 | [FPGA_OFF] = "sysclk-lwla1034-off.rbf", | |
133 | [FPGA_INT] = "sysclk-lwla1034-int.rbf", | |
134 | [FPGA_EXTPOS] = "sysclk-lwla1034-extpos.rbf", | |
135 | [FPGA_EXTNEG] = "sysclk-lwla1034-extneg.rbf", | |
136 | }; | |
137 | ||
138 | /* Read 64-bit long register. | |
139 | */ | |
140 | static int read_long_reg(const struct sr_usb_dev_inst *usb, | |
141 | uint32_t addr, uint64_t *value) | |
142 | { | |
143 | uint32_t low, high, dummy; | |
144 | int ret; | |
145 | ||
146 | ret = lwla_write_reg(usb, REG_LONG_ADDR, addr); | |
147 | if (ret != SR_OK) | |
148 | return ret; | |
149 | ||
150 | ret = lwla_read_reg(usb, REG_LONG_STROBE, &dummy); | |
151 | if (ret != SR_OK) | |
152 | return ret; | |
153 | ||
154 | ret = lwla_read_reg(usb, REG_LONG_HIGH, &high); | |
155 | if (ret != SR_OK) | |
156 | return ret; | |
157 | ||
158 | ret = lwla_read_reg(usb, REG_LONG_LOW, &low); | |
159 | if (ret != SR_OK) | |
160 | return ret; | |
161 | ||
162 | *value = ((uint64_t)high << 32) | low; | |
163 | ||
164 | return SR_OK; | |
165 | } | |
166 | ||
167 | /* Queue access sequence for a long register write. | |
168 | */ | |
169 | static void queue_long_regval(struct acquisition_state *acq, | |
170 | uint32_t addr, uint64_t value) | |
171 | { | |
172 | lwla_queue_regval(acq, REG_LONG_ADDR, addr); | |
173 | lwla_queue_regval(acq, REG_LONG_LOW, value & 0xFFFFFFFF); | |
174 | lwla_queue_regval(acq, REG_LONG_HIGH, value >> 32); | |
175 | lwla_queue_regval(acq, REG_LONG_STROBE, 0); | |
176 | } | |
177 | ||
178 | /* Helper to fill in the long register bulk write command. | |
179 | */ | |
180 | static inline void bulk_long_set(struct acquisition_state *acq, | |
7ed80817 | 181 | unsigned int idx, uint64_t value) |
be64f90b DE |
182 | { |
183 | acq->xfer_buf_out[4 * idx + 3] = LWLA_WORD_0(value); | |
184 | acq->xfer_buf_out[4 * idx + 4] = LWLA_WORD_1(value); | |
185 | acq->xfer_buf_out[4 * idx + 5] = LWLA_WORD_2(value); | |
186 | acq->xfer_buf_out[4 * idx + 6] = LWLA_WORD_3(value); | |
187 | } | |
188 | ||
189 | /* Helper for dissecting the response to a long register bulk read. | |
190 | */ | |
191 | static inline uint64_t bulk_long_get(const struct acquisition_state *acq, | |
7ed80817 | 192 | unsigned int idx) |
be64f90b DE |
193 | { |
194 | uint64_t low, high; | |
195 | ||
940805ce DE |
196 | low = LWLA_TO_UINT32(acq->xfer_buf_in[2 * (idx - READ_LREGS_START)]); |
197 | high = LWLA_TO_UINT32(acq->xfer_buf_in[2 * (idx - READ_LREGS_START) + 1]); | |
be64f90b DE |
198 | |
199 | return (high << 32) | low; | |
200 | } | |
201 | ||
202 | /* Demangle and decompress incoming sample data from the transfer buffer. | |
203 | * The data chunk is taken from the acquisition state, and is expected to | |
204 | * contain a multiple of 8 packed 36-bit words. | |
205 | */ | |
206 | static void read_response(struct acquisition_state *acq) | |
207 | { | |
208 | uint64_t sample, high_nibbles, word; | |
209 | uint32_t *slice; | |
210 | uint8_t *out_p; | |
7ed80817 DE |
211 | unsigned int words_left; |
212 | unsigned int max_samples, run_samples; | |
213 | unsigned int wi, ri, si; | |
be64f90b DE |
214 | |
215 | /* Number of 36-bit words remaining in the transfer buffer. */ | |
216 | words_left = MIN(acq->mem_addr_next, acq->mem_addr_stop) | |
217 | - acq->mem_addr_done; | |
218 | ||
219 | for (wi = 0;; wi++) { | |
220 | /* Calculate number of samples to write into packet. */ | |
221 | max_samples = MIN(acq->samples_max - acq->samples_done, | |
222 | PACKET_SIZE / UNIT_SIZE - acq->out_index); | |
223 | run_samples = MIN(max_samples, acq->run_len); | |
224 | ||
225 | /* Expand run-length samples into session packet. */ | |
226 | sample = acq->sample; | |
227 | out_p = &acq->out_packet[acq->out_index * UNIT_SIZE]; | |
228 | ||
229 | for (ri = 0; ri < run_samples; ri++) { | |
230 | out_p[0] = sample & 0xFF; | |
231 | out_p[1] = (sample >> 8) & 0xFF; | |
232 | out_p[2] = (sample >> 16) & 0xFF; | |
233 | out_p[3] = (sample >> 24) & 0xFF; | |
234 | out_p[4] = (sample >> 32) & 0xFF; | |
235 | out_p += UNIT_SIZE; | |
236 | } | |
237 | acq->run_len -= run_samples; | |
238 | acq->out_index += run_samples; | |
239 | acq->samples_done += run_samples; | |
240 | ||
241 | if (run_samples == max_samples) | |
242 | break; /* packet full or sample limit reached */ | |
243 | if (wi >= words_left) | |
244 | break; /* done with current transfer */ | |
245 | ||
246 | /* Get the current slice of 8 packed 36-bit words. */ | |
247 | slice = &acq->xfer_buf_in[(acq->in_index + wi) / 8 * 9]; | |
248 | si = (acq->in_index + wi) % 8; /* word index within slice */ | |
249 | ||
250 | /* Extract the next 36-bit word. */ | |
251 | high_nibbles = LWLA_TO_UINT32(slice[8]); | |
252 | word = LWLA_TO_UINT32(slice[si]); | |
253 | word |= (high_nibbles << (4 * si + 4)) & (UINT64_C(0xF) << 32); | |
254 | ||
255 | if (acq->rle == RLE_STATE_DATA) { | |
256 | acq->sample = word & ALL_CHANNELS_MASK; | |
257 | acq->run_len = ((word >> NUM_CHANNELS) & 1) + 1; | |
258 | acq->rle = ((word & RLE_FLAG_LEN_FOLLOWS) != 0) | |
259 | ? RLE_STATE_LEN : RLE_STATE_DATA; | |
260 | } else { | |
261 | acq->run_len += word << 1; | |
262 | acq->rle = RLE_STATE_DATA; | |
263 | } | |
264 | } | |
265 | acq->in_index += wi; | |
266 | acq->mem_addr_done += wi; | |
267 | } | |
268 | ||
78648577 DE |
269 | /* Check whether we can receive responses of more than 64 bytes. |
270 | * The FX2 firmware of the LWLA1034 has a bug in the reset logic which | |
271 | * sometimes causes the response endpoint to be limited to transfers of | |
272 | * 64 bytes at a time, instead of the expected 2*512 bytes. The problem | |
273 | * can be worked around by never requesting more than 64 bytes. | |
274 | * This quirk manifests itself only under certain conditions, and some | |
275 | * users seem to see it more frequently than others. Detect it here in | |
276 | * order to avoid paying the penalty unnecessarily. | |
277 | */ | |
278 | static int detect_short_transfer_quirk(const struct sr_dev_inst *sdi) | |
279 | { | |
280 | struct dev_context *devc; | |
281 | struct sr_usb_dev_inst *usb; | |
282 | int xfer_len; | |
283 | int ret; | |
284 | uint16_t command[3]; | |
285 | unsigned char buf[512]; | |
286 | ||
287 | const int lreg_count = 10; | |
288 | ||
289 | devc = sdi->priv; | |
290 | usb = sdi->conn; | |
291 | ||
292 | command[0] = LWLA_WORD(CMD_READ_LREGS); | |
293 | command[1] = LWLA_WORD(0); | |
294 | command[2] = LWLA_WORD(lreg_count); | |
295 | ||
296 | ret = lwla_send_command(usb, command, ARRAY_SIZE(command)); | |
297 | if (ret != SR_OK) | |
298 | return ret; | |
299 | ||
300 | ret = lwla_receive_reply(usb, buf, sizeof(buf), &xfer_len); | |
301 | if (ret != SR_OK) | |
302 | return ret; | |
303 | ||
304 | devc->short_transfer_quirk = (xfer_len == 64); | |
305 | ||
306 | if (xfer_len == 8 * lreg_count) | |
307 | return SR_OK; | |
308 | ||
309 | if (xfer_len == 64) { | |
310 | /* Drain the tailing portion of the split transfer. */ | |
311 | ret = lwla_receive_reply(usb, buf, sizeof(buf), &xfer_len); | |
312 | if (ret != SR_OK) | |
313 | return ret; | |
314 | ||
315 | if (xfer_len == 8 * lreg_count - 64) | |
316 | return SR_OK; | |
317 | } | |
318 | sr_err("Received response of unexpected length %d.", xfer_len); | |
319 | ||
320 | return SR_ERR; | |
321 | } | |
322 | ||
be64f90b DE |
323 | /* Select and transfer FPGA bitstream for the current configuration. |
324 | */ | |
325 | static int apply_fpga_config(const struct sr_dev_inst *sdi) | |
326 | { | |
327 | struct dev_context *devc; | |
328 | struct drv_context *drvc; | |
329 | int config; | |
330 | int ret; | |
331 | ||
332 | devc = sdi->priv; | |
333 | drvc = sdi->driver->context; | |
334 | ||
335 | if (sdi->status == SR_ST_INACTIVE) | |
336 | config = FPGA_OFF; | |
337 | else if (devc->cfg_clock_source == CLOCK_INTERNAL) | |
338 | config = FPGA_INT; | |
339 | else if (devc->cfg_clock_edge == EDGE_POSITIVE) | |
340 | config = FPGA_EXTPOS; | |
341 | else | |
342 | config = FPGA_EXTNEG; | |
343 | ||
344 | if (config == devc->active_fpga_config) | |
345 | return SR_OK; /* no change */ | |
346 | ||
347 | ret = lwla_send_bitstream(drvc->sr_ctx, sdi->conn, | |
348 | bitstream_map[config]); | |
349 | devc->active_fpga_config = (ret == SR_OK) ? config : FPGA_NOCONF; | |
350 | ||
351 | return ret; | |
352 | } | |
353 | ||
354 | /* Perform initialization self test. | |
355 | */ | |
356 | static int device_init_check(const struct sr_dev_inst *sdi) | |
357 | { | |
358 | uint64_t value; | |
359 | int ret; | |
360 | ||
361 | ret = read_long_reg(sdi->conn, LREG_TEST_ID, &value); | |
362 | if (ret != SR_OK) | |
363 | return ret; | |
364 | ||
365 | /* Ignore the value returned by the first read. */ | |
366 | ret = read_long_reg(sdi->conn, LREG_TEST_ID, &value); | |
367 | if (ret != SR_OK) | |
368 | return ret; | |
369 | ||
370 | if (value != UINT64_C(0x1234567887654321)) { | |
371 | sr_err("Received invalid test word 0x%016" PRIX64 ".", value); | |
372 | return SR_ERR; | |
373 | } | |
78648577 DE |
374 | |
375 | return detect_short_transfer_quirk(sdi); | |
be64f90b DE |
376 | } |
377 | ||
378 | /* Set up the device in preparation for an acquisition session. | |
379 | */ | |
380 | static int setup_acquisition(const struct sr_dev_inst *sdi) | |
381 | { | |
382 | uint64_t divider_count; | |
383 | uint64_t trigger_mask; | |
384 | struct dev_context *devc; | |
385 | struct sr_usb_dev_inst *usb; | |
386 | struct acquisition_state *acq; | |
387 | int ret; | |
388 | ||
389 | devc = sdi->priv; | |
390 | usb = sdi->conn; | |
391 | acq = devc->acquisition; | |
392 | ||
393 | acq->reg_seq_pos = 0; | |
394 | acq->reg_seq_len = 0; | |
395 | ||
396 | lwla_queue_regval(acq, REG_MEM_CTRL, MEM_CTRL_CLR_IDX); | |
397 | lwla_queue_regval(acq, REG_MEM_CTRL, MEM_CTRL_WRITE); | |
398 | ||
399 | queue_long_regval(acq, LREG_CAP_CTRL, | |
400 | CAP_CTRL_CLR_TIMEBASE | CAP_CTRL_FLUSH_FIFO | | |
401 | CAP_CTRL_CLR_FIFOFULL | CAP_CTRL_CLR_COUNTER); | |
402 | ||
403 | lwla_queue_regval(acq, REG_CLK_BOOST, acq->clock_boost); | |
404 | ||
405 | ret = lwla_write_regs(usb, acq->reg_sequence, acq->reg_seq_len); | |
406 | acq->reg_seq_len = 0; | |
407 | ||
408 | if (ret != SR_OK) | |
409 | return ret; | |
410 | ||
411 | acq->xfer_buf_out[0] = LWLA_WORD(CMD_WRITE_LREGS); | |
412 | acq->xfer_buf_out[1] = LWLA_WORD(0); | |
413 | acq->xfer_buf_out[2] = LWLA_WORD(LREG_STATUS + 1); | |
414 | ||
415 | bulk_long_set(acq, LREG_CHAN_MASK, devc->channel_mask); | |
416 | ||
417 | if (devc->samplerate > 0 && devc->samplerate <= SR_MHZ(100) | |
418 | && !acq->clock_boost) | |
419 | divider_count = SR_MHZ(100) / devc->samplerate - 1; | |
420 | else | |
421 | divider_count = 0; | |
422 | ||
423 | bulk_long_set(acq, LREG_DIV_COUNT, divider_count); | |
424 | bulk_long_set(acq, LREG_TRG_VALUE, devc->trigger_values); | |
425 | bulk_long_set(acq, LREG_TRG_TYPE, devc->trigger_edge_mask); | |
426 | ||
427 | trigger_mask = devc->trigger_mask; | |
428 | ||
429 | /* Set bits to select external TRG input edge. */ | |
430 | if (devc->cfg_trigger_source == TRIGGER_EXT_TRG) | |
431 | switch (devc->cfg_trigger_slope) { | |
432 | case EDGE_POSITIVE: | |
433 | trigger_mask |= UINT64_C(1) << 35; | |
434 | break; | |
435 | case EDGE_NEGATIVE: | |
436 | trigger_mask |= UINT64_C(1) << 34; | |
437 | break; | |
438 | } | |
439 | ||
440 | bulk_long_set(acq, LREG_TRG_ENABLE, trigger_mask); | |
441 | ||
442 | /* Set the capture memory full threshold. This is slightly less | |
443 | * than the actual maximum, most likely in order to compensate for | |
444 | * pipeline latency. | |
445 | */ | |
446 | bulk_long_set(acq, LREG_MEM_FILL, MEMORY_DEPTH - 16); | |
447 | ||
448 | /* Fill remaining words with zeroes. */ | |
449 | bulk_long_set(acq, 6, 0); | |
450 | bulk_long_set(acq, LREG_DURATION, 0); | |
451 | bulk_long_set(acq, LREG_CHAN_STATE, 0); | |
452 | bulk_long_set(acq, LREG_STATUS, 0); | |
453 | ||
454 | return lwla_send_command(sdi->conn, acq->xfer_buf_out, | |
455 | 3 + (LREG_STATUS + 1) * 4); | |
456 | } | |
457 | ||
458 | static int prepare_request(const struct sr_dev_inst *sdi) | |
459 | { | |
460 | struct dev_context *devc; | |
461 | struct acquisition_state *acq; | |
78648577 | 462 | unsigned int chunk_len, remaining, count; |
be64f90b DE |
463 | |
464 | devc = sdi->priv; | |
465 | acq = devc->acquisition; | |
466 | ||
467 | acq->xfer_out->length = 0; | |
468 | acq->reg_seq_pos = 0; | |
469 | acq->reg_seq_len = 0; | |
470 | ||
471 | switch (devc->state) { | |
472 | case STATE_START_CAPTURE: | |
473 | queue_long_regval(acq, LREG_CAP_CTRL, CAP_CTRL_TRG_EN); | |
474 | break; | |
475 | case STATE_STOP_CAPTURE: | |
476 | queue_long_regval(acq, LREG_CAP_CTRL, 0); | |
477 | lwla_queue_regval(acq, REG_CLK_BOOST, 0); | |
478 | break; | |
479 | case STATE_READ_PREPARE: | |
480 | lwla_queue_regval(acq, REG_CLK_BOOST, 1); | |
481 | lwla_queue_regval(acq, REG_MEM_CTRL, MEM_CTRL_CLR_IDX); | |
482 | lwla_queue_regval(acq, REG_MEM_START, READ_START_ADDR); | |
483 | break; | |
484 | case STATE_READ_FINISH: | |
485 | lwla_queue_regval(acq, REG_CLK_BOOST, 0); | |
486 | break; | |
487 | case STATE_STATUS_REQUEST: | |
488 | acq->xfer_buf_out[0] = LWLA_WORD(CMD_READ_LREGS); | |
940805ce DE |
489 | acq->xfer_buf_out[1] = LWLA_WORD(READ_LREGS_START); |
490 | acq->xfer_buf_out[2] = LWLA_WORD(READ_LREGS_COUNT); | |
be64f90b DE |
491 | acq->xfer_out->length = 3 * sizeof(acq->xfer_buf_out[0]); |
492 | break; | |
493 | case STATE_LENGTH_REQUEST: | |
494 | lwla_queue_regval(acq, REG_MEM_FILL, 0); | |
495 | break; | |
496 | case STATE_READ_REQUEST: | |
78648577 DE |
497 | /* Limit reads to 8 device words (36 bytes) at a time if the |
498 | * device firmware has the short transfer quirk. */ | |
499 | chunk_len = (devc->short_transfer_quirk) ? 8 : READ_CHUNK_LEN; | |
be64f90b | 500 | /* Always read a multiple of 8 device words. */ |
78648577 DE |
501 | remaining = (acq->mem_addr_stop - acq->mem_addr_next + 7) / 8 * 8; |
502 | count = MIN(chunk_len, remaining); | |
be64f90b DE |
503 | |
504 | acq->xfer_buf_out[0] = LWLA_WORD(CMD_READ_MEM36); | |
505 | acq->xfer_buf_out[1] = LWLA_WORD_0(acq->mem_addr_next); | |
506 | acq->xfer_buf_out[2] = LWLA_WORD_1(acq->mem_addr_next); | |
507 | acq->xfer_buf_out[3] = LWLA_WORD_0(count); | |
508 | acq->xfer_buf_out[4] = LWLA_WORD_1(count); | |
509 | acq->xfer_out->length = 5 * sizeof(acq->xfer_buf_out[0]); | |
510 | ||
511 | acq->mem_addr_next += count; | |
512 | break; | |
513 | default: | |
514 | sr_err("BUG: unhandled request state %d.", devc->state); | |
515 | return SR_ERR_BUG; | |
516 | } | |
517 | ||
518 | return SR_OK; | |
519 | } | |
520 | ||
521 | static int handle_response(const struct sr_dev_inst *sdi) | |
522 | { | |
523 | struct dev_context *devc; | |
524 | struct acquisition_state *acq; | |
525 | int expect_len; | |
526 | ||
527 | devc = sdi->priv; | |
528 | acq = devc->acquisition; | |
529 | ||
530 | switch (devc->state) { | |
531 | case STATE_STATUS_REQUEST: | |
940805ce | 532 | if (acq->xfer_in->actual_length != READ_LREGS_COUNT * 8) { |
be64f90b | 533 | sr_err("Received size %d doesn't match expected size %d.", |
940805ce | 534 | acq->xfer_in->actual_length, READ_LREGS_COUNT * 8); |
be64f90b DE |
535 | return SR_ERR; |
536 | } | |
537 | acq->mem_addr_fill = bulk_long_get(acq, LREG_MEM_FILL) & 0xFFFFFFFF; | |
538 | acq->duration_now = bulk_long_get(acq, LREG_DURATION); | |
539 | /* Shift left by one so the bit positions match the LWLA1016. */ | |
540 | acq->status = (bulk_long_get(acq, LREG_STATUS) & 0x3F) << 1; | |
541 | /* | |
542 | * It seems that the 125 MS/s mode is implemented simply by | |
543 | * running the FPGA logic at a 25% higher clock rate. As a | |
544 | * result, the millisecond counter for the capture duration | |
545 | * is also off by 25%, and thus needs to be corrected here. | |
546 | */ | |
547 | if (acq->clock_boost) | |
548 | acq->duration_now = acq->duration_now * 4 / 5; | |
549 | break; | |
550 | case STATE_LENGTH_REQUEST: | |
551 | acq->mem_addr_next = READ_START_ADDR; | |
552 | acq->mem_addr_stop = acq->reg_sequence[0].val; | |
553 | break; | |
554 | case STATE_READ_REQUEST: | |
555 | /* Expect a multiple of 8 36-bit words packed into 9 32-bit | |
556 | * words. */ | |
557 | expect_len = (acq->mem_addr_next - acq->mem_addr_done | |
558 | + acq->in_index + 7) / 8 * 9 * sizeof(acq->xfer_buf_in[0]); | |
559 | ||
560 | if (acq->xfer_in->actual_length != expect_len) { | |
561 | sr_err("Received size %d does not match expected size %d.", | |
562 | acq->xfer_in->actual_length, expect_len); | |
563 | devc->transfer_error = TRUE; | |
564 | return SR_ERR; | |
565 | } | |
566 | read_response(acq); | |
567 | break; | |
568 | default: | |
569 | sr_err("BUG: unhandled response state %d.", devc->state); | |
570 | return SR_ERR_BUG; | |
571 | } | |
572 | ||
573 | return SR_OK; | |
574 | } | |
575 | ||
576 | /** Model descriptor for the LWLA1034. | |
577 | */ | |
578 | SR_PRIV const struct model_info lwla1034_info = { | |
579 | .name = "LWLA1034", | |
580 | .num_channels = NUM_CHANNELS, | |
581 | ||
582 | .num_devopts = 8, | |
583 | .devopts = { | |
584 | SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, | |
585 | SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, | |
586 | SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
587 | SR_CONF_TRIGGER_MATCH | SR_CONF_LIST, | |
588 | SR_CONF_EXTERNAL_CLOCK | SR_CONF_GET | SR_CONF_SET, | |
589 | SR_CONF_CLOCK_EDGE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
590 | SR_CONF_TRIGGER_SOURCE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
591 | SR_CONF_TRIGGER_SLOPE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
592 | }, | |
593 | .num_samplerates = 20, | |
594 | .samplerates = { | |
595 | SR_MHZ(125), SR_MHZ(100), | |
596 | SR_MHZ(50), SR_MHZ(20), SR_MHZ(10), | |
597 | SR_MHZ(5), SR_MHZ(2), SR_MHZ(1), | |
598 | SR_KHZ(500), SR_KHZ(200), SR_KHZ(100), | |
599 | SR_KHZ(50), SR_KHZ(20), SR_KHZ(10), | |
600 | SR_KHZ(5), SR_KHZ(2), SR_KHZ(1), | |
601 | SR_HZ(500), SR_HZ(200), SR_HZ(100), | |
602 | }, | |
603 | ||
604 | .apply_fpga_config = &apply_fpga_config, | |
605 | .device_init_check = &device_init_check, | |
606 | .setup_acquisition = &setup_acquisition, | |
607 | ||
608 | .prepare_request = &prepare_request, | |
609 | .handle_response = &handle_response, | |
610 | }; |