[libsigrok.git] / src / hardware / sysclk-lwla / lwla1034.c

/*
 * This file is part of the libsigrok project.
 *
 * Copyright (C) 2015 Daniel Elstner <daniel.kitta@gmail.com>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <config.h>
#include "lwla.h"
#include "protocol.h"

/* Number of logic channels.
 */
#define NUM_CHANNELS	34

/* Bit mask covering all logic channels.
 */
#define ALL_CHANNELS_MASK	((UINT64_C(1) << NUM_CHANNELS) - 1)

/* Unit size for the sigrok logic datafeed.
 */
#define UNIT_SIZE	((NUM_CHANNELS + 7) / 8)

/* Size of the acquisition buffer in device memory units.
 */
#define MEMORY_DEPTH	(256 * 1024)	/* 256k x 36 bit */

/* Capture memory read start address.
 */
#define READ_START_ADDR		4

/* Number of device memory units (36 bit) to read at a time. Slices of 8
 * consecutive 36-bit words are mapped to 9 32-bit words each, so the chunk
 * length should be a multiple of 8 to ensure alignment to slice boundaries.
 *
 * Experimentation has shown that reading chunks larger than about 1024 bytes
 * is unreliable. The threshold seems to relate to the buffer size on the FX2
 * USB chip: The configured endpoint buffer size is 512, and with double or
 * triple buffering enabled a multiple of 512 bytes can be kept in fly.
 *
 * The vendor software limits reads to 120 words (15 slices, 540 bytes) at
 * a time. So far, it appears safe to increase this to 224 words (28 slices,
 * 1008 bytes), thus making the most of two 512 byte buffers.
 */
#define READ_CHUNK_LEN36	(28 * 8)

/* Bit mask for the RLE repeat-count-follows flag.
 */
#define RLE_FLAG_LEN_FOLLOWS	(UINT64_C(1) << 35)

/* Start index and count for bulk long register reads.
 * The first five long registers do not return useful values when read,
 * so skip over them to reduce the transfer size of status poll responses.
 */
#define READ_LREGS_START	LREG_MEM_FILL
#define READ_LREGS_COUNT	(LREG_STATUS + 1 - READ_LREGS_START)

/** LWLA1034 register addresses.
 */
enum reg_addr {
	REG_MEM_CTRL	= 0x1074, /* capture buffer control */
	REG_MEM_FILL	= 0x1078, /* capture buffer fill level */
	REG_MEM_START	= 0x107C, /* capture buffer start address */

	REG_CLK_BOOST	= 0x1094, /* logic clock boost flag */

	REG_LONG_STROBE	= 0x10B0, /* long register read/write strobe */
	REG_LONG_ADDR	= 0x10B4, /* long register address */
	REG_LONG_LOW	= 0x10B8, /* long register low word */
	REG_LONG_HIGH	= 0x10BC, /* long register high word */
};

/** Flag bits for REG_MEM_CTRL.
 */
enum mem_ctrl_flag {
	MEM_CTRL_WRITE   = 1 << 0, /* "wr1rd0" bit */
	MEM_CTRL_CLR_IDX = 1 << 1, /* "clr_idx" bit */
};

/* LWLA1034 long register addresses.
 */
enum long_reg_addr {
	LREG_CHAN_MASK	= 0,	/* channel enable mask */
	LREG_DIV_COUNT	= 1,	/* clock divider max count */
	LREG_TRG_VALUE	= 2,	/* trigger level/slope bits */
	LREG_TRG_TYPE	= 3,	/* trigger type bits (level or edge) */
	LREG_TRG_ENABLE	= 4,	/* trigger enable mask */
	LREG_MEM_FILL	= 5,	/* capture memory fill level or limit */

	LREG_DURATION	= 7,	/* elapsed time in ms (0.8 ms at 125 MS/s) */
	LREG_CHAN_STATE	= 8,	/* current logic levels at the inputs */
	LREG_STATUS	= 9,	/* capture status flags */

	LREG_CAP_CTRL	= 10,	/* capture control bits */
	LREG_TEST_ID	= 100,	/* constant test ID */
};

/** Flag bits for LREG_CAP_CTRL.
 */
enum cap_ctrl_flag {
	CAP_CTRL_TRG_EN       = 1 << 0, /* "trg_en" bit */
	CAP_CTRL_CLR_TIMEBASE = 1 << 2, /* "do_clr_timebase" bit */
	CAP_CTRL_FLUSH_FIFO   = 1 << 4, /* "flush_fifo" bit */
	CAP_CTRL_CLR_FIFOFULL = 1 << 5, /* "clr_fifo32_ful" bit */
	CAP_CTRL_CLR_COUNTER  = 1 << 6, /* "clr_cntr0" bit */
};

/* Available FPGA configurations.
 */
enum fpga_config {
	FPGA_OFF = 0,	/* FPGA shutdown config */
	FPGA_INT,	/* internal clock config */
	FPGA_EXTPOS,	/* external clock, rising edge config */
	FPGA_EXTNEG,	/* external clock, falling edge config */
};

/* FPGA bitstream resource filenames.
 */
static const char bitstream_map[][32] = {
	[FPGA_OFF]	= "sysclk-lwla1034-off.rbf",
	[FPGA_INT]	= "sysclk-lwla1034-int.rbf",
	[FPGA_EXTPOS]	= "sysclk-lwla1034-extpos.rbf",
	[FPGA_EXTNEG]	= "sysclk-lwla1034-extneg.rbf",
};

/* Read 64-bit long register.
 */
static int read_long_reg(const struct sr_usb_dev_inst *usb,
			 uint32_t addr, uint64_t *value)
{
	uint32_t low, high, dummy;
	int ret;

	ret = lwla_write_reg(usb, REG_LONG_ADDR, addr);
	if (ret != SR_OK)
		return ret;

	ret = lwla_read_reg(usb, REG_LONG_STROBE, &dummy);
	if (ret != SR_OK)
		return ret;

	ret = lwla_read_reg(usb, REG_LONG_HIGH, &high);
	if (ret != SR_OK)
		return ret;

	ret = lwla_read_reg(usb, REG_LONG_LOW, &low);
	if (ret != SR_OK)
		return ret;

	*value = ((uint64_t)high << 32) | low;

	return SR_OK;
}

/* Queue access sequence for a long register write.
 */
static void queue_long_regval(struct acquisition_state *acq,
			      uint32_t addr, uint64_t value)
{
	lwla_queue_regval(acq, REG_LONG_ADDR, addr);
	lwla_queue_regval(acq, REG_LONG_LOW, value & 0xFFFFFFFF);
	lwla_queue_regval(acq, REG_LONG_HIGH, value >> 32);
	lwla_queue_regval(acq, REG_LONG_STROBE, 0);
}

/* Helper to fill in the long register bulk write command.
 */
static inline void bulk_long_set(struct acquisition_state *acq,
				 unsigned int idx, uint64_t value)
{
	acq->xfer_buf_out[4 * idx + 3] = LWLA_WORD_0(value);
	acq->xfer_buf_out[4 * idx + 4] = LWLA_WORD_1(value);
	acq->xfer_buf_out[4 * idx + 5] = LWLA_WORD_2(value);
	acq->xfer_buf_out[4 * idx + 6] = LWLA_WORD_3(value);
}

/* Helper for dissecting the response to a long register bulk read.
 */
static inline uint64_t bulk_long_get(const struct acquisition_state *acq,
				     unsigned int idx)
{
	uint64_t low, high;

	low  = LWLA_TO_UINT32(acq->xfer_buf_in[2 * (idx - READ_LREGS_START)]);
	high = LWLA_TO_UINT32(acq->xfer_buf_in[2 * (idx - READ_LREGS_START) + 1]);

	return (high << 32) | low;
}

/* Demangle and decompress incoming sample data from the transfer buffer.
 * The data chunk is taken from the acquisition state, and is expected to
 * contain a multiple of 8 packed 36-bit words.
 */
static void read_response(struct acquisition_state *acq)
{
	uint64_t sample, high_nibbles, word;
	uint32_t *slice;
	uint8_t *out_p;
	unsigned int words_left;
	unsigned int max_samples, run_samples;
	unsigned int wi, ri, si;

	/* Number of 36-bit words remaining in the transfer buffer. */
	words_left = MIN(acq->mem_addr_next, acq->mem_addr_stop)
			- acq->mem_addr_done;

	for (wi = 0;; wi++) {
		/* Calculate number of samples to write into packet. */
		max_samples = MIN(acq->samples_max - acq->samples_done,
				  PACKET_SIZE / UNIT_SIZE - acq->out_index);
		run_samples = MIN(max_samples, acq->run_len);

		/* Expand run-length samples into session packet. */
		sample = acq->sample;
		out_p = &acq->out_packet[acq->out_index * UNIT_SIZE];

		for (ri = 0; ri < run_samples; ri++) {
			out_p[0] =  sample        & 0xFF;
			out_p[1] = (sample >>  8) & 0xFF;
			out_p[2] = (sample >> 16) & 0xFF;
			out_p[3] = (sample >> 24) & 0xFF;
			out_p[4] = (sample >> 32) & 0xFF;
			out_p += UNIT_SIZE;
		}
		acq->run_len -= run_samples;
		acq->out_index += run_samples;
		acq->samples_done += run_samples;

		if (run_samples == max_samples)
			break; /* packet full or sample limit reached */
		if (wi >= words_left)
			break; /* done with current transfer */

		/* Get the current slice of 8 packed 36-bit words. */
		slice = &acq->xfer_buf_in[(acq->in_index + wi) / 8 * 9];
		si = (acq->in_index + wi) % 8; /* word index within slice */

		/* Extract the next 36-bit word. */
		high_nibbles = LWLA_TO_UINT32(slice[8]);
		word = LWLA_TO_UINT32(slice[si]);
		word |= (high_nibbles << (4 * si + 4)) & (UINT64_C(0xF) << 32);

		if (acq->rle == RLE_STATE_DATA) {
			acq->sample = word & ALL_CHANNELS_MASK;
			acq->run_len = ((word >> NUM_CHANNELS) & 1) + 1;
			acq->rle = ((word & RLE_FLAG_LEN_FOLLOWS) != 0)
					? RLE_STATE_LEN : RLE_STATE_DATA;
		} else {
			acq->run_len += word << 1;
			acq->rle = RLE_STATE_DATA;
		}
	}
	acq->in_index += wi;
	acq->mem_addr_done += wi;
}

/* Select and transfer FPGA bitstream for the current configuration.
 */
static int apply_fpga_config(const struct sr_dev_inst *sdi)
{
	struct dev_context *devc;
	struct drv_context *drvc;
	int config;
	int ret;

	devc = sdi->priv;
	drvc = sdi->driver->context;

	if (sdi->status == SR_ST_INACTIVE)
		config = FPGA_OFF;
	else if (devc->cfg_clock_source == CLOCK_INTERNAL)
		config = FPGA_INT;
	else if (devc->cfg_clock_edge == EDGE_POSITIVE)
		config = FPGA_EXTPOS;
	else
		config = FPGA_EXTNEG;

	if (config == devc->active_fpga_config)
		return SR_OK; /* no change */

	ret = lwla_send_bitstream(drvc->sr_ctx, sdi->conn,
				  bitstream_map[config]);
	devc->active_fpga_config = (ret == SR_OK) ? config : FPGA_NOCONF;

	return ret;
}

/* Perform initialization self test.
 */
static int device_init_check(const struct sr_dev_inst *sdi)
{
	uint64_t value;
	int ret;

	ret = read_long_reg(sdi->conn, LREG_TEST_ID, &value);
	if (ret != SR_OK)
		return ret;

	/* Ignore the value returned by the first read. */
	ret = read_long_reg(sdi->conn, LREG_TEST_ID, &value);
	if (ret != SR_OK)
		return ret;

	if (value != UINT64_C(0x1234567887654321)) {
		sr_err("Received invalid test word 0x%016" PRIX64 ".", value);
		return SR_ERR;
	}
	return SR_OK;
}

/* Set up the device in preparation for an acquisition session.
 */
static int setup_acquisition(const struct sr_dev_inst *sdi)
{
	uint64_t divider_count;
	uint64_t trigger_mask;
	struct dev_context *devc;
	struct sr_usb_dev_inst *usb;
	struct acquisition_state *acq;
	int ret;

	devc = sdi->priv;
	usb  = sdi->conn;
	acq  = devc->acquisition;

	acq->reg_seq_pos = 0;
	acq->reg_seq_len = 0;

	lwla_queue_regval(acq, REG_MEM_CTRL, MEM_CTRL_CLR_IDX);
	lwla_queue_regval(acq, REG_MEM_CTRL, MEM_CTRL_WRITE);

	queue_long_regval(acq, LREG_CAP_CTRL,
		CAP_CTRL_CLR_TIMEBASE | CAP_CTRL_FLUSH_FIFO |
		CAP_CTRL_CLR_FIFOFULL | CAP_CTRL_CLR_COUNTER);

	lwla_queue_regval(acq, REG_CLK_BOOST, acq->clock_boost);

	ret = lwla_write_regs(usb, acq->reg_sequence, acq->reg_seq_len);
	acq->reg_seq_len = 0;

	if (ret != SR_OK)
		return ret;

	acq->xfer_buf_out[0] = LWLA_WORD(CMD_WRITE_LREGS);
	acq->xfer_buf_out[1] = LWLA_WORD(0);
	acq->xfer_buf_out[2] = LWLA_WORD(LREG_STATUS + 1);

	bulk_long_set(acq, LREG_CHAN_MASK, devc->channel_mask);

	if (devc->samplerate > 0 && devc->samplerate <= SR_MHZ(100)
			&& !acq->clock_boost)
		divider_count = SR_MHZ(100) / devc->samplerate - 1;
	else
		divider_count = 0;

	bulk_long_set(acq, LREG_DIV_COUNT, divider_count);
	bulk_long_set(acq, LREG_TRG_VALUE, devc->trigger_values);
	bulk_long_set(acq, LREG_TRG_TYPE,  devc->trigger_edge_mask);

	trigger_mask = devc->trigger_mask;

	/* Set bits to select external TRG input edge. */
	if (devc->cfg_trigger_source == TRIGGER_EXT_TRG)
		switch (devc->cfg_trigger_slope) {
		case EDGE_POSITIVE:
			trigger_mask |= UINT64_C(1) << 35;
			break;
		case EDGE_NEGATIVE:
			trigger_mask |= UINT64_C(1) << 34;
			break;
		}

	bulk_long_set(acq, LREG_TRG_ENABLE, trigger_mask);

	/* Set the capture memory full threshold. This is slightly less
	 * than the actual maximum, most likely in order to compensate for
	 * pipeline latency.
	 */
	bulk_long_set(acq, LREG_MEM_FILL, MEMORY_DEPTH - 16);

	/* Fill remaining words with zeroes. */
	bulk_long_set(acq, 6, 0);
	bulk_long_set(acq, LREG_DURATION, 0);
	bulk_long_set(acq, LREG_CHAN_STATE, 0);
	bulk_long_set(acq, LREG_STATUS, 0);

	return lwla_send_command(sdi->conn, acq->xfer_buf_out,
				 3 + (LREG_STATUS + 1) * 4);
}

static int prepare_request(const struct sr_dev_inst *sdi)
{
	struct dev_context *devc;
	struct acquisition_state *acq;
	unsigned int count;

	devc = sdi->priv;
	acq  = devc->acquisition;

	acq->xfer_out->length = 0;
	acq->reg_seq_pos = 0;
	acq->reg_seq_len = 0;

	switch (devc->state) {
	case STATE_START_CAPTURE:
		queue_long_regval(acq, LREG_CAP_CTRL, CAP_CTRL_TRG_EN);
		break;
	case STATE_STOP_CAPTURE:
		queue_long_regval(acq, LREG_CAP_CTRL, 0);
		lwla_queue_regval(acq, REG_CLK_BOOST, 0);
		break;
	case STATE_READ_PREPARE:
		lwla_queue_regval(acq, REG_CLK_BOOST, 1);
		lwla_queue_regval(acq, REG_MEM_CTRL, MEM_CTRL_CLR_IDX);
		lwla_queue_regval(acq, REG_MEM_START, READ_START_ADDR);
		break;
	case STATE_READ_FINISH:
		lwla_queue_regval(acq, REG_CLK_BOOST, 0);
		break;
	case STATE_STATUS_REQUEST:
		acq->xfer_buf_out[0] = LWLA_WORD(CMD_READ_LREGS);
		acq->xfer_buf_out[1] = LWLA_WORD(READ_LREGS_START);
		acq->xfer_buf_out[2] = LWLA_WORD(READ_LREGS_COUNT);
		acq->xfer_out->length = 3 * sizeof(acq->xfer_buf_out[0]);
		break;
	case STATE_LENGTH_REQUEST:
		lwla_queue_regval(acq, REG_MEM_FILL, 0);
		break;
	case STATE_READ_REQUEST:
		/* Always read a multiple of 8 device words. */
		count = MIN(READ_CHUNK_LEN36, acq->mem_addr_stop
					- acq->mem_addr_next + 7) / 8 * 8;

		acq->xfer_buf_out[0] = LWLA_WORD(CMD_READ_MEM36);
		acq->xfer_buf_out[1] = LWLA_WORD_0(acq->mem_addr_next);
		acq->xfer_buf_out[2] = LWLA_WORD_1(acq->mem_addr_next);
		acq->xfer_buf_out[3] = LWLA_WORD_0(count);
		acq->xfer_buf_out[4] = LWLA_WORD_1(count);
		acq->xfer_out->length = 5 * sizeof(acq->xfer_buf_out[0]);

		acq->mem_addr_next += count;
		break;
	default:
		sr_err("BUG: unhandled request state %d.", devc->state);
		return SR_ERR_BUG;
	}

	return SR_OK;
}

static int handle_response(const struct sr_dev_inst *sdi)
{
	struct dev_context *devc;
	struct acquisition_state *acq;
	int expect_len;

	devc = sdi->priv;
	acq  = devc->acquisition;

	switch (devc->state) {
	case STATE_STATUS_REQUEST:
		if (acq->xfer_in->actual_length != READ_LREGS_COUNT * 8) {
			sr_err("Received size %d doesn't match expected size %d.",
			       acq->xfer_in->actual_length, READ_LREGS_COUNT * 8);
			return SR_ERR;
		}
		acq->mem_addr_fill = bulk_long_get(acq, LREG_MEM_FILL) & 0xFFFFFFFF;
		acq->duration_now  = bulk_long_get(acq, LREG_DURATION);
		/* Shift left by one so the bit positions match the LWLA1016. */
		acq->status = (bulk_long_get(acq, LREG_STATUS) & 0x3F) << 1;
		/*
		 * It seems that the 125 MS/s mode is implemented simply by
		 * running the FPGA logic at a 25% higher clock rate. As a
		 * result, the millisecond counter for the capture duration
		 * is also off by 25%, and thus needs to be corrected here.
		 */
		if (acq->clock_boost)
			acq->duration_now = acq->duration_now * 4 / 5;
		break;
	case STATE_LENGTH_REQUEST:
		acq->mem_addr_next = READ_START_ADDR;
		acq->mem_addr_stop = acq->reg_sequence[0].val;
		break;
	case STATE_READ_REQUEST:
		/* Expect a multiple of 8 36-bit words packed into 9 32-bit
		 * words. */
		expect_len = (acq->mem_addr_next - acq->mem_addr_done
			+ acq->in_index + 7) / 8 * 9 * sizeof(acq->xfer_buf_in[0]);

		if (acq->xfer_in->actual_length != expect_len) {
			sr_err("Received size %d does not match expected size %d.",
			       acq->xfer_in->actual_length, expect_len);
			devc->transfer_error = TRUE;
			return SR_ERR;
		}
		read_response(acq);
		break;
	default:
		sr_err("BUG: unhandled response state %d.", devc->state);
		return SR_ERR_BUG;
	}

	return SR_OK;
}

/** Model descriptor for the LWLA1034.
 */
SR_PRIV const struct model_info lwla1034_info = {
	.name = "LWLA1034",
	.num_channels = NUM_CHANNELS,

	.num_devopts = 8,
	.devopts = {
		SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
		SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
		SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
		SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
		SR_CONF_EXTERNAL_CLOCK | SR_CONF_GET | SR_CONF_SET,
		SR_CONF_CLOCK_EDGE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
		SR_CONF_TRIGGER_SOURCE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
		SR_CONF_TRIGGER_SLOPE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
	},
	.num_samplerates = 20,
	.samplerates = {
		SR_MHZ(125), SR_MHZ(100),
		SR_MHZ(50),  SR_MHZ(20),  SR_MHZ(10),
		SR_MHZ(5),   SR_MHZ(2),   SR_MHZ(1),
		SR_KHZ(500), SR_KHZ(200), SR_KHZ(100),
		SR_KHZ(50),  SR_KHZ(20),  SR_KHZ(10),
		SR_KHZ(5),   SR_KHZ(2),   SR_KHZ(1),
		SR_HZ(500),  SR_HZ(200),  SR_HZ(100),
	},

	.apply_fpga_config = &apply_fpga_config,
	.device_init_check = &device_init_check,
	.setup_acquisition = &setup_acquisition,

	.prepare_request = &prepare_request,
	.handle_response = &handle_response,
};
Commit	Line	Data
be64f90b DE	1	/*
	2	* This file is part of the libsigrok project.
	3	*
	4	* Copyright (C) 2015 Daniel Elstner <daniel.kitta@gmail.com>
	5	*
	6	* This program is free software: you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation, either version 3 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include <config.h>
	21	#include "lwla.h"
	22	#include "protocol.h"
	23
	24	/* Number of logic channels.
	25	*/
	26	#define NUM_CHANNELS 34
	27
	28	/* Bit mask covering all logic channels.
	29	*/
	30	#define ALL_CHANNELS_MASK ((UINT64_C(1) << NUM_CHANNELS) - 1)
	31
	32	/* Unit size for the sigrok logic datafeed.
	33	*/
	34	#define UNIT_SIZE ((NUM_CHANNELS + 7) / 8)
	35
	36	/* Size of the acquisition buffer in device memory units.
	37	*/
	38	#define MEMORY_DEPTH (256 * 1024) /* 256k x 36 bit */
	39
	40	/* Capture memory read start address.
	41	*/
	42	#define READ_START_ADDR 4
	43
	44	/* Number of device memory units (36 bit) to read at a time. Slices of 8
	45	* consecutive 36-bit words are mapped to 9 32-bit words each, so the chunk
	46	* length should be a multiple of 8 to ensure alignment to slice boundaries.
	47	*
	48	* Experimentation has shown that reading chunks larger than about 1024 bytes
	49	* is unreliable. The threshold seems to relate to the buffer size on the FX2
	50	* USB chip: The configured endpoint buffer size is 512, and with double or
	51	* triple buffering enabled a multiple of 512 bytes can be kept in fly.
	52	*
	53	* The vendor software limits reads to 120 words (15 slices, 540 bytes) at
	54	* a time. So far, it appears safe to increase this to 224 words (28 slices,
	55	* 1008 bytes), thus making the most of two 512 byte buffers.
	56	*/
	57	#define READ_CHUNK_LEN36 (28 * 8)
	58
940805ce DE	59	/* Bit mask for the RLE repeat-count-follows flag.
940805ce DE	60	*/
be64f90b DE	61	#define RLE_FLAG_LEN_FOLLOWS (UINT64_C(1) << 35)
be64f90b DE	62
940805ce DE	63	/* Start index and count for bulk long register reads.
	64	* The first five long registers do not return useful values when read,
	65	* so skip over them to reduce the transfer size of status poll responses.
	66	*/
	67	#define READ_LREGS_START LREG_MEM_FILL
	68	#define READ_LREGS_COUNT (LREG_STATUS + 1 - READ_LREGS_START)
	69
be64f90b DE	70	/** LWLA1034 register addresses.
	71	*/
	72	enum reg_addr {
	73	REG_MEM_CTRL = 0x1074, /* capture buffer control */
	74	REG_MEM_FILL = 0x1078, /* capture buffer fill level */
	75	REG_MEM_START = 0x107C, /* capture buffer start address */
	76
	77	REG_CLK_BOOST = 0x1094, /* logic clock boost flag */
	78
	79	REG_LONG_STROBE = 0x10B0, /* long register read/write strobe */
	80	REG_LONG_ADDR = 0x10B4, /* long register address */
	81	REG_LONG_LOW = 0x10B8, /* long register low word */
	82	REG_LONG_HIGH = 0x10BC, /* long register high word */
	83	};
	84
	85	/** Flag bits for REG_MEM_CTRL.
	86	*/
	87	enum mem_ctrl_flag {
	88	MEM_CTRL_WRITE = 1 << 0, /* "wr1rd0" bit */
	89	MEM_CTRL_CLR_IDX = 1 << 1, /* "clr_idx" bit */
	90	};
	91
	92	/* LWLA1034 long register addresses.
	93	*/
	94	enum long_reg_addr {
	95	LREG_CHAN_MASK = 0, /* channel enable mask */
	96	LREG_DIV_COUNT = 1, /* clock divider max count */
	97	LREG_TRG_VALUE = 2, /* trigger level/slope bits */
	98	LREG_TRG_TYPE = 3, /* trigger type bits (level or edge) */
	99	LREG_TRG_ENABLE = 4, /* trigger enable mask */
	100	LREG_MEM_FILL = 5, /* capture memory fill level or limit */
	101
	102	LREG_DURATION = 7, /* elapsed time in ms (0.8 ms at 125 MS/s) */
	103	LREG_CHAN_STATE = 8, /* current logic levels at the inputs */
	104	LREG_STATUS = 9, /* capture status flags */
	105
	106	LREG_CAP_CTRL = 10, /* capture control bits */
	107	LREG_TEST_ID = 100, /* constant test ID */
	108	};
	109
	110	/** Flag bits for LREG_CAP_CTRL.
	111	*/
	112	enum cap_ctrl_flag {
	113	CAP_CTRL_TRG_EN = 1 << 0, /* "trg_en" bit */
	114	CAP_CTRL_CLR_TIMEBASE = 1 << 2, /* "do_clr_timebase" bit */
	115	CAP_CTRL_FLUSH_FIFO = 1 << 4, /* "flush_fifo" bit */
	116	CAP_CTRL_CLR_FIFOFULL = 1 << 5, /* "clr_fifo32_ful" bit */
	117	CAP_CTRL_CLR_COUNTER = 1 << 6, /* "clr_cntr0" bit */
	118	};
	119
	120	/* Available FPGA configurations.
	121	*/
	122	enum fpga_config {
	123	FPGA_OFF = 0, /* FPGA shutdown config */
	124	FPGA_INT, /* internal clock config */
	125	FPGA_EXTPOS, /* external clock, rising edge config */
	126	FPGA_EXTNEG, /* external clock, falling edge config */
	127	};
	128
	129	/* FPGA bitstream resource filenames.
	130	*/
	131	static const char bitstream_map[][32] = {
	132	[FPGA_OFF] = "sysclk-lwla1034-off.rbf",
	133	[FPGA_INT] = "sysclk-lwla1034-int.rbf",
134	[FPGA_EXTPOS] = "sysclk-lwla1034-extpos.rbf",
135	[FPGA_EXTNEG] = "sysclk-lwla1034-extneg.rbf",
136	};
137
138	/* Read 64-bit long register.
139	*/
140	static int read_long_reg(const struct sr_usb_dev_inst *usb,
141	uint32_t addr, uint64_t *value)
142	{
143	uint32_t low, high, dummy;
144	int ret;
145
146	ret = lwla_write_reg(usb, REG_LONG_ADDR, addr);
147	if (ret != SR_OK)
148	return ret;
149
150	ret = lwla_read_reg(usb, REG_LONG_STROBE, &dummy);
151	if (ret != SR_OK)
152	return ret;
153
154	ret = lwla_read_reg(usb, REG_LONG_HIGH, &high);
155	if (ret != SR_OK)
156	return ret;
157
158	ret = lwla_read_reg(usb, REG_LONG_LOW, &low);
159	if (ret != SR_OK)
160	return ret;
161
162	*value = ((uint64_t)high << 32) \| low;
163
164	return SR_OK;
165	}
166
167	/* Queue access sequence for a long register write.
168	*/
169	static void queue_long_regval(struct acquisition_state *acq,
170	uint32_t addr, uint64_t value)
171	{
172	lwla_queue_regval(acq, REG_LONG_ADDR, addr);
173	lwla_queue_regval(acq, REG_LONG_LOW, value & 0xFFFFFFFF);
174	lwla_queue_regval(acq, REG_LONG_HIGH, value >> 32);
175	lwla_queue_regval(acq, REG_LONG_STROBE, 0);
176	}
177
178	/* Helper to fill in the long register bulk write command.
179	*/
180	static inline void bulk_long_set(struct acquisition_state *acq,
7ed80817	181	unsigned int idx, uint64_t value)
be64f90b DE	182	{
	183	acq->xfer_buf_out[4 * idx + 3] = LWLA_WORD_0(value);
	184	acq->xfer_buf_out[4 * idx + 4] = LWLA_WORD_1(value);
	185	acq->xfer_buf_out[4 * idx + 5] = LWLA_WORD_2(value);
	186	acq->xfer_buf_out[4 * idx + 6] = LWLA_WORD_3(value);
	187	}
	188
	189	/* Helper for dissecting the response to a long register bulk read.
	190	*/
	191	static inline uint64_t bulk_long_get(const struct acquisition_state *acq,
7ed80817	192	unsigned int idx)
be64f90b DE	193	{
	194	uint64_t low, high;
	195
940805ce DE	196	low = LWLA_TO_UINT32(acq->xfer_buf_in[2 * (idx - READ_LREGS_START)]);
940805ce DE	197	high = LWLA_TO_UINT32(acq->xfer_buf_in[2 * (idx - READ_LREGS_START) + 1]);
be64f90b DE	198
	199	return (high << 32) \| low;
	200	}
	201
	202	/* Demangle and decompress incoming sample data from the transfer buffer.
	203	* The data chunk is taken from the acquisition state, and is expected to
	204	* contain a multiple of 8 packed 36-bit words.
	205	*/
	206	static void read_response(struct acquisition_state *acq)
	207	{
	208	uint64_t sample, high_nibbles, word;
	209	uint32_t *slice;
	210	uint8_t *out_p;
7ed80817 DE	211	unsigned int words_left;
	212	unsigned int max_samples, run_samples;
	213	unsigned int wi, ri, si;
be64f90b DE	214
	215	/* Number of 36-bit words remaining in the transfer buffer. */
	216	words_left = MIN(acq->mem_addr_next, acq->mem_addr_stop)
	217	- acq->mem_addr_done;
	218
	219	for (wi = 0;; wi++) {
	220	/* Calculate number of samples to write into packet. */
	221	max_samples = MIN(acq->samples_max - acq->samples_done,
	222	PACKET_SIZE / UNIT_SIZE - acq->out_index);
	223	run_samples = MIN(max_samples, acq->run_len);
	224
	225	/* Expand run-length samples into session packet. */
	226	sample = acq->sample;
	227	out_p = &acq->out_packet[acq->out_index * UNIT_SIZE];
	228
	229	for (ri = 0; ri < run_samples; ri++) {
	230	out_p[0] = sample & 0xFF;
	231	out_p[1] = (sample >> 8) & 0xFF;
	232	out_p[2] = (sample >> 16) & 0xFF;
	233	out_p[3] = (sample >> 24) & 0xFF;
	234	out_p[4] = (sample >> 32) & 0xFF;
	235	out_p += UNIT_SIZE;
	236	}
	237	acq->run_len -= run_samples;
	238	acq->out_index += run_samples;
	239	acq->samples_done += run_samples;
	240
	241	if (run_samples == max_samples)
	242	break; /* packet full or sample limit reached */
	243	if (wi >= words_left)
	244	break; /* done with current transfer */
	245
	246	/* Get the current slice of 8 packed 36-bit words. */
	247	slice = &acq->xfer_buf_in[(acq->in_index + wi) / 8 * 9];
	248	si = (acq->in_index + wi) % 8; /* word index within slice */
	249
	250	/* Extract the next 36-bit word. */
	251	high_nibbles = LWLA_TO_UINT32(slice[8]);
	252	word = LWLA_TO_UINT32(slice[si]);
	253	word \|= (high_nibbles << (4 * si + 4)) & (UINT64_C(0xF) << 32);
	254
	255	if (acq->rle == RLE_STATE_DATA) {
	256	acq->sample = word & ALL_CHANNELS_MASK;
	257	acq->run_len = ((word >> NUM_CHANNELS) & 1) + 1;
	258	acq->rle = ((word & RLE_FLAG_LEN_FOLLOWS) != 0)
	259	? RLE_STATE_LEN : RLE_STATE_DATA;
	260	} else {
	261	acq->run_len += word << 1;
	262	acq->rle = RLE_STATE_DATA;
	263	}
	264	}
	265	acq->in_index += wi;
	266	acq->mem_addr_done += wi;
	267	}
	268
	269	/* Select and transfer FPGA bitstream for the current configuration.
	270	*/
	271	static int apply_fpga_config(const struct sr_dev_inst *sdi)
	272	{
	273	struct dev_context *devc;
	274	struct drv_context *drvc;
	275	int config;
	276	int ret;
	277
278	devc = sdi->priv;
279	drvc = sdi->driver->context;
280
281	if (sdi->status == SR_ST_INACTIVE)
282	config = FPGA_OFF;
283	else if (devc->cfg_clock_source == CLOCK_INTERNAL)
284	config = FPGA_INT;
285	else if (devc->cfg_clock_edge == EDGE_POSITIVE)
286	config = FPGA_EXTPOS;
287	else
288	config = FPGA_EXTNEG;
289
290	if (config == devc->active_fpga_config)
291	return SR_OK; /* no change */
292
293	ret = lwla_send_bitstream(drvc->sr_ctx, sdi->conn,
294	bitstream_map[config]);
295	devc->active_fpga_config = (ret == SR_OK) ? config : FPGA_NOCONF;
296
297	return ret;
298	}
299
300	/* Perform initialization self test.
301	*/
302	static int device_init_check(const struct sr_dev_inst *sdi)
303	{
304	uint64_t value;
305	int ret;
306
307	ret = read_long_reg(sdi->conn, LREG_TEST_ID, &value);
308	if (ret != SR_OK)
309	return ret;
310
311	/* Ignore the value returned by the first read. */
312	ret = read_long_reg(sdi->conn, LREG_TEST_ID, &value);
313	if (ret != SR_OK)
314	return ret;
315
316	if (value != UINT64_C(0x1234567887654321)) {
317	sr_err("Received invalid test word 0x%016" PRIX64 ".", value);
318	return SR_ERR;
319	}
320	return SR_OK;
321	}
322
323	/* Set up the device in preparation for an acquisition session.
324	*/
325	static int setup_acquisition(const struct sr_dev_inst *sdi)
326	{
327	uint64_t divider_count;
328	uint64_t trigger_mask;
329	struct dev_context *devc;
330	struct sr_usb_dev_inst *usb;
331	struct acquisition_state *acq;
332	int ret;
333
334	devc = sdi->priv;
335	usb = sdi->conn;
336	acq = devc->acquisition;
337
338	acq->reg_seq_pos = 0;
339	acq->reg_seq_len = 0;
340
341	lwla_queue_regval(acq, REG_MEM_CTRL, MEM_CTRL_CLR_IDX);
342	lwla_queue_regval(acq, REG_MEM_CTRL, MEM_CTRL_WRITE);
343
344	queue_long_regval(acq, LREG_CAP_CTRL,
345	CAP_CTRL_CLR_TIMEBASE \| CAP_CTRL_FLUSH_FIFO \|
346	CAP_CTRL_CLR_FIFOFULL \| CAP_CTRL_CLR_COUNTER);
347
348	lwla_queue_regval(acq, REG_CLK_BOOST, acq->clock_boost);
349
350	ret = lwla_write_regs(usb, acq->reg_sequence, acq->reg_seq_len);
351	acq->reg_seq_len = 0;
352
353	if (ret != SR_OK)
354	return ret;
355
356	acq->xfer_buf_out[0] = LWLA_WORD(CMD_WRITE_LREGS);
357	acq->xfer_buf_out[1] = LWLA_WORD(0);
358	acq->xfer_buf_out[2] = LWLA_WORD(LREG_STATUS + 1);
359
360	bulk_long_set(acq, LREG_CHAN_MASK, devc->channel_mask);
361
362	if (devc->samplerate > 0 && devc->samplerate <= SR_MHZ(100)
363	&& !acq->clock_boost)
364	divider_count = SR_MHZ(100) / devc->samplerate - 1;
365	else
366	divider_count = 0;
367
368	bulk_long_set(acq, LREG_DIV_COUNT, divider_count);
369	bulk_long_set(acq, LREG_TRG_VALUE, devc->trigger_values);
370	bulk_long_set(acq, LREG_TRG_TYPE, devc->trigger_edge_mask);
371
372	trigger_mask = devc->trigger_mask;
373
374	/* Set bits to select external TRG input edge. */
375	if (devc->cfg_trigger_source == TRIGGER_EXT_TRG)
376	switch (devc->cfg_trigger_slope) {
377	case EDGE_POSITIVE:
378	trigger_mask \|= UINT64_C(1) << 35;
379	break;
380	case EDGE_NEGATIVE:
381	trigger_mask \|= UINT64_C(1) << 34;
382	break;
383	}
384
385	bulk_long_set(acq, LREG_TRG_ENABLE, trigger_mask);
386
387	/* Set the capture memory full threshold. This is slightly less
388	* than the actual maximum, most likely in order to compensate for
389	* pipeline latency.
390	*/
391	bulk_long_set(acq, LREG_MEM_FILL, MEMORY_DEPTH - 16);
392
393	/* Fill remaining words with zeroes. */
394	bulk_long_set(acq, 6, 0);
395	bulk_long_set(acq, LREG_DURATION, 0);
396	bulk_long_set(acq, LREG_CHAN_STATE, 0);
397	bulk_long_set(acq, LREG_STATUS, 0);
398
399	return lwla_send_command(sdi->conn, acq->xfer_buf_out,
400	3 + (LREG_STATUS + 1) * 4);
401	}
402
403	static int prepare_request(const struct sr_dev_inst *sdi)
404	{
405	struct dev_context *devc;
406	struct acquisition_state *acq;
7ed80817	407	unsigned int count;
be64f90b DE	408
	409	devc = sdi->priv;
	410	acq = devc->acquisition;
	411
	412	acq->xfer_out->length = 0;
	413	acq->reg_seq_pos = 0;
	414	acq->reg_seq_len = 0;
	415
	416	switch (devc->state) {
	417	case STATE_START_CAPTURE:
	418	queue_long_regval(acq, LREG_CAP_CTRL, CAP_CTRL_TRG_EN);
	419	break;
	420	case STATE_STOP_CAPTURE:
	421	queue_long_regval(acq, LREG_CAP_CTRL, 0);
	422	lwla_queue_regval(acq, REG_CLK_BOOST, 0);
	423	break;
	424	case STATE_READ_PREPARE:
	425	lwla_queue_regval(acq, REG_CLK_BOOST, 1);
	426	lwla_queue_regval(acq, REG_MEM_CTRL, MEM_CTRL_CLR_IDX);
	427	lwla_queue_regval(acq, REG_MEM_START, READ_START_ADDR);
	428	break;
	429	case STATE_READ_FINISH:
	430	lwla_queue_regval(acq, REG_CLK_BOOST, 0);
	431	break;
	432	case STATE_STATUS_REQUEST:
	433	acq->xfer_buf_out[0] = LWLA_WORD(CMD_READ_LREGS);
940805ce DE	434	acq->xfer_buf_out[1] = LWLA_WORD(READ_LREGS_START);
940805ce DE	435	acq->xfer_buf_out[2] = LWLA_WORD(READ_LREGS_COUNT);
be64f90b DE	436	acq->xfer_out->length = 3 * sizeof(acq->xfer_buf_out[0]);
	437	break;
	438	case STATE_LENGTH_REQUEST:
	439	lwla_queue_regval(acq, REG_MEM_FILL, 0);
	440	break;
	441	case STATE_READ_REQUEST:
	442	/* Always read a multiple of 8 device words. */
	443	count = MIN(READ_CHUNK_LEN36, acq->mem_addr_stop
	444	- acq->mem_addr_next + 7) / 8 * 8;
	445
	446	acq->xfer_buf_out[0] = LWLA_WORD(CMD_READ_MEM36);
	447	acq->xfer_buf_out[1] = LWLA_WORD_0(acq->mem_addr_next);
	448	acq->xfer_buf_out[2] = LWLA_WORD_1(acq->mem_addr_next);
	449	acq->xfer_buf_out[3] = LWLA_WORD_0(count);
	450	acq->xfer_buf_out[4] = LWLA_WORD_1(count);
	451	acq->xfer_out->length = 5 * sizeof(acq->xfer_buf_out[0]);
	452
	453	acq->mem_addr_next += count;
	454	break;
	455	default:
	456	sr_err("BUG: unhandled request state %d.", devc->state);
	457	return SR_ERR_BUG;
	458	}
	459
	460	return SR_OK;
	461	}
	462
	463	static int handle_response(const struct sr_dev_inst *sdi)
	464	{
	465	struct dev_context *devc;
	466	struct acquisition_state *acq;
	467	int expect_len;
	468
	469	devc = sdi->priv;
	470	acq = devc->acquisition;
	471
	472	switch (devc->state) {
	473	case STATE_STATUS_REQUEST:
940805ce	474	if (acq->xfer_in->actual_length != READ_LREGS_COUNT * 8) {
be64f90b	475	sr_err("Received size %d doesn't match expected size %d.",
940805ce	476	acq->xfer_in->actual_length, READ_LREGS_COUNT * 8);
be64f90b DE	477	return SR_ERR;
	478	}
	479	acq->mem_addr_fill = bulk_long_get(acq, LREG_MEM_FILL) & 0xFFFFFFFF;
	480	acq->duration_now = bulk_long_get(acq, LREG_DURATION);
	481	/* Shift left by one so the bit positions match the LWLA1016. */
	482	acq->status = (bulk_long_get(acq, LREG_STATUS) & 0x3F) << 1;
	483	/*
	484	* It seems that the 125 MS/s mode is implemented simply by
	485	* running the FPGA logic at a 25% higher clock rate. As a
	486	* result, the millisecond counter for the capture duration
	487	* is also off by 25%, and thus needs to be corrected here.
	488	*/
	489	if (acq->clock_boost)
	490	acq->duration_now = acq->duration_now * 4 / 5;
	491	break;
	492	case STATE_LENGTH_REQUEST:
	493	acq->mem_addr_next = READ_START_ADDR;
	494	acq->mem_addr_stop = acq->reg_sequence[0].val;
	495	break;
	496	case STATE_READ_REQUEST:
	497	/* Expect a multiple of 8 36-bit words packed into 9 32-bit
	498	* words. */
	499	expect_len = (acq->mem_addr_next - acq->mem_addr_done
	500	+ acq->in_index + 7) / 8 * 9 * sizeof(acq->xfer_buf_in[0]);
	501
	502	if (acq->xfer_in->actual_length != expect_len) {
	503	sr_err("Received size %d does not match expected size %d.",
	504	acq->xfer_in->actual_length, expect_len);
	505	devc->transfer_error = TRUE;
	506	return SR_ERR;
	507	}
	508	read_response(acq);
	509	break;
	510	default:
	511	sr_err("BUG: unhandled response state %d.", devc->state);
	512	return SR_ERR_BUG;
	513	}
	514
	515	return SR_OK;
	516	}
	517
	518	/** Model descriptor for the LWLA1034.
	519	*/
	520	SR_PRIV const struct model_info lwla1034_info = {
	521	.name = "LWLA1034",
	522	.num_channels = NUM_CHANNELS,
	523
	524	.num_devopts = 8,
	525	.devopts = {
	526	SR_CONF_LIMIT_SAMPLES \| SR_CONF_GET \| SR_CONF_SET,
	527	SR_CONF_LIMIT_MSEC \| SR_CONF_GET \| SR_CONF_SET,
	528	SR_CONF_SAMPLERATE \| SR_CONF_GET \| SR_CONF_SET \| SR_CONF_LIST,
	529	SR_CONF_TRIGGER_MATCH \| SR_CONF_LIST,
	530	SR_CONF_EXTERNAL_CLOCK \| SR_CONF_GET \| SR_CONF_SET,
	531	SR_CONF_CLOCK_EDGE \| SR_CONF_GET \| SR_CONF_SET \| SR_CONF_LIST,
	532	SR_CONF_TRIGGER_SOURCE \| SR_CONF_GET \| SR_CONF_SET \| SR_CONF_LIST,
	533	SR_CONF_TRIGGER_SLOPE \| SR_CONF_GET \| SR_CONF_SET \| SR_CONF_LIST,
	534	},
	535	.num_samplerates = 20,
	536	.samplerates = {
	537	SR_MHZ(125), SR_MHZ(100),
	538	SR_MHZ(50), SR_MHZ(20), SR_MHZ(10),
	539	SR_MHZ(5), SR_MHZ(2), SR_MHZ(1),
	540	SR_KHZ(500), SR_KHZ(200), SR_KHZ(100),
541	SR_KHZ(50), SR_KHZ(20), SR_KHZ(10),
542	SR_KHZ(5), SR_KHZ(2), SR_KHZ(1),
543	SR_HZ(500), SR_HZ(200), SR_HZ(100),
544	},
545
546	.apply_fpga_config = &apply_fpga_config,
547	.device_init_check = &device_init_check,
548	.setup_acquisition = &setup_acquisition,
549
550	.prepare_request = &prepare_request,
551	.handle_response = &handle_response,
552	};