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d4eabea8 BV |
1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2014 Bert Vermeulen <bert@biot.com> | |
4ee1e2f3 AG |
5 | * Copyright (C) 2015 Google, Inc. |
6 | * (Written by Alexandru Gagniuc <mrnuke@google.com> for Google, Inc.) | |
d4eabea8 BV |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
6ec6c43b | 22 | #include <config.h> |
22c18b03 | 23 | #include <string.h> |
ba464a12 | 24 | #include <strings.h> |
d4eabea8 BV |
25 | #include "protocol.h" |
26 | ||
27 | #define CH_IDX(x) (1 << x) | |
6ed709fe | 28 | #define FREQ_DC_ONLY {0, 0, 0, 0, 0} |
d4eabea8 | 29 | |
5c9e56c9 AG |
30 | /* Agilent/Keysight N5700A series */ |
31 | static const uint32_t agilent_n5700a_devopts[] = { | |
e91bb0a6 | 32 | SR_CONF_CONTINUOUS, |
5c9e56c9 AG |
33 | }; |
34 | ||
35 | static const uint32_t agilent_n5700a_devopts_cg[] = { | |
36 | SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, | |
37 | SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
38 | SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, | |
da005885 UH |
39 | SR_CONF_VOLTAGE | SR_CONF_GET, |
40 | SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
41 | SR_CONF_CURRENT | SR_CONF_GET, | |
42 | SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
5c9e56c9 AG |
43 | }; |
44 | ||
6cc93128 AG |
45 | static const struct channel_group_spec agilent_n5700a_cg[] = { |
46 | { "1", CH_IDX(0), PPS_OVP | PPS_OCP }, | |
47 | }; | |
48 | ||
8cb5affe | 49 | static const struct channel_spec agilent_n5767a_ch[] = { |
6ed709fe | 50 | { "1", { 0, 60, 0.0072, 3, 4 }, { 0, 25, 0.003, 3, 4 }, { 0, 1500 }, FREQ_DC_ONLY }, |
5c9e56c9 AG |
51 | }; |
52 | ||
6cc93128 | 53 | static const struct channel_spec agilent_n5763a_ch[] = { |
6ed709fe | 54 | { "1", { 0, 12.5, 0.0015, 3, 4 }, { 0, 120, 0.0144, 3, 4 }, { 0, 1500 }, FREQ_DC_ONLY }, |
5c9e56c9 AG |
55 | }; |
56 | ||
57 | /* | |
58 | * TODO: OVER_CURRENT_PROTECTION_ACTIVE status can be determined by the OC bit | |
562a3490 | 59 | * in STAT:QUES:EVEN?, but this is not implemented. |
5c9e56c9 | 60 | */ |
8cb5affe | 61 | static const struct scpi_command agilent_n5700a_cmd[] = { |
5c9e56c9 AG |
62 | { SCPI_CMD_REMOTE, "SYST:COMM:RLST REM" }, |
63 | { SCPI_CMD_LOCAL, "SYST:COMM:RLST LOC" }, | |
64 | { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" }, | |
65 | { SCPI_CMD_GET_MEAS_CURRENT, "MEAS:CURR?" }, | |
66 | { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" }, | |
67 | { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" }, | |
68 | { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" }, | |
69 | { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" }, | |
70 | { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP:STAT?" }, | |
71 | { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" }, | |
72 | { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" }, | |
73 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT?" }, | |
74 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT %.6f" }, | |
75 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":CURR:PROT:STAT?" }, | |
76 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":CURR:PROT:STAT ON?"}, | |
77 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":CURR:PROT:STAT OFF?"}, | |
562a3490 | 78 | /* Current limit (CC mode) and OCP are set using the same command. */ |
5c9e56c9 AG |
79 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR?" }, |
80 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR %.6f" }, | |
91ef511d | 81 | ALL_ZERO |
5c9e56c9 AG |
82 | }; |
83 | ||
4ee1e2f3 AG |
84 | /* Chroma 61600 series AC source */ |
85 | static const uint32_t chroma_61604_devopts[] = { | |
e91bb0a6 | 86 | SR_CONF_CONTINUOUS, |
4ee1e2f3 AG |
87 | }; |
88 | ||
89 | static const uint32_t chroma_61604_devopts_cg[] = { | |
90 | SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, | |
91 | SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, | |
da005885 UH |
92 | SR_CONF_VOLTAGE | SR_CONF_GET, |
93 | SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
6c0c9dd2 AG |
94 | SR_CONF_OUTPUT_FREQUENCY | SR_CONF_GET, |
95 | SR_CONF_OUTPUT_FREQUENCY_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
da005885 UH |
96 | SR_CONF_CURRENT | SR_CONF_GET, |
97 | SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
4ee1e2f3 AG |
98 | }; |
99 | ||
8cb5affe | 100 | static const struct channel_spec chroma_61604_ch[] = { |
6ed709fe | 101 | { "1", { 0, 300, 0.1, 1, 1 }, { 0, 16, 0.1, 2, 2 }, { 0, 2000, 0, 1, 1 }, { 1.0, 1000.0, 0.01 } }, |
4ee1e2f3 AG |
102 | }; |
103 | ||
8cb5affe | 104 | static const struct channel_group_spec chroma_61604_cg[] = { |
4ee1e2f3 AG |
105 | { "1", CH_IDX(0), PPS_OVP | PPS_OCP }, |
106 | }; | |
107 | ||
8cb5affe | 108 | static const struct scpi_command chroma_61604_cmd[] = { |
4ee1e2f3 AG |
109 | { SCPI_CMD_REMOTE, "SYST:REM" }, |
110 | { SCPI_CMD_LOCAL, "SYST:LOC" }, | |
111 | { SCPI_CMD_GET_MEAS_VOLTAGE, ":FETC:VOLT:ACDC?" }, | |
6c0c9dd2 | 112 | { SCPI_CMD_GET_MEAS_FREQUENCY, ":FETC:FREQ?" }, |
4ee1e2f3 AG |
113 | { SCPI_CMD_GET_MEAS_CURRENT, ":FETC:CURR:AC?" }, |
114 | { SCPI_CMD_GET_MEAS_POWER, ":FETC:POW:AC?" }, | |
115 | { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT:AC?" }, | |
116 | { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT:AC %.1f" }, | |
6c0c9dd2 AG |
117 | { SCPI_CMD_GET_FREQUENCY_TARGET, ":SOUR:FREQ?" }, |
118 | { SCPI_CMD_SET_FREQUENCY_TARGET, ":SOUR:FREQ %.2f" }, | |
4ee1e2f3 AG |
119 | { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" }, |
120 | { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" }, | |
121 | { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" }, | |
122 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:LIM:AC?" }, | |
123 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:LIM:AC %.1f" }, | |
562a3490 | 124 | /* This is not a current limit mode. It is overcurrent protection. */ |
4ee1e2f3 AG |
125 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:LIM?" }, |
126 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:LIM %.2f" }, | |
91ef511d | 127 | ALL_ZERO |
4ee1e2f3 AG |
128 | }; |
129 | ||
5281993e | 130 | /* Chroma 62000 series DC source */ |
5281993e | 131 | static const uint32_t chroma_62000_devopts[] = { |
e91bb0a6 | 132 | SR_CONF_CONTINUOUS, |
5281993e AG |
133 | }; |
134 | ||
135 | static const uint32_t chroma_62000_devopts_cg[] = { | |
136 | SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, | |
137 | SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, | |
138 | SR_CONF_VOLTAGE | SR_CONF_GET, | |
139 | SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
140 | SR_CONF_CURRENT | SR_CONF_GET, | |
141 | SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
142 | SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
143 | }; | |
144 | ||
5281993e AG |
145 | static const struct channel_group_spec chroma_62000_cg[] = { |
146 | { "1", CH_IDX(0), PPS_OVP | PPS_OCP }, | |
147 | }; | |
148 | ||
149 | static const struct scpi_command chroma_62000_cmd[] = { | |
150 | { SCPI_CMD_REMOTE, ":CONF:REM ON" }, | |
151 | { SCPI_CMD_LOCAL, ":CONF:REM OFF" }, | |
152 | { SCPI_CMD_BEEPER, ":CONF:BEEP?" }, | |
153 | { SCPI_CMD_BEEPER_ENABLE, ":CONF:BEEP ON" }, | |
154 | { SCPI_CMD_BEEPER_DISABLE, ":CONF:BEEP OFF" }, | |
155 | { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" }, | |
156 | { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" }, | |
157 | { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POW?" }, | |
158 | { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" }, | |
159 | { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.2f" }, | |
160 | { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" }, | |
161 | { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" }, | |
162 | { SCPI_CMD_GET_OUTPUT_ENABLED, ":CONF:OUTP?" }, | |
163 | { SCPI_CMD_SET_OUTPUT_ENABLE, ":CONF:OUTP ON" }, | |
164 | { SCPI_CMD_SET_OUTPUT_DISABLE, ":CONF:OUTP OFF" }, | |
165 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:HIGH?" }, | |
166 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:HIGH %.6f" }, | |
167 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:PROT:HIGH?" }, | |
168 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:PROT:HIGH %.6f" }, | |
91ef511d | 169 | ALL_ZERO |
5281993e AG |
170 | }; |
171 | ||
9a5185c7 AG |
172 | static int chroma_62000p_probe_channels(struct sr_dev_inst *sdi, |
173 | struct sr_scpi_hw_info *hw_info, | |
174 | struct channel_spec **channels, unsigned int *num_channels, | |
175 | struct channel_group_spec **channel_groups, | |
176 | unsigned int *num_channel_groups) | |
177 | { | |
6ed709fe | 178 | unsigned int volts, amps, watts; |
9a5185c7 AG |
179 | struct channel_spec *channel; |
180 | ||
181 | (void)sdi; | |
182 | ||
6ed709fe AJ |
183 | sscanf(hw_info->model, "620%uP-%u-%u", &watts, &volts, &s); |
184 | watts *= 100; | |
185 | sr_dbg("Found device rated for %d V, %d A and %d W", volts, amps, watts); | |
9a5185c7 AG |
186 | |
187 | if (volts > 600) { | |
188 | sr_err("Probed max voltage of %u V is out of spec.", volts); | |
189 | return SR_ERR_BUG; | |
190 | } | |
191 | ||
6ed709fe | 192 | if (amps > 120) { |
9a5185c7 AG |
193 | sr_err("Probed max current of %u A is out of spec.", amps); |
194 | return SR_ERR_BUG; | |
195 | } | |
196 | ||
6ed709fe AJ |
197 | if (watts > 5000) { |
198 | sr_err("Probed max power of %u W is out of spec.", watts); | |
199 | return SR_ERR_BUG; | |
200 | } | |
201 | ||
9a5185c7 AG |
202 | channel = g_malloc0(sizeof(struct channel_spec)); |
203 | channel->name = "1"; | |
6ed709fe | 204 | channel->voltage[0] = channel->current[0] = channel->power[0] = 0.0; |
bcee1299 UH |
205 | channel->voltage[1] = volts; |
206 | channel->current[1] = amps; | |
207 | channel->power[1] = watts; | |
9a5185c7 | 208 | channel->voltage[2] = channel->current[2] = 0.01; |
6ed709fe AJ |
209 | channel->voltage[3] = channel->voltage[4] = 3; |
210 | channel->current[3] = channel->current[4] = 4; | |
9a5185c7 AG |
211 | *channels = channel; |
212 | *num_channels = 1; | |
213 | ||
214 | *channel_groups = g_malloc(sizeof(struct channel_group_spec)); | |
215 | **channel_groups = chroma_62000_cg[0]; | |
216 | *num_channel_groups = 1; | |
217 | ||
218 | return SR_OK; | |
219 | } | |
220 | ||
319fe9ce UH |
221 | /* Rigol DP700 series */ |
222 | static const uint32_t rigol_dp700_devopts[] = { | |
223 | SR_CONF_CONTINUOUS, | |
224 | }; | |
225 | ||
226 | static const uint32_t rigol_dp700_devopts_cg[] = { | |
227 | SR_CONF_REGULATION | SR_CONF_GET, | |
228 | SR_CONF_OVER_VOLTAGE_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
229 | SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET, | |
230 | SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, | |
231 | SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
232 | SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET, | |
233 | SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, | |
234 | SR_CONF_VOLTAGE | SR_CONF_GET, | |
235 | SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
236 | SR_CONF_CURRENT | SR_CONF_GET, | |
237 | SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
238 | SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
239 | }; | |
240 | ||
241 | static const struct channel_spec rigol_dp711_ch[] = { | |
242 | { "1", { 0, 30, 0.01, 3, 3 }, { 0, 5, 0.01, 3, 3 }, { 0, 150, 0, 3, 3 }, FREQ_DC_ONLY }, | |
243 | }; | |
244 | ||
245 | static const struct channel_spec rigol_dp712_ch[] = { | |
246 | { "1", { 0, 50, 0.01, 3, 3 }, { 0, 3, 0.01, 3, 3 }, { 0, 150, 0, 3, 3 }, FREQ_DC_ONLY }, | |
247 | }; | |
248 | ||
249 | static const struct channel_group_spec rigol_dp700_cg[] = { | |
250 | { "1", CH_IDX(0), PPS_OVP | PPS_OCP }, | |
251 | }; | |
252 | ||
253 | /* Same as the DP800 series, except for the missing :SYST:OTP* commands. */ | |
254 | static const struct scpi_command rigol_dp700_cmd[] = { | |
255 | { SCPI_CMD_REMOTE, "SYST:REMOTE" }, | |
256 | { SCPI_CMD_LOCAL, "SYST:LOCAL" }, | |
257 | { SCPI_CMD_BEEPER, "SYST:BEEP:STAT?" }, | |
258 | { SCPI_CMD_BEEPER_ENABLE, "SYST:BEEP:STAT ON" }, | |
259 | { SCPI_CMD_BEEPER_DISABLE, "SYST:BEEP:STAT OFF" }, | |
260 | { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" }, | |
261 | { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" }, | |
262 | { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" }, | |
263 | { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POWE?" }, | |
264 | { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" }, | |
265 | { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" }, | |
266 | { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" }, | |
267 | { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" }, | |
268 | { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" }, | |
269 | { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" }, | |
270 | { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" }, | |
271 | { SCPI_CMD_GET_OUTPUT_REGULATION, ":OUTP:MODE?" }, | |
272 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ENABLED, ":OUTP:OVP?" }, | |
273 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_ENABLE, ":OUTP:OVP ON" }, | |
274 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_DISABLE, ":OUTP:OVP OFF" }, | |
275 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, ":OUTP:OVP:QUES?" }, | |
276 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL?" }, | |
277 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL %.6f" }, | |
278 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":OUTP:OCP?" }, | |
279 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":OUTP:OCP:STAT ON" }, | |
280 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":OUTP:OCP:STAT OFF" }, | |
281 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, ":OUTP:OCP:QUES?" }, | |
282 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL?" }, | |
283 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL %.6f" }, | |
284 | ALL_ZERO | |
285 | }; | |
286 | ||
d4eabea8 | 287 | /* Rigol DP800 series */ |
584560f1 | 288 | static const uint32_t rigol_dp800_devopts[] = { |
e91bb0a6 | 289 | SR_CONF_CONTINUOUS, |
5827f61b | 290 | SR_CONF_OVER_TEMPERATURE_PROTECTION | SR_CONF_GET | SR_CONF_SET, |
d4eabea8 BV |
291 | }; |
292 | ||
584560f1 | 293 | static const uint32_t rigol_dp800_devopts_cg[] = { |
7a0b98b5 | 294 | SR_CONF_REGULATION | SR_CONF_GET, |
5827f61b BV |
295 | SR_CONF_OVER_VOLTAGE_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET, |
296 | SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET, | |
297 | SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, | |
298 | SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
299 | SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET, | |
300 | SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, | |
7a0b98b5 AJ |
301 | SR_CONF_VOLTAGE | SR_CONF_GET, |
302 | SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
303 | SR_CONF_CURRENT | SR_CONF_GET, | |
304 | SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
305 | SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
d4eabea8 BV |
306 | }; |
307 | ||
8cb5affe | 308 | static const struct channel_spec rigol_dp821a_ch[] = { |
6ed709fe AJ |
309 | { "1", { 0, 60, 0.001, 3, 3 }, { 0, 1, 0.0001, 4, 4 }, { 0, 60, 0, 3, 4 }, FREQ_DC_ONLY }, |
310 | { "2", { 0, 8, 0.001, 3, 3 }, { 0, 10, 0.001, 3, 3 }, { 0, 80, 0, 3, 3 }, FREQ_DC_ONLY }, | |
cfcdf576 ML |
311 | }; |
312 | ||
8cb5affe | 313 | static const struct channel_spec rigol_dp831_ch[] = { |
6ed709fe AJ |
314 | { "1", { 0, 8, 0.001, 3, 4 }, { 0, 5, 0.0003, 3, 4 }, { 0, 40, 0, 3, 4 }, FREQ_DC_ONLY }, |
315 | { "2", { 0, 30, 0.001, 3, 4 }, { 0, 2, 0.0001, 3, 4 }, { 0, 60, 0, 3, 4 }, FREQ_DC_ONLY }, | |
316 | { "3", { 0, -30, 0.001, 3, 4 }, { 0, 2, 0.0001, 3, 4 }, { 0, 60, 0, 3, 4 }, FREQ_DC_ONLY }, | |
d4eabea8 BV |
317 | }; |
318 | ||
8cb5affe | 319 | static const struct channel_spec rigol_dp832_ch[] = { |
6ed709fe AJ |
320 | { "1", { 0, 30, 0.001, 3, 4 }, { 0, 3, 0.001, 3, 4 }, { 0, 90, 0, 3, 4 }, FREQ_DC_ONLY }, |
321 | { "2", { 0, 30, 0.001, 3, 4 }, { 0, 3, 0.001, 3, 4 }, { 0, 90, 0, 3, 4 }, FREQ_DC_ONLY }, | |
322 | { "3", { 0, 5, 0.001, 3, 4 }, { 0, 3, 0.001, 3, 4 }, { 0, 90, 0, 3, 4 }, FREQ_DC_ONLY }, | |
3222ee10 BV |
323 | }; |
324 | ||
8cb5affe | 325 | static const struct channel_group_spec rigol_dp820_cg[] = { |
cfcdf576 ML |
326 | { "1", CH_IDX(0), PPS_OVP | PPS_OCP }, |
327 | { "2", CH_IDX(1), PPS_OVP | PPS_OCP }, | |
328 | }; | |
329 | ||
8cb5affe | 330 | static const struct channel_group_spec rigol_dp830_cg[] = { |
d4eabea8 BV |
331 | { "1", CH_IDX(0), PPS_OVP | PPS_OCP }, |
332 | { "2", CH_IDX(1), PPS_OVP | PPS_OCP }, | |
333 | { "3", CH_IDX(2), PPS_OVP | PPS_OCP }, | |
334 | }; | |
335 | ||
8cb5affe | 336 | static const struct scpi_command rigol_dp800_cmd[] = { |
60475cd7 BV |
337 | { SCPI_CMD_REMOTE, "SYST:REMOTE" }, |
338 | { SCPI_CMD_LOCAL, "SYST:LOCAL" }, | |
ee2860ee BV |
339 | { SCPI_CMD_BEEPER, "SYST:BEEP:STAT?" }, |
340 | { SCPI_CMD_BEEPER_ENABLE, "SYST:BEEP:STAT ON" }, | |
341 | { SCPI_CMD_BEEPER_DISABLE, "SYST:BEEP:STAT OFF" }, | |
60475cd7 BV |
342 | { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" }, |
343 | { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" }, | |
344 | { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" }, | |
345 | { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POWE?" }, | |
346 | { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" }, | |
347 | { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" }, | |
348 | { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" }, | |
349 | { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" }, | |
350 | { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" }, | |
351 | { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" }, | |
352 | { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" }, | |
353 | { SCPI_CMD_GET_OUTPUT_REGULATION, ":OUTP:MODE?" }, | |
d4eabea8 | 354 | { SCPI_CMD_GET_OVER_TEMPERATURE_PROTECTION, ":SYST:OTP?" }, |
53a81803 BV |
355 | { SCPI_CMD_SET_OVER_TEMPERATURE_PROTECTION_ENABLE, ":SYST:OTP ON" }, |
356 | { SCPI_CMD_SET_OVER_TEMPERATURE_PROTECTION_DISABLE, ":SYST:OTP OFF" }, | |
60475cd7 BV |
357 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ENABLED, ":OUTP:OVP?" }, |
358 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_ENABLE, ":OUTP:OVP ON" }, | |
359 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_DISABLE, ":OUTP:OVP OFF" }, | |
360 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, ":OUTP:OVP:QUES?" }, | |
361 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL?" }, | |
362 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL %.6f" }, | |
363 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":OUTP:OCP?" }, | |
364 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":OUTP:OCP:STAT ON" }, | |
365 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":OUTP:OCP:STAT OFF" }, | |
366 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, ":OUTP:OCP:QUES?" }, | |
367 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL?" }, | |
368 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL %.6f" }, | |
91ef511d | 369 | ALL_ZERO |
d4eabea8 BV |
370 | }; |
371 | ||
bfc86799 | 372 | /* HP 663xx series */ |
e76a3575 AG |
373 | static const uint32_t hp_6630a_devopts[] = { |
374 | SR_CONF_CONTINUOUS, | |
7c517d02 FS |
375 | }; |
376 | ||
377 | static const uint32_t hp_6630a_devopts_cg[] = { | |
e76a3575 AG |
378 | SR_CONF_ENABLED | SR_CONF_SET, |
379 | SR_CONF_VOLTAGE | SR_CONF_GET, | |
380 | SR_CONF_CURRENT | SR_CONF_GET, | |
381 | SR_CONF_VOLTAGE_TARGET | SR_CONF_SET | SR_CONF_LIST, | |
382 | SR_CONF_CURRENT_LIMIT | SR_CONF_SET | SR_CONF_LIST, | |
383 | SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_SET, | |
384 | SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_SET, | |
385 | }; | |
386 | ||
584560f1 | 387 | static const uint32_t hp_6632b_devopts[] = { |
e91bb0a6 | 388 | SR_CONF_CONTINUOUS, |
7c517d02 FS |
389 | }; |
390 | ||
391 | static const uint32_t hp_6632b_devopts_cg[] = { | |
7a0b98b5 AJ |
392 | SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET, |
393 | SR_CONF_VOLTAGE | SR_CONF_GET, | |
394 | SR_CONF_CURRENT | SR_CONF_GET, | |
395 | SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
396 | SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
bc4a2a46 BV |
397 | }; |
398 | ||
e76a3575 | 399 | static const struct channel_spec hp_6633a_ch[] = { |
6ed709fe | 400 | { "1", { 0, 51.188, 0.0125, 3, 4 }, { 0, 2.0475, 0.0005, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY }, |
e76a3575 AG |
401 | }; |
402 | ||
8cb5affe | 403 | static const struct channel_spec hp_6632b_ch[] = { |
6ed709fe | 404 | { "1", { 0, 20.475, 0.005, 3, 4 }, { 0, 5.1188, 0.00132, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY }, |
bc4a2a46 BV |
405 | }; |
406 | ||
e76a3575 | 407 | static const struct channel_group_spec hp_663xx_cg[] = { |
bc4a2a46 BV |
408 | { "1", CH_IDX(0), 0 }, |
409 | }; | |
410 | ||
e76a3575 AG |
411 | static const struct scpi_command hp_6630a_cmd[] = { |
412 | { SCPI_CMD_SET_OUTPUT_ENABLE, "OUT 1" }, | |
413 | { SCPI_CMD_SET_OUTPUT_DISABLE, "OUT 0" }, | |
414 | { SCPI_CMD_GET_MEAS_VOLTAGE, "VOUT?" }, | |
415 | { SCPI_CMD_GET_MEAS_CURRENT, "IOUT?" }, | |
416 | { SCPI_CMD_SET_VOLTAGE_TARGET, "VSET %.4f" }, | |
417 | { SCPI_CMD_SET_CURRENT_LIMIT, "ISET %.4f" }, | |
418 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, "OCP 1" }, | |
419 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, "OCP 0" }, | |
420 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "OVSET %.4f" }, | |
421 | ALL_ZERO | |
422 | }; | |
423 | ||
8cb5affe | 424 | static const struct scpi_command hp_6632b_cmd[] = { |
bc4a2a46 | 425 | { SCPI_CMD_GET_OUTPUT_ENABLED, "OUTP:STAT?" }, |
53a81803 BV |
426 | { SCPI_CMD_SET_OUTPUT_ENABLE, "OUTP:STAT ON" }, |
427 | { SCPI_CMD_SET_OUTPUT_DISABLE, "OUTP:STAT OFF" }, | |
bc4a2a46 BV |
428 | { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" }, |
429 | { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" }, | |
ca95e90f BV |
430 | { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" }, |
431 | { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" }, | |
432 | { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" }, | |
433 | { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" }, | |
91ef511d | 434 | ALL_ZERO |
bc4a2a46 BV |
435 | }; |
436 | ||
c3eadb07 | 437 | /* Philips/Fluke PM2800 series */ |
9d9cf1c4 | 438 | static const uint32_t philips_pm2800_devopts[] = { |
e91bb0a6 | 439 | SR_CONF_CONTINUOUS, |
9d9cf1c4 BV |
440 | }; |
441 | ||
c3eadb07 | 442 | static const uint32_t philips_pm2800_devopts_cg[] = { |
7a0b98b5 AJ |
443 | SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET, |
444 | SR_CONF_VOLTAGE | SR_CONF_GET, | |
445 | SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
446 | SR_CONF_CURRENT | SR_CONF_GET, | |
447 | SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
c3eadb07 BV |
448 | SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET, |
449 | SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, | |
450 | SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
451 | SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET, | |
7a0b98b5 | 452 | SR_CONF_REGULATION | SR_CONF_GET, |
c3eadb07 BV |
453 | }; |
454 | ||
455 | enum philips_pm2800_modules { | |
456 | PM2800_MOD_30V_10A = 1, | |
457 | PM2800_MOD_60V_5A, | |
458 | PM2800_MOD_60V_10A, | |
459 | PM2800_MOD_8V_15A, | |
460 | PM2800_MOD_60V_2A, | |
461 | PM2800_MOD_120V_1A, | |
462 | }; | |
463 | ||
329733d9 | 464 | static const struct philips_pm2800_module_spec { |
c3eadb07 | 465 | /* Min, max, programming resolution. */ |
bcee1299 UH |
466 | double voltage[5]; |
467 | double current[5]; | |
468 | double power[5]; | |
c3eadb07 BV |
469 | } philips_pm2800_module_specs[] = { |
470 | /* Autoranging modules. */ | |
6ed709fe AJ |
471 | [PM2800_MOD_30V_10A] = { { 0, 30, 0.0075, 2, 4 }, { 0, 10, 0.0025, 2, 4 }, { 0, 60 } }, |
472 | [PM2800_MOD_60V_5A] = { { 0, 60, 0.015, 2, 3 }, { 0, 5, 0.00125, 2, 5 }, { 0, 60 } }, | |
473 | [PM2800_MOD_60V_10A] = { { 0, 60, 0.015, 2, 3 }, { 0, 10, 0.0025, 2, 5 }, { 0, 120 } }, | |
c3eadb07 | 474 | /* Linear modules. */ |
6ed709fe AJ |
475 | [PM2800_MOD_8V_15A] = { { 0, 8, 0.002, 3, 3 }, { -15, 15, 0.00375, 3, 5 }, { 0, 120 } }, |
476 | [PM2800_MOD_60V_2A] = { { 0, 60, 0.015, 2, 3 }, { -2, 2, 0.0005, 3, 4 }, { 0, 120 } }, | |
477 | [PM2800_MOD_120V_1A] = { { 0, 120, 0.030, 2, 2 }, { -1, 1, 0.00025, 3, 5 }, { 0, 120 } }, | |
c3eadb07 BV |
478 | }; |
479 | ||
329733d9 | 480 | static const struct philips_pm2800_model { |
c3eadb07 BV |
481 | unsigned int chassis; |
482 | unsigned int num_modules; | |
483 | unsigned int set; | |
484 | unsigned int modules[3]; | |
485 | } philips_pm2800_matrix[] = { | |
486 | /* Autoranging chassis. */ | |
487 | { 1, 1, 0, { PM2800_MOD_30V_10A, 0, 0 } }, | |
488 | { 1, 1, 1, { PM2800_MOD_60V_5A, 0, 0 } }, | |
489 | { 1, 2, 0, { PM2800_MOD_30V_10A, PM2800_MOD_30V_10A, 0 } }, | |
490 | { 1, 2, 1, { PM2800_MOD_60V_5A, PM2800_MOD_60V_5A, 0 } }, | |
491 | { 1, 2, 2, { PM2800_MOD_30V_10A, PM2800_MOD_60V_5A, 0 } }, | |
492 | { 1, 2, 3, { PM2800_MOD_30V_10A, PM2800_MOD_60V_10A, 0 } }, | |
493 | { 1, 2, 4, { PM2800_MOD_60V_5A, PM2800_MOD_60V_10A, 0 } }, | |
494 | { 1, 3, 0, { PM2800_MOD_30V_10A, PM2800_MOD_30V_10A, PM2800_MOD_30V_10A } }, | |
495 | { 1, 3, 1, { PM2800_MOD_60V_5A, PM2800_MOD_60V_5A, PM2800_MOD_60V_5A } }, | |
496 | { 1, 3, 2, { PM2800_MOD_30V_10A, PM2800_MOD_30V_10A, PM2800_MOD_60V_5A } }, | |
497 | { 1, 3, 3, { PM2800_MOD_30V_10A, PM2800_MOD_60V_5A, PM2800_MOD_60V_5A } }, | |
498 | /* Linear chassis. */ | |
499 | { 3, 1, 0, { PM2800_MOD_60V_2A, 0, 0 } }, | |
500 | { 3, 1, 1, { PM2800_MOD_120V_1A, 0, 0 } }, | |
501 | { 3, 1, 2, { PM2800_MOD_8V_15A, 0, 0 } }, | |
502 | { 3, 2, 0, { PM2800_MOD_60V_2A, 0, 0 } }, | |
503 | { 3, 2, 1, { PM2800_MOD_120V_1A, 0, 0 } }, | |
504 | { 3, 2, 2, { PM2800_MOD_60V_2A, PM2800_MOD_120V_1A, 0 } }, | |
505 | { 3, 2, 3, { PM2800_MOD_8V_15A, PM2800_MOD_8V_15A, 0 } }, | |
506 | }; | |
507 | ||
329733d9 | 508 | static const char *philips_pm2800_names[] = { "1", "2", "3" }; |
c3eadb07 BV |
509 | |
510 | static int philips_pm2800_probe_channels(struct sr_dev_inst *sdi, | |
511 | struct sr_scpi_hw_info *hw_info, | |
512 | struct channel_spec **channels, unsigned int *num_channels, | |
513 | struct channel_group_spec **channel_groups, unsigned int *num_channel_groups) | |
514 | { | |
329733d9 UH |
515 | const struct philips_pm2800_model *model; |
516 | const struct philips_pm2800_module_spec *spec; | |
c3eadb07 BV |
517 | unsigned int chassis, num_modules, set, module, m, i; |
518 | ||
519 | (void)sdi; | |
520 | ||
521 | /* | |
522 | * The model number as reported by *IDN? looks like e.g. PM2813/11, | |
523 | * Where "PM28" is fixed, followed by the chassis code (1 = autoranging, | |
524 | * 3 = linear series) and the number of modules: 1-3 for autoranging, | |
525 | * 1-2 for linear. | |
526 | * After the slash, the first digit denotes the module set. The | |
527 | * digit after that denotes front (5) or rear (1) binding posts. | |
528 | */ | |
529 | chassis = hw_info->model[4] - 0x30; | |
530 | num_modules = hw_info->model[5] - 0x30; | |
531 | set = hw_info->model[7] - 0x30; | |
532 | for (m = 0; m < ARRAY_SIZE(philips_pm2800_matrix); m++) { | |
533 | model = &philips_pm2800_matrix[m]; | |
534 | if (model->chassis == chassis && model->num_modules == num_modules | |
535 | && model->set == set) | |
536 | break; | |
537 | } | |
538 | if (m == ARRAY_SIZE(philips_pm2800_matrix)) { | |
539 | sr_dbg("Model %s not found in matrix.", hw_info->model); | |
540 | return SR_ERR; | |
541 | } | |
542 | ||
543 | sr_dbg("Found %d output channel%s:", num_modules, num_modules > 1 ? "s" : ""); | |
544 | *channels = g_malloc0(sizeof(struct channel_spec) * num_modules); | |
545 | *channel_groups = g_malloc0(sizeof(struct channel_group_spec) * num_modules); | |
546 | for (i = 0; i < num_modules; i++) { | |
547 | module = model->modules[i]; | |
548 | spec = &philips_pm2800_module_specs[module]; | |
6ed709fe | 549 | sr_dbg("output %d: %.0f - %.0fV, %.0f - %.0fA, %.0f - %.0fW", i + 1, |
c3eadb07 | 550 | spec->voltage[0], spec->voltage[1], |
6ed709fe | 551 | spec->current[0], spec->current[1], |
d9251a2c | 552 | spec->power[0], spec->power[1]); |
329733d9 | 553 | (*channels)[i].name = (char *)philips_pm2800_names[i]; |
bcee1299 | 554 | memcpy(&((*channels)[i].voltage), spec, sizeof(double) * 15); |
329733d9 | 555 | (*channel_groups)[i].name = (char *)philips_pm2800_names[i]; |
c3eadb07 BV |
556 | (*channel_groups)[i].channel_index_mask = 1 << i; |
557 | (*channel_groups)[i].features = PPS_OTP | PPS_OVP | PPS_OCP; | |
558 | } | |
559 | *num_channels = *num_channel_groups = num_modules; | |
560 | ||
561 | return SR_OK; | |
562 | } | |
563 | ||
8cb5affe | 564 | static const struct scpi_command philips_pm2800_cmd[] = { |
c3eadb07 BV |
565 | { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" }, |
566 | { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" }, | |
567 | { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" }, | |
568 | { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" }, | |
569 | { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" }, | |
570 | { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" }, | |
571 | { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" }, | |
572 | { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" }, | |
573 | { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" }, | |
574 | { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" }, | |
575 | { SCPI_CMD_GET_OUTPUT_REGULATION, ":SOUR:FUNC:MODE?" }, | |
576 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, ":SOUR:VOLT:PROT:TRIP?" }, | |
577 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:LEV?" }, | |
578 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:LEV %.6f" }, | |
579 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":SOUR:CURR:PROT:STAT?" }, | |
580 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":SOUR:CURR:PROT:STAT ON" }, | |
581 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":SOUR:CURR:PROT:STAT OFF" }, | |
582 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, ":SOUR:CURR:PROT:TRIP?" }, | |
91ef511d | 583 | ALL_ZERO |
c3eadb07 BV |
584 | }; |
585 | ||
81eb36d6 MS |
586 | static const uint32_t rs_hmc8043_devopts[] = { |
587 | SR_CONF_CONTINUOUS, | |
588 | }; | |
589 | ||
590 | static const uint32_t rs_hmc8043_devopts_cg[] = { | |
591 | SR_CONF_OVER_VOLTAGE_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
592 | SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET, | |
593 | SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, | |
594 | SR_CONF_VOLTAGE | SR_CONF_GET, | |
595 | SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
596 | SR_CONF_CURRENT | SR_CONF_GET, | |
597 | SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
598 | SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
599 | }; | |
600 | ||
601 | static const struct channel_spec rs_hmc8043_ch[] = { | |
602 | { "1", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY }, | |
603 | { "2", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY }, | |
604 | { "3", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY }, | |
605 | }; | |
606 | ||
607 | static const struct channel_group_spec rs_hmc8043_cg[] = { | |
608 | { "1", CH_IDX(0), PPS_OVP }, | |
609 | { "2", CH_IDX(1), PPS_OVP }, | |
610 | { "3", CH_IDX(2), PPS_OVP }, | |
611 | }; | |
612 | ||
613 | static const struct scpi_command rs_hmc8043_cmd[] = { | |
614 | { SCPI_CMD_SELECT_CHANNEL, "INST:NSEL %s" }, | |
615 | { SCPI_CMD_GET_MEAS_VOLTAGE, "MEAS:VOLT?" }, | |
616 | { SCPI_CMD_GET_MEAS_CURRENT, "MEAS:CURR?" }, | |
617 | { SCPI_CMD_GET_VOLTAGE_TARGET, "VOLT?" }, | |
618 | { SCPI_CMD_SET_VOLTAGE_TARGET, "VOLT %.6f" }, | |
619 | { SCPI_CMD_GET_CURRENT_LIMIT, "CURR?" }, | |
620 | { SCPI_CMD_SET_CURRENT_LIMIT, "CURR %.6f" }, | |
621 | { SCPI_CMD_GET_OUTPUT_ENABLED, "OUTP?" }, | |
622 | { SCPI_CMD_SET_OUTPUT_ENABLE, "OUTP ON" }, | |
623 | { SCPI_CMD_SET_OUTPUT_DISABLE, "OUTP OFF" }, | |
624 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, "VOLT:PROT:TRIP?" }, | |
625 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "VOLT:PROT:LEV?" }, | |
626 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "VOLT:PROT:LEV %.6f" }, | |
627 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ENABLED, "VOLT:PROT:STAT?" }, | |
628 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_ENABLE, "VOLT:PROT:STAT ON" }, | |
629 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_DISABLE, "VOLT:PROT:STAT OFF" }, | |
630 | ALL_ZERO | |
631 | }; | |
632 | ||
d4eabea8 | 633 | SR_PRIV const struct scpi_pps pps_profiles[] = { |
6cc93128 AG |
634 | /* Agilent N5763A */ |
635 | { "Agilent", "N5763A", 0, | |
636 | ARRAY_AND_SIZE(agilent_n5700a_devopts), | |
637 | ARRAY_AND_SIZE(agilent_n5700a_devopts_cg), | |
638 | ARRAY_AND_SIZE(agilent_n5763a_ch), | |
639 | ARRAY_AND_SIZE(agilent_n5700a_cg), | |
640 | agilent_n5700a_cmd, | |
641 | .probe_channels = NULL, | |
642 | }, | |
ca314e06 | 643 | |
5c9e56c9 AG |
644 | /* Agilent N5767A */ |
645 | { "Agilent", "N5767A", 0, | |
646 | ARRAY_AND_SIZE(agilent_n5700a_devopts), | |
647 | ARRAY_AND_SIZE(agilent_n5700a_devopts_cg), | |
648 | ARRAY_AND_SIZE(agilent_n5767a_ch), | |
6cc93128 | 649 | ARRAY_AND_SIZE(agilent_n5700a_cg), |
91ef511d | 650 | agilent_n5700a_cmd, |
5c9e56c9 AG |
651 | .probe_channels = NULL, |
652 | }, | |
ca314e06 | 653 | |
4ee1e2f3 AG |
654 | /* Chroma 61604 */ |
655 | { "Chroma", "61604", 0, | |
656 | ARRAY_AND_SIZE(chroma_61604_devopts), | |
657 | ARRAY_AND_SIZE(chroma_61604_devopts_cg), | |
658 | ARRAY_AND_SIZE(chroma_61604_ch), | |
659 | ARRAY_AND_SIZE(chroma_61604_cg), | |
91ef511d | 660 | chroma_61604_cmd, |
4ee1e2f3 AG |
661 | .probe_channels = NULL, |
662 | }, | |
ca314e06 | 663 | |
5281993e | 664 | /* Chroma 62000 series */ |
9a5185c7 | 665 | { "Chroma", "620[0-9]{2}P-[0-9]{2,3}-[0-9]{1,3}", 0, |
5281993e AG |
666 | ARRAY_AND_SIZE(chroma_62000_devopts), |
667 | ARRAY_AND_SIZE(chroma_62000_devopts_cg), | |
9a5185c7 AG |
668 | NULL, 0, |
669 | NULL, 0, | |
91ef511d | 670 | chroma_62000_cmd, |
9a5185c7 | 671 | .probe_channels = chroma_62000p_probe_channels, |
5281993e | 672 | }, |
ca314e06 | 673 | |
e76a3575 AG |
674 | /* HP 6633A */ |
675 | { "HP", "6633A", 0, | |
676 | ARRAY_AND_SIZE(hp_6630a_devopts), | |
7c517d02 | 677 | ARRAY_AND_SIZE(hp_6630a_devopts_cg), |
e76a3575 AG |
678 | ARRAY_AND_SIZE(hp_6633a_ch), |
679 | ARRAY_AND_SIZE(hp_663xx_cg), | |
680 | hp_6630a_cmd, | |
681 | .probe_channels = NULL, | |
682 | }, | |
683 | ||
bc4a2a46 BV |
684 | /* HP 6632B */ |
685 | { "HP", "6632B", 0, | |
686 | ARRAY_AND_SIZE(hp_6632b_devopts), | |
7c517d02 | 687 | ARRAY_AND_SIZE(hp_6632b_devopts_cg), |
bc4a2a46 | 688 | ARRAY_AND_SIZE(hp_6632b_ch), |
e76a3575 | 689 | ARRAY_AND_SIZE(hp_663xx_cg), |
91ef511d | 690 | hp_6632b_cmd, |
c3eadb07 | 691 | .probe_channels = NULL, |
bc4a2a46 BV |
692 | }, |
693 | ||
319fe9ce UH |
694 | /* Rigol DP700 series */ |
695 | { "Rigol", "^DP711$", 0, | |
696 | ARRAY_AND_SIZE(rigol_dp700_devopts), | |
697 | ARRAY_AND_SIZE(rigol_dp700_devopts_cg), | |
698 | ARRAY_AND_SIZE(rigol_dp711_ch), | |
699 | ARRAY_AND_SIZE(rigol_dp700_cg), | |
700 | rigol_dp700_cmd, | |
701 | .probe_channels = NULL, | |
702 | }, | |
703 | { "Rigol", "^DP712$", 0, | |
704 | ARRAY_AND_SIZE(rigol_dp700_devopts), | |
705 | ARRAY_AND_SIZE(rigol_dp700_devopts_cg), | |
706 | ARRAY_AND_SIZE(rigol_dp712_ch), | |
707 | ARRAY_AND_SIZE(rigol_dp700_cg), | |
708 | rigol_dp700_cmd, | |
709 | .probe_channels = NULL, | |
710 | }, | |
711 | ||
d4eabea8 | 712 | /* Rigol DP800 series */ |
cfcdf576 ML |
713 | { "Rigol", "^DP821A$", PPS_OTP, |
714 | ARRAY_AND_SIZE(rigol_dp800_devopts), | |
715 | ARRAY_AND_SIZE(rigol_dp800_devopts_cg), | |
716 | ARRAY_AND_SIZE(rigol_dp821a_ch), | |
717 | ARRAY_AND_SIZE(rigol_dp820_cg), | |
91ef511d | 718 | rigol_dp800_cmd, |
cfcdf576 ML |
719 | .probe_channels = NULL, |
720 | }, | |
3222ee10 BV |
721 | { "Rigol", "^DP831A$", PPS_OTP, |
722 | ARRAY_AND_SIZE(rigol_dp800_devopts), | |
723 | ARRAY_AND_SIZE(rigol_dp800_devopts_cg), | |
724 | ARRAY_AND_SIZE(rigol_dp831_ch), | |
cfcdf576 | 725 | ARRAY_AND_SIZE(rigol_dp830_cg), |
91ef511d | 726 | rigol_dp800_cmd, |
c3eadb07 | 727 | .probe_channels = NULL, |
3222ee10 BV |
728 | }, |
729 | { "Rigol", "^(DP832|DP832A)$", PPS_OTP, | |
730 | ARRAY_AND_SIZE(rigol_dp800_devopts), | |
731 | ARRAY_AND_SIZE(rigol_dp800_devopts_cg), | |
732 | ARRAY_AND_SIZE(rigol_dp832_ch), | |
cfcdf576 | 733 | ARRAY_AND_SIZE(rigol_dp830_cg), |
91ef511d | 734 | rigol_dp800_cmd, |
c3eadb07 BV |
735 | .probe_channels = NULL, |
736 | }, | |
737 | ||
738 | /* Philips/Fluke PM2800 series */ | |
739 | { "Philips", "^PM28[13][123]/[01234]{1,2}$", 0, | |
9d9cf1c4 | 740 | ARRAY_AND_SIZE(philips_pm2800_devopts), |
c3eadb07 BV |
741 | ARRAY_AND_SIZE(philips_pm2800_devopts_cg), |
742 | NULL, 0, | |
743 | NULL, 0, | |
91ef511d | 744 | philips_pm2800_cmd, |
c3eadb07 | 745 | philips_pm2800_probe_channels, |
d4eabea8 | 746 | }, |
81eb36d6 MS |
747 | |
748 | /* Rohde & Schwarz HMC8043 */ | |
749 | { "Rohde&Schwarz", "HMC8043", 0, | |
750 | ARRAY_AND_SIZE(rs_hmc8043_devopts), | |
751 | ARRAY_AND_SIZE(rs_hmc8043_devopts_cg), | |
752 | ARRAY_AND_SIZE(rs_hmc8043_ch), | |
753 | ARRAY_AND_SIZE(rs_hmc8043_cg), | |
754 | rs_hmc8043_cmd, | |
755 | .probe_channels = NULL, | |
756 | }, | |
d4eabea8 | 757 | }; |
d4eabea8 | 758 | |
1beccaed | 759 | SR_PRIV unsigned int num_pps_profiles = ARRAY_SIZE(pps_profiles); |