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c463dcf0 MC |
1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se> | |
fec7aa6a MC |
5 | * Copyright (C) 2013 Bert Vermeulen <bert@biot.com> |
6 | * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk> | |
c463dcf0 MC |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
6ec6c43b | 22 | #include <config.h> |
15abcf0f MC |
23 | #include <stdint.h> |
24 | #include <string.h> | |
25 | #include <glib.h> | |
26 | #include <glib/gstdio.h> | |
27 | #include <stdio.h> | |
28 | #include <errno.h> | |
29 | #include <math.h> | |
c1aae900 | 30 | #include <libsigrok/libsigrok.h> |
15abcf0f | 31 | #include "libsigrok-internal.h" |
515ab088 | 32 | #include "protocol.h" |
15abcf0f MC |
33 | |
34 | #define FPGA_FIRMWARE_18 FIRMWARE_DIR"/saleae-logic16-fpga-18.bitstream" | |
35 | #define FPGA_FIRMWARE_33 FIRMWARE_DIR"/saleae-logic16-fpga-33.bitstream" | |
36 | ||
7b5daad4 MC |
37 | #define MAX_SAMPLE_RATE SR_MHZ(100) |
38 | #define MAX_4CH_SAMPLE_RATE SR_MHZ(50) | |
39 | #define MAX_7CH_SAMPLE_RATE SR_MHZ(40) | |
40 | #define MAX_8CH_SAMPLE_RATE SR_MHZ(32) | |
41 | #define MAX_10CH_SAMPLE_RATE SR_MHZ(25) | |
42 | #define MAX_13CH_SAMPLE_RATE SR_MHZ(16) | |
43 | ||
44 | #define BASE_CLOCK_0_FREQ SR_MHZ(100) | |
45 | #define BASE_CLOCK_1_FREQ SR_MHZ(160) | |
46 | ||
15abcf0f MC |
47 | #define COMMAND_START_ACQUISITION 1 |
48 | #define COMMAND_ABORT_ACQUISITION_ASYNC 2 | |
49 | #define COMMAND_WRITE_EEPROM 6 | |
50 | #define COMMAND_READ_EEPROM 7 | |
51 | #define COMMAND_WRITE_LED_TABLE 0x7a | |
52 | #define COMMAND_SET_LED_MODE 0x7b | |
53 | #define COMMAND_RETURN_TO_BOOTLOADER 0x7c | |
54 | #define COMMAND_ABORT_ACQUISITION_SYNC 0x7d | |
55 | #define COMMAND_FPGA_UPLOAD_INIT 0x7e | |
56 | #define COMMAND_FPGA_UPLOAD_SEND_DATA 0x7f | |
57 | #define COMMAND_FPGA_WRITE_REGISTER 0x80 | |
58 | #define COMMAND_FPGA_READ_REGISTER 0x81 | |
59 | #define COMMAND_GET_REVID 0x82 | |
60 | ||
61 | #define WRITE_EEPROM_COOKIE1 0x42 | |
62 | #define WRITE_EEPROM_COOKIE2 0x55 | |
63 | #define READ_EEPROM_COOKIE1 0x33 | |
64 | #define READ_EEPROM_COOKIE2 0x81 | |
65 | #define ABORT_ACQUISITION_SYNC_PATTERN 0x55 | |
66 | ||
7b5daad4 MC |
67 | #define MAX_EMPTY_TRANSFERS 64 |
68 | ||
c8681396 MC |
69 | /* Register mappings for old and new bitstream versions */ |
70 | ||
71 | enum fpga_register_id { | |
72 | FPGA_REGISTER_VERSION, | |
73 | FPGA_REGISTER_STATUS_CONTROL, | |
74 | FPGA_REGISTER_CHANNEL_SELECT_LOW, | |
75 | FPGA_REGISTER_CHANNEL_SELECT_HIGH, | |
76 | FPGA_REGISTER_SAMPLE_RATE_DIVISOR, | |
77 | FPGA_REGISTER_LED_BRIGHTNESS, | |
78 | FPGA_REGISTER_PRIMER_DATA1, | |
79 | FPGA_REGISTER_PRIMER_CONTROL, | |
80 | FPGA_REGISTER_MODE, | |
81 | FPGA_REGISTER_PRIMER_DATA2, | |
82 | FPGA_REGISTER_MAX = FPGA_REGISTER_PRIMER_DATA2 | |
83 | }; | |
84 | ||
85 | enum fpga_status_control_bit { | |
86 | FPGA_STATUS_CONTROL_BIT_RUNNING, | |
87 | FPGA_STATUS_CONTROL_BIT_UPDATE, | |
88 | FPGA_STATUS_CONTROL_BIT_UNKNOWN1, | |
89 | FPGA_STATUS_CONTROL_BIT_OVERFLOW, | |
90 | FPGA_STATUS_CONTROL_BIT_UNKNOWN2, | |
91 | FPGA_STATUS_CONTROL_BIT_MAX = FPGA_STATUS_CONTROL_BIT_UNKNOWN2 | |
92 | }; | |
93 | ||
94 | enum fpga_mode_bit { | |
95 | FPGA_MODE_BIT_CLOCK, | |
96 | FPGA_MODE_BIT_UNKNOWN1, | |
97 | FPGA_MODE_BIT_UNKNOWN2, | |
98 | FPGA_MODE_BIT_MAX = FPGA_MODE_BIT_UNKNOWN2 | |
99 | }; | |
100 | ||
101 | static const uint8_t fpga_register_map_old[FPGA_REGISTER_MAX + 1] = { | |
102 | [FPGA_REGISTER_VERSION] = 0, | |
103 | [FPGA_REGISTER_STATUS_CONTROL] = 1, | |
104 | [FPGA_REGISTER_CHANNEL_SELECT_LOW] = 2, | |
105 | [FPGA_REGISTER_CHANNEL_SELECT_HIGH] = 3, | |
106 | [FPGA_REGISTER_SAMPLE_RATE_DIVISOR] = 4, | |
107 | [FPGA_REGISTER_LED_BRIGHTNESS] = 5, | |
108 | [FPGA_REGISTER_PRIMER_DATA1] = 6, | |
109 | [FPGA_REGISTER_PRIMER_CONTROL] = 7, | |
110 | [FPGA_REGISTER_MODE] = 10, | |
111 | [FPGA_REGISTER_PRIMER_DATA2] = 12, | |
112 | }; | |
113 | ||
114 | static const uint8_t fpga_register_map_new[FPGA_REGISTER_MAX + 1] = { | |
115 | [FPGA_REGISTER_VERSION] = 7, | |
116 | [FPGA_REGISTER_STATUS_CONTROL] = 15, | |
117 | [FPGA_REGISTER_CHANNEL_SELECT_LOW] = 1, | |
118 | [FPGA_REGISTER_CHANNEL_SELECT_HIGH] = 6, | |
119 | [FPGA_REGISTER_SAMPLE_RATE_DIVISOR] = 11, | |
120 | [FPGA_REGISTER_LED_BRIGHTNESS] = 5, | |
121 | [FPGA_REGISTER_PRIMER_DATA1] = 14, | |
122 | [FPGA_REGISTER_PRIMER_CONTROL] = 2, | |
123 | [FPGA_REGISTER_MODE] = 4, | |
124 | [FPGA_REGISTER_PRIMER_DATA2] = 3, | |
125 | }; | |
126 | ||
127 | static const uint8_t fpga_status_control_bit_map_old[FPGA_STATUS_CONTROL_BIT_MAX + 1] = { | |
128 | [FPGA_STATUS_CONTROL_BIT_RUNNING] = 0x01, | |
129 | [FPGA_STATUS_CONTROL_BIT_UPDATE] = 0x02, | |
130 | [FPGA_STATUS_CONTROL_BIT_UNKNOWN1] = 0x08, | |
131 | [FPGA_STATUS_CONTROL_BIT_OVERFLOW] = 0x20, | |
132 | [FPGA_STATUS_CONTROL_BIT_UNKNOWN2] = 0x40, | |
133 | }; | |
134 | ||
135 | static const uint8_t fpga_status_control_bit_map_new[FPGA_STATUS_CONTROL_BIT_MAX + 1] = { | |
136 | [FPGA_STATUS_CONTROL_BIT_RUNNING] = 0x20, | |
137 | [FPGA_STATUS_CONTROL_BIT_UPDATE] = 0x08, | |
138 | [FPGA_STATUS_CONTROL_BIT_UNKNOWN1] = 0x10, | |
139 | [FPGA_STATUS_CONTROL_BIT_OVERFLOW] = 0x01, | |
140 | [FPGA_STATUS_CONTROL_BIT_UNKNOWN2] = 0x04, | |
141 | }; | |
142 | ||
143 | static const uint8_t fpga_mode_bit_map_old[FPGA_MODE_BIT_MAX + 1] = { | |
144 | [FPGA_MODE_BIT_CLOCK] = 0x01, | |
145 | [FPGA_MODE_BIT_UNKNOWN1] = 0x40, | |
146 | [FPGA_MODE_BIT_UNKNOWN2] = 0x80, | |
147 | }; | |
148 | ||
149 | static const uint8_t fpga_mode_bit_map_new[FPGA_MODE_BIT_MAX + 1] = { | |
150 | [FPGA_MODE_BIT_CLOCK] = 0x04, | |
151 | [FPGA_MODE_BIT_UNKNOWN1] = 0x80, | |
152 | [FPGA_MODE_BIT_UNKNOWN2] = 0x01, | |
153 | }; | |
154 | ||
155 | #define FPGA_REG(x) \ | |
156 | (devc->fpga_register_map[FPGA_REGISTER_ ## x]) | |
157 | ||
158 | #define FPGA_STATUS_CONTROL(x) \ | |
159 | (devc->fpga_status_control_bit_map[FPGA_STATUS_CONTROL_BIT_ ## x]) | |
160 | ||
161 | #define FPGA_MODE(x) \ | |
162 | (devc->fpga_mode_bit_map[FPGA_MODE_BIT_ ## x]) | |
163 | ||
15abcf0f MC |
164 | static void encrypt(uint8_t *dest, const uint8_t *src, uint8_t cnt) |
165 | { | |
166 | uint8_t state1 = 0x9b, state2 = 0x54; | |
96484e22 | 167 | uint8_t t, v; |
15abcf0f MC |
168 | int i; |
169 | ||
96484e22 UH |
170 | for (i = 0; i < cnt; i++) { |
171 | v = src[i]; | |
15abcf0f MC |
172 | t = (((v ^ state2 ^ 0x2b) - 0x05) ^ 0x35) - 0x39; |
173 | t = (((t ^ state1 ^ 0x5a) - 0xb0) ^ 0x38) - 0x45; | |
174 | dest[i] = state2 = t; | |
175 | state1 = v; | |
176 | } | |
177 | } | |
178 | ||
179 | static void decrypt(uint8_t *dest, const uint8_t *src, uint8_t cnt) | |
180 | { | |
181 | uint8_t state1 = 0x9b, state2 = 0x54; | |
96484e22 | 182 | uint8_t t, v; |
15abcf0f | 183 | int i; |
96484e22 UH |
184 | |
185 | for (i = 0; i < cnt; i++) { | |
186 | v = src[i]; | |
15abcf0f MC |
187 | t = (((v + 0x45) ^ 0x38) + 0xb0) ^ 0x5a ^ state1; |
188 | t = (((t + 0x39) ^ 0x35) + 0x05) ^ 0x2b ^ state2; | |
189 | dest[i] = state1 = t; | |
190 | state2 = v; | |
191 | } | |
192 | } | |
193 | ||
194 | static int do_ep1_command(const struct sr_dev_inst *sdi, | |
195 | const uint8_t *command, uint8_t cmd_len, | |
196 | uint8_t *reply, uint8_t reply_len) | |
197 | { | |
198 | uint8_t buf[64]; | |
199 | struct sr_usb_dev_inst *usb; | |
200 | int ret, xfer; | |
201 | ||
202 | usb = sdi->conn; | |
203 | ||
204 | if (cmd_len < 1 || cmd_len > 64 || reply_len > 64 || | |
98fec29e | 205 | !command || (reply_len > 0 && !reply)) |
15abcf0f MC |
206 | return SR_ERR_ARG; |
207 | ||
208 | encrypt(buf, command, cmd_len); | |
209 | ||
210 | ret = libusb_bulk_transfer(usb->devhdl, 1, buf, cmd_len, &xfer, 1000); | |
211 | if (ret != 0) { | |
96484e22 | 212 | sr_dbg("Failed to send EP1 command 0x%02x: %s.", |
15abcf0f MC |
213 | command[0], libusb_error_name(ret)); |
214 | return SR_ERR; | |
215 | } | |
216 | if (xfer != cmd_len) { | |
96484e22 | 217 | sr_dbg("Failed to send EP1 command 0x%02x: incorrect length " |
6433156c | 218 | "%d != %d.", command[0], xfer, cmd_len); |
15abcf0f MC |
219 | return SR_ERR; |
220 | } | |
221 | ||
222 | if (reply_len == 0) | |
223 | return SR_OK; | |
224 | ||
96484e22 UH |
225 | ret = libusb_bulk_transfer(usb->devhdl, 0x80 | 1, buf, reply_len, |
226 | &xfer, 1000); | |
15abcf0f | 227 | if (ret != 0) { |
96484e22 | 228 | sr_dbg("Failed to receive reply to EP1 command 0x%02x: %s.", |
15abcf0f MC |
229 | command[0], libusb_error_name(ret)); |
230 | return SR_ERR; | |
231 | } | |
232 | if (xfer != reply_len) { | |
96484e22 | 233 | sr_dbg("Failed to receive reply to EP1 command 0x%02x: " |
6433156c | 234 | "incorrect length %d != %d.", command[0], xfer, reply_len); |
15abcf0f MC |
235 | return SR_ERR; |
236 | } | |
237 | ||
238 | decrypt(reply, buf, reply_len); | |
239 | ||
240 | return SR_OK; | |
241 | } | |
242 | ||
243 | static int read_eeprom(const struct sr_dev_inst *sdi, | |
244 | uint8_t address, uint8_t length, uint8_t *buf) | |
245 | { | |
246 | uint8_t command[5] = { | |
247 | COMMAND_READ_EEPROM, | |
248 | READ_EEPROM_COOKIE1, | |
249 | READ_EEPROM_COOKIE2, | |
250 | address, | |
251 | length, | |
252 | }; | |
253 | ||
254 | return do_ep1_command(sdi, command, 5, buf, length); | |
255 | } | |
256 | ||
257 | static int upload_led_table(const struct sr_dev_inst *sdi, | |
258 | const uint8_t *table, uint8_t offset, uint8_t cnt) | |
259 | { | |
96484e22 | 260 | uint8_t chunk, command[64]; |
15abcf0f MC |
261 | int ret; |
262 | ||
98fec29e | 263 | if (cnt < 1 || cnt + offset > 64 || !table) |
15abcf0f MC |
264 | return SR_ERR_ARG; |
265 | ||
266 | while (cnt > 0) { | |
96484e22 | 267 | chunk = (cnt > 32 ? 32 : cnt); |
15abcf0f MC |
268 | |
269 | command[0] = COMMAND_WRITE_LED_TABLE; | |
270 | command[1] = offset; | |
271 | command[2] = chunk; | |
96484e22 | 272 | memcpy(command + 3, table, chunk); |
15abcf0f | 273 | |
96484e22 UH |
274 | ret = do_ep1_command(sdi, command, 3 + chunk, NULL, 0); |
275 | if (ret != SR_OK) | |
15abcf0f MC |
276 | return ret; |
277 | ||
278 | table += chunk; | |
279 | offset += chunk; | |
280 | cnt -= chunk; | |
281 | } | |
282 | ||
283 | return SR_OK; | |
284 | } | |
285 | ||
286 | static int set_led_mode(const struct sr_dev_inst *sdi, | |
287 | uint8_t animate, uint16_t t2reload, uint8_t div, | |
288 | uint8_t repeat) | |
289 | { | |
290 | uint8_t command[6] = { | |
291 | COMMAND_SET_LED_MODE, | |
292 | animate, | |
96484e22 UH |
293 | t2reload & 0xff, |
294 | t2reload >> 8, | |
15abcf0f MC |
295 | div, |
296 | repeat, | |
297 | }; | |
298 | ||
299 | return do_ep1_command(sdi, command, 6, NULL, 0); | |
300 | } | |
301 | ||
302 | static int read_fpga_register(const struct sr_dev_inst *sdi, | |
303 | uint8_t address, uint8_t *value) | |
304 | { | |
305 | uint8_t command[3] = { | |
306 | COMMAND_FPGA_READ_REGISTER, | |
307 | 1, | |
308 | address, | |
309 | }; | |
310 | ||
311 | return do_ep1_command(sdi, command, 3, value, 1); | |
312 | } | |
313 | ||
314 | static int write_fpga_registers(const struct sr_dev_inst *sdi, | |
315 | uint8_t (*regs)[2], uint8_t cnt) | |
316 | { | |
317 | uint8_t command[64]; | |
318 | int i; | |
319 | ||
320 | if (cnt < 1 || cnt > 31) | |
321 | return SR_ERR_ARG; | |
322 | ||
323 | command[0] = COMMAND_FPGA_WRITE_REGISTER; | |
324 | command[1] = cnt; | |
96484e22 UH |
325 | for (i = 0; i < cnt; i++) { |
326 | command[2 + 2 * i] = regs[i][0]; | |
327 | command[3 + 2 * i] = regs[i][1]; | |
15abcf0f MC |
328 | } |
329 | ||
96484e22 | 330 | return do_ep1_command(sdi, command, 2 * (cnt + 1), NULL, 0); |
15abcf0f MC |
331 | } |
332 | ||
333 | static int write_fpga_register(const struct sr_dev_inst *sdi, | |
334 | uint8_t address, uint8_t value) | |
335 | { | |
336 | uint8_t regs[2] = { address, value }; | |
96484e22 | 337 | |
15abcf0f MC |
338 | return write_fpga_registers(sdi, ®s, 1); |
339 | } | |
340 | ||
15abcf0f MC |
341 | static uint8_t map_eeprom_data(uint8_t v) |
342 | { | |
186dde8d | 343 | return (((v ^ 0x80) + 0x44) ^ 0xd5) + 0x69; |
15abcf0f MC |
344 | } |
345 | ||
c8681396 MC |
346 | static int setup_register_mapping(const struct sr_dev_inst *sdi) |
347 | { | |
348 | struct dev_context *devc; | |
349 | int ret; | |
350 | ||
351 | devc = sdi->priv; | |
352 | ||
353 | if (devc->fpga_variant != FPGA_VARIANT_MCUPRO) { | |
354 | uint8_t reg0, reg7; | |
355 | ||
356 | /* | |
357 | * Check for newer bitstream version by polling the | |
358 | * version register at the old and new location. | |
359 | */ | |
360 | ||
361 | if ((ret = read_fpga_register(sdi, 0 /* No mapping */, ®0)) != SR_OK) | |
362 | return ret; | |
363 | ||
364 | if ((ret = read_fpga_register(sdi, 7 /* No mapping */, ®7)) != SR_OK) | |
365 | return ret; | |
366 | ||
84ab9da1 UH |
367 | if (reg0 == 0 && reg7 > 0x10) { |
368 | sr_info("Original Saleae Logic16 using new bitstream."); | |
c8681396 | 369 | devc->fpga_variant = FPGA_VARIANT_ORIGINAL_NEW_BITSTREAM; |
84ab9da1 UH |
370 | } else { |
371 | sr_info("Original Saleae Logic16 using old bitstream."); | |
c8681396 | 372 | devc->fpga_variant = FPGA_VARIANT_ORIGINAL; |
84ab9da1 | 373 | } |
c8681396 MC |
374 | } |
375 | ||
376 | if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL_NEW_BITSTREAM) { | |
377 | devc->fpga_register_map = fpga_register_map_new; | |
378 | devc->fpga_status_control_bit_map = fpga_status_control_bit_map_new; | |
379 | devc->fpga_mode_bit_map = fpga_mode_bit_map_new; | |
380 | } else { | |
381 | devc->fpga_register_map = fpga_register_map_old; | |
382 | devc->fpga_status_control_bit_map = fpga_status_control_bit_map_old; | |
383 | devc->fpga_mode_bit_map = fpga_mode_bit_map_old; | |
384 | } | |
385 | ||
386 | return SR_OK; | |
387 | } | |
388 | ||
15abcf0f MC |
389 | static int prime_fpga(const struct sr_dev_inst *sdi) |
390 | { | |
c8681396 | 391 | struct dev_context *devc = sdi->priv; |
15abcf0f | 392 | uint8_t eeprom_data[16]; |
c8681396 | 393 | uint8_t old_mode_reg, version; |
15abcf0f | 394 | uint8_t regs[8][2] = { |
c8681396 MC |
395 | {FPGA_REG(MODE), 0x00}, |
396 | {FPGA_REG(MODE), FPGA_MODE(UNKNOWN1)}, | |
397 | {FPGA_REG(PRIMER_DATA2), 0}, | |
398 | {FPGA_REG(MODE), FPGA_MODE(UNKNOWN1) | FPGA_MODE(UNKNOWN2)}, | |
399 | {FPGA_REG(MODE), FPGA_MODE(UNKNOWN1)}, | |
400 | {FPGA_REG(PRIMER_DATA1), 0}, | |
401 | {FPGA_REG(PRIMER_CONTROL), 1}, | |
402 | {FPGA_REG(PRIMER_CONTROL), 0} | |
15abcf0f MC |
403 | }; |
404 | int i, ret; | |
405 | ||
406 | if ((ret = read_eeprom(sdi, 16, 16, eeprom_data)) != SR_OK) | |
407 | return ret; | |
408 | ||
c8681396 | 409 | if ((ret = read_fpga_register(sdi, FPGA_REG(MODE), &old_mode_reg)) != SR_OK) |
15abcf0f MC |
410 | return ret; |
411 | ||
c8681396 MC |
412 | regs[0][1] = (old_mode_reg &= ~FPGA_MODE(UNKNOWN2)); |
413 | regs[1][1] |= old_mode_reg; | |
414 | regs[3][1] |= old_mode_reg; | |
415 | regs[4][1] |= old_mode_reg; | |
186dde8d | 416 | |
96484e22 | 417 | for (i = 0; i < 16; i++) { |
15abcf0f MC |
418 | regs[2][1] = eeprom_data[i]; |
419 | regs[5][1] = map_eeprom_data(eeprom_data[i]); | |
420 | if (i) | |
421 | ret = write_fpga_registers(sdi, ®s[2], 6); | |
422 | else | |
423 | ret = write_fpga_registers(sdi, ®s[0], 8); | |
424 | if (ret != SR_OK) | |
425 | return ret; | |
426 | } | |
427 | ||
c8681396 | 428 | if ((ret = write_fpga_register(sdi, FPGA_REG(MODE), old_mode_reg)) != SR_OK) |
15abcf0f MC |
429 | return ret; |
430 | ||
c8681396 | 431 | if ((ret = read_fpga_register(sdi, FPGA_REG(VERSION), &version)) != SR_OK) |
15abcf0f MC |
432 | return ret; |
433 | ||
c8681396 | 434 | if (version != 0x10 && version != 0x13 && version != 0x40 && version != 0x41) { |
6f479a0a | 435 | sr_err("Unsupported FPGA version: 0x%02x.", version); |
15abcf0f MC |
436 | return SR_ERR; |
437 | } | |
438 | ||
439 | return SR_OK; | |
440 | } | |
441 | ||
442 | static void make_heartbeat(uint8_t *table, int len) | |
443 | { | |
444 | int i, j; | |
445 | ||
446 | memset(table, 0, len); | |
447 | len >>= 3; | |
96484e22 UH |
448 | for (i = 0; i < 2; i++) |
449 | for (j = 0; j < len; j++) | |
bbc42811 | 450 | *table++ = sin(j * G_PI / len) * 255; |
15abcf0f MC |
451 | } |
452 | ||
453 | static int configure_led(const struct sr_dev_inst *sdi) | |
454 | { | |
455 | uint8_t table[64]; | |
456 | int ret; | |
457 | ||
458 | make_heartbeat(table, 64); | |
459 | if ((ret = upload_led_table(sdi, table, 0, 64)) != SR_OK) | |
460 | return ret; | |
461 | ||
462 | return set_led_mode(sdi, 1, 6250, 0, 1); | |
463 | } | |
464 | ||
465 | static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, | |
466 | enum voltage_range vrange) | |
467 | { | |
468 | struct dev_context *devc; | |
469 | int offset, chunksize, ret; | |
470 | const char *filename; | |
96484e22 | 471 | uint8_t len, buf[256 * 62], command[64]; |
15abcf0f | 472 | FILE *fw; |
15abcf0f MC |
473 | |
474 | devc = sdi->priv; | |
475 | ||
476 | if (devc->cur_voltage_range == vrange) | |
477 | return SR_OK; | |
478 | ||
c8681396 | 479 | if (devc->fpga_variant != FPGA_VARIANT_MCUPRO) { |
6f479a0a PZ |
480 | switch (vrange) { |
481 | case VOLTAGE_RANGE_18_33_V: | |
482 | filename = FPGA_FIRMWARE_18; | |
483 | break; | |
484 | case VOLTAGE_RANGE_5_V: | |
485 | filename = FPGA_FIRMWARE_33; | |
486 | break; | |
487 | default: | |
488 | sr_err("Unsupported voltage range."); | |
489 | return SR_ERR; | |
490 | } | |
15abcf0f | 491 | |
6f479a0a | 492 | sr_info("Uploading FPGA bitstream at %s.", filename); |
98fec29e | 493 | if (!(fw = g_fopen(filename, "rb"))) { |
6f479a0a | 494 | sr_err("Unable to open bitstream file %s for reading: %s.", |
7237e912 | 495 | filename, g_strerror(errno)); |
6f479a0a PZ |
496 | return SR_ERR; |
497 | } | |
15abcf0f | 498 | |
6f479a0a PZ |
499 | buf[0] = COMMAND_FPGA_UPLOAD_INIT; |
500 | if ((ret = do_ep1_command(sdi, buf, 1, NULL, 0)) != SR_OK) { | |
501 | fclose(fw); | |
502 | return ret; | |
503 | } | |
15abcf0f | 504 | |
6f479a0a PZ |
505 | while (1) { |
506 | chunksize = fread(buf, 1, sizeof(buf), fw); | |
507 | if (chunksize == 0) | |
508 | break; | |
509 | ||
510 | for (offset = 0; offset < chunksize; offset += 62) { | |
511 | len = (offset + 62 > chunksize ? | |
512 | chunksize - offset : 62); | |
513 | command[0] = COMMAND_FPGA_UPLOAD_SEND_DATA; | |
514 | command[1] = len; | |
515 | memcpy(command + 2, buf + offset, len); | |
516 | ret = do_ep1_command(sdi, command, len + 2, NULL, 0); | |
517 | if (ret != SR_OK) { | |
518 | fclose(fw); | |
519 | return ret; | |
520 | } | |
15abcf0f | 521 | } |
15abcf0f | 522 | |
6f479a0a PZ |
523 | sr_info("Uploaded %d bytes.", chunksize); |
524 | } | |
525 | fclose(fw); | |
526 | sr_info("FPGA bitstream upload done."); | |
15abcf0f | 527 | } |
15abcf0f | 528 | |
c8681396 MC |
529 | /* This needs to be called before accessing any FPGA registers. */ |
530 | if ((ret = setup_register_mapping(sdi)) != SR_OK) | |
531 | return ret; | |
532 | ||
15abcf0f MC |
533 | if ((ret = prime_fpga(sdi)) != SR_OK) |
534 | return ret; | |
535 | ||
536 | if ((ret = configure_led(sdi)) != SR_OK) | |
537 | return ret; | |
538 | ||
15abcf0f MC |
539 | devc->cur_voltage_range = vrange; |
540 | return SR_OK; | |
541 | } | |
542 | ||
7b5daad4 | 543 | static int abort_acquisition_sync(const struct sr_dev_inst *sdi) |
15abcf0f MC |
544 | { |
545 | static const uint8_t command[2] = { | |
546 | COMMAND_ABORT_ACQUISITION_SYNC, | |
547 | ABORT_ACQUISITION_SYNC_PATTERN, | |
548 | }; | |
549 | uint8_t reply, expected_reply; | |
550 | int ret; | |
551 | ||
552 | if ((ret = do_ep1_command(sdi, command, 2, &reply, 1)) != SR_OK) | |
553 | return ret; | |
554 | ||
555 | expected_reply = ~command[1]; | |
556 | if (reply != expected_reply) { | |
557 | sr_err("Invalid response for abort acquisition command: " | |
96484e22 | 558 | "0x%02x != 0x%02x.", reply, expected_reply); |
15abcf0f MC |
559 | return SR_ERR; |
560 | } | |
561 | ||
562 | return SR_OK; | |
563 | } | |
564 | ||
96484e22 UH |
565 | SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi, |
566 | uint64_t samplerate, uint16_t channels) | |
7b5daad4 | 567 | { |
c8681396 | 568 | uint8_t clock_select, sta_con_reg, mode_reg; |
7b5daad4 MC |
569 | uint64_t div; |
570 | int i, ret, nchan = 0; | |
db11d7d2 MC |
571 | struct dev_context *devc; |
572 | ||
573 | devc = sdi->priv; | |
7b5daad4 MC |
574 | |
575 | if (samplerate == 0 || samplerate > MAX_SAMPLE_RATE) { | |
576 | sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate); | |
577 | return SR_ERR; | |
578 | } | |
579 | ||
580 | if (BASE_CLOCK_0_FREQ % samplerate == 0 && | |
581 | (div = BASE_CLOCK_0_FREQ / samplerate) <= 256) { | |
582 | clock_select = 0; | |
583 | } else if (BASE_CLOCK_1_FREQ % samplerate == 0 && | |
584 | (div = BASE_CLOCK_1_FREQ / samplerate) <= 256) { | |
585 | clock_select = 1; | |
586 | } else { | |
587 | sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate); | |
588 | return SR_ERR; | |
589 | } | |
590 | ||
96484e22 UH |
591 | for (i = 0; i < 16; i++) |
592 | if (channels & (1U << i)) | |
7b5daad4 MC |
593 | nchan++; |
594 | ||
595 | if ((nchan >= 13 && samplerate > MAX_13CH_SAMPLE_RATE) || | |
596 | (nchan >= 10 && samplerate > MAX_10CH_SAMPLE_RATE) || | |
597 | (nchan >= 8 && samplerate > MAX_8CH_SAMPLE_RATE) || | |
598 | (nchan >= 7 && samplerate > MAX_7CH_SAMPLE_RATE) || | |
599 | (nchan >= 4 && samplerate > MAX_4CH_SAMPLE_RATE)) { | |
600 | sr_err("Unable to sample at %" PRIu64 "Hz " | |
601 | "with this many channels.", samplerate); | |
602 | return SR_ERR; | |
603 | } | |
604 | ||
96484e22 UH |
605 | ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range); |
606 | if (ret != SR_OK) | |
db11d7d2 MC |
607 | return ret; |
608 | ||
c8681396 | 609 | if ((ret = read_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), &sta_con_reg)) != SR_OK) |
7b5daad4 MC |
610 | return ret; |
611 | ||
7754fb4d | 612 | /* Ignore FIFO overflow on previous capture */ |
c8681396 | 613 | sta_con_reg &= ~FPGA_STATUS_CONTROL(OVERFLOW); |
7754fb4d | 614 | |
c8681396 MC |
615 | if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && sta_con_reg != FPGA_STATUS_CONTROL(UNKNOWN1)) { |
616 | sr_dbg("Invalid state at acquisition setup register 1: 0x%02x != 0x%02x. " | |
617 | "Proceeding anyway.", sta_con_reg, FPGA_STATUS_CONTROL(UNKNOWN1)); | |
7b5daad4 MC |
618 | } |
619 | ||
c8681396 | 620 | if ((ret = write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), FPGA_STATUS_CONTROL(UNKNOWN2))) != SR_OK) |
7b5daad4 MC |
621 | return ret; |
622 | ||
c8681396 | 623 | if ((ret = write_fpga_register(sdi, FPGA_REG(MODE), (clock_select? FPGA_MODE(CLOCK) : 0))) != SR_OK) |
7b5daad4 MC |
624 | return ret; |
625 | ||
c8681396 | 626 | if ((ret = write_fpga_register(sdi, FPGA_REG(SAMPLE_RATE_DIVISOR), (uint8_t)(div - 1))) != SR_OK) |
7b5daad4 MC |
627 | return ret; |
628 | ||
c8681396 | 629 | if ((ret = write_fpga_register(sdi, FPGA_REG(CHANNEL_SELECT_LOW), (uint8_t)(channels & 0xff))) != SR_OK) |
7b5daad4 MC |
630 | return ret; |
631 | ||
c8681396 | 632 | if ((ret = write_fpga_register(sdi, FPGA_REG(CHANNEL_SELECT_HIGH), (uint8_t)(channels >> 8))) != SR_OK) |
7b5daad4 MC |
633 | return ret; |
634 | ||
c8681396 | 635 | if ((ret = write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), FPGA_STATUS_CONTROL(UNKNOWN2) | FPGA_STATUS_CONTROL(UPDATE))) != SR_OK) |
7b5daad4 MC |
636 | return ret; |
637 | ||
c8681396 | 638 | if ((ret = write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), FPGA_STATUS_CONTROL(UNKNOWN2))) != SR_OK) |
7b5daad4 MC |
639 | return ret; |
640 | ||
c8681396 | 641 | if ((ret = read_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), &sta_con_reg)) != SR_OK) |
7b5daad4 MC |
642 | return ret; |
643 | ||
c8681396 MC |
644 | if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && sta_con_reg != (FPGA_STATUS_CONTROL(UNKNOWN2) | FPGA_STATUS_CONTROL(UNKNOWN1))) { |
645 | sr_dbg("Invalid state at acquisition setup register 1: 0x%02x != 0x%02x. " | |
646 | "Proceeding anyway.", sta_con_reg, FPGA_STATUS_CONTROL(UNKNOWN2) | FPGA_STATUS_CONTROL(UNKNOWN1)); | |
7b5daad4 MC |
647 | } |
648 | ||
c8681396 | 649 | if ((ret = read_fpga_register(sdi, FPGA_REG(MODE), &mode_reg)) != SR_OK) |
7b5daad4 MC |
650 | return ret; |
651 | ||
c8681396 | 652 | if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && mode_reg != (clock_select? FPGA_MODE(CLOCK) : 0)) { |
a11e10ec | 653 | sr_dbg("Invalid state at acquisition setup register 10: 0x%02x != 0x%02x. " |
c8681396 | 654 | "Proceeding anyway.", mode_reg, (clock_select? FPGA_MODE(CLOCK) : 0)); |
7b5daad4 MC |
655 | } |
656 | ||
657 | return SR_OK; | |
658 | } | |
659 | ||
96484e22 | 660 | SR_PRIV int logic16_start_acquisition(const struct sr_dev_inst *sdi) |
7b5daad4 MC |
661 | { |
662 | static const uint8_t command[1] = { | |
663 | COMMAND_START_ACQUISITION, | |
664 | }; | |
665 | int ret; | |
c8681396 MC |
666 | struct dev_context *devc; |
667 | ||
668 | devc = sdi->priv; | |
7b5daad4 MC |
669 | |
670 | if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK) | |
671 | return ret; | |
672 | ||
c8681396 | 673 | return write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), FPGA_STATUS_CONTROL(UNKNOWN2) | FPGA_STATUS_CONTROL(RUNNING)); |
7b5daad4 MC |
674 | } |
675 | ||
96484e22 | 676 | SR_PRIV int logic16_abort_acquisition(const struct sr_dev_inst *sdi) |
7b5daad4 MC |
677 | { |
678 | static const uint8_t command[1] = { | |
679 | COMMAND_ABORT_ACQUISITION_ASYNC, | |
680 | }; | |
681 | int ret; | |
c8681396 | 682 | uint8_t sta_con_reg; |
6f479a0a PZ |
683 | struct dev_context *devc; |
684 | ||
685 | devc = sdi->priv; | |
7b5daad4 MC |
686 | |
687 | if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK) | |
688 | return ret; | |
689 | ||
c8681396 | 690 | if ((ret = write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), 0x00)) != SR_OK) |
7b5daad4 MC |
691 | return ret; |
692 | ||
c8681396 | 693 | if ((ret = read_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), &sta_con_reg)) != SR_OK) |
7b5daad4 MC |
694 | return ret; |
695 | ||
c8681396 MC |
696 | if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && (sta_con_reg & ~FPGA_STATUS_CONTROL(OVERFLOW)) != FPGA_STATUS_CONTROL(UNKNOWN1)) { |
697 | sr_dbg("Invalid state at acquisition stop: 0x%02x != 0x%02x.", sta_con_reg & ~0x20, FPGA_STATUS_CONTROL(UNKNOWN1)); | |
7b5daad4 MC |
698 | return SR_ERR; |
699 | } | |
700 | ||
7b5daad4 | 701 | |
c8681396 MC |
702 | if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL) { |
703 | uint8_t reg8, reg9; | |
704 | ||
705 | if ((ret = read_fpga_register(sdi, 8, ®8)) != SR_OK) | |
706 | return ret; | |
707 | ||
708 | if ((ret = read_fpga_register(sdi, 9, ®9)) != SR_OK) | |
709 | return ret; | |
710 | } | |
7b5daad4 | 711 | |
c8681396 | 712 | if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && sta_con_reg & FPGA_STATUS_CONTROL(OVERFLOW)) { |
7754fb4d MC |
713 | sr_warn("FIFO overflow, capture data may be truncated."); |
714 | return SR_ERR; | |
715 | } | |
716 | ||
7b5daad4 MC |
717 | return SR_OK; |
718 | } | |
719 | ||
96484e22 | 720 | SR_PRIV int logic16_init_device(const struct sr_dev_inst *sdi) |
15abcf0f | 721 | { |
6f479a0a | 722 | uint8_t version; |
15abcf0f MC |
723 | struct dev_context *devc; |
724 | int ret; | |
725 | ||
726 | devc = sdi->priv; | |
727 | ||
728 | devc->cur_voltage_range = VOLTAGE_RANGE_UNKNOWN; | |
729 | ||
7b5daad4 | 730 | if ((ret = abort_acquisition_sync(sdi)) != SR_OK) |
15abcf0f MC |
731 | return ret; |
732 | ||
733 | if ((ret = read_eeprom(sdi, 8, 8, devc->eeprom_data)) != SR_OK) | |
734 | return ret; | |
735 | ||
6f479a0a PZ |
736 | /* mcupro Saleae16 has firmware pre-stored in FPGA. |
737 | So, we can query it right away. */ | |
c8681396 | 738 | if (read_fpga_register(sdi, 0 /* No mapping */, &version) == SR_OK && |
6f479a0a PZ |
739 | (version == 0x40 || version == 0x41)) { |
740 | sr_info("mcupro Saleae16 detected."); | |
741 | devc->fpga_variant = FPGA_VARIANT_MCUPRO; | |
742 | } else { | |
743 | sr_info("Original Saleae Logic16 detected."); | |
744 | devc->fpga_variant = FPGA_VARIANT_ORIGINAL; | |
745 | } | |
746 | ||
96484e22 UH |
747 | ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range); |
748 | if (ret != SR_OK) | |
15abcf0f MC |
749 | return ret; |
750 | ||
751 | return SR_OK; | |
752 | } | |
753 | ||
102f1239 | 754 | static void finish_acquisition(struct sr_dev_inst *sdi) |
7b5daad4 MC |
755 | { |
756 | struct sr_datafeed_packet packet; | |
102f1239 BV |
757 | struct dev_context *devc; |
758 | ||
759 | devc = sdi->priv; | |
7b5daad4 MC |
760 | |
761 | /* Terminate session. */ | |
762 | packet.type = SR_DF_END; | |
763 | sr_session_send(devc->cb_data, &packet); | |
764 | ||
765 | /* Remove fds from polling. */ | |
102f1239 | 766 | usb_source_remove(sdi->session, devc->ctx); |
7b5daad4 MC |
767 | |
768 | devc->num_transfers = 0; | |
769 | g_free(devc->transfers); | |
770 | g_free(devc->convbuffer); | |
863357fb BV |
771 | if (devc->stl) { |
772 | soft_trigger_logic_free(devc->stl); | |
773 | devc->stl = NULL; | |
774 | } | |
7b5daad4 MC |
775 | } |
776 | ||
777 | static void free_transfer(struct libusb_transfer *transfer) | |
778 | { | |
102f1239 | 779 | struct sr_dev_inst *sdi; |
7b5daad4 MC |
780 | struct dev_context *devc; |
781 | unsigned int i; | |
782 | ||
102f1239 BV |
783 | sdi = transfer->user_data; |
784 | devc = sdi->priv; | |
7b5daad4 MC |
785 | |
786 | g_free(transfer->buffer); | |
787 | transfer->buffer = NULL; | |
788 | libusb_free_transfer(transfer); | |
789 | ||
790 | for (i = 0; i < devc->num_transfers; i++) { | |
791 | if (devc->transfers[i] == transfer) { | |
792 | devc->transfers[i] = NULL; | |
793 | break; | |
794 | } | |
795 | } | |
796 | ||
797 | devc->submitted_transfers--; | |
798 | if (devc->submitted_transfers == 0) | |
102f1239 | 799 | finish_acquisition(sdi); |
7b5daad4 MC |
800 | } |
801 | ||
802 | static void resubmit_transfer(struct libusb_transfer *transfer) | |
803 | { | |
804 | int ret; | |
805 | ||
806 | if ((ret = libusb_submit_transfer(transfer)) == LIBUSB_SUCCESS) | |
807 | return; | |
808 | ||
809 | free_transfer(transfer); | |
810 | /* TODO: Stop session? */ | |
811 | ||
812 | sr_err("%s: %s", __func__, libusb_error_name(ret)); | |
813 | } | |
814 | ||
a989cdbe BV |
815 | static size_t convert_sample_data(struct dev_context *devc, |
816 | uint8_t *dest, size_t destcnt, const uint8_t *src, size_t srccnt) | |
c463dcf0 | 817 | { |
7b5daad4 MC |
818 | uint16_t *channel_data; |
819 | int i, cur_channel; | |
820 | size_t ret = 0; | |
96484e22 | 821 | uint16_t sample, channel_mask; |
7b5daad4 MC |
822 | |
823 | srccnt /= 2; | |
824 | ||
825 | channel_data = devc->channel_data; | |
826 | cur_channel = devc->cur_channel; | |
827 | ||
96484e22 | 828 | while (srccnt--) { |
7b5daad4 MC |
829 | sample = src[0] | (src[1] << 8); |
830 | src += 2; | |
831 | ||
832 | channel_mask = devc->channel_masks[cur_channel]; | |
833 | ||
96484e22 | 834 | for (i = 15; i >= 0; --i, sample >>= 1) |
7b5daad4 MC |
835 | if (sample & 1) |
836 | channel_data[i] |= channel_mask; | |
837 | ||
838 | if (++cur_channel == devc->num_channels) { | |
839 | cur_channel = 0; | |
96484e22 | 840 | if (destcnt < 16 * 2) { |
7b5daad4 MC |
841 | sr_err("Conversion buffer too small!"); |
842 | break; | |
843 | } | |
96484e22 UH |
844 | memcpy(dest, channel_data, 16 * 2); |
845 | memset(channel_data, 0, 16 * 2); | |
846 | dest += 16 * 2; | |
1b822521 | 847 | ret += 16; |
96484e22 | 848 | destcnt -= 16 * 2; |
7b5daad4 MC |
849 | } |
850 | } | |
851 | ||
852 | devc->cur_channel = cur_channel; | |
c463dcf0 | 853 | |
7b5daad4 MC |
854 | return ret; |
855 | } | |
856 | ||
55462b8b | 857 | SR_PRIV void LIBUSB_CALL logic16_receive_transfer(struct libusb_transfer *transfer) |
7b5daad4 MC |
858 | { |
859 | gboolean packet_has_error = FALSE; | |
860 | struct sr_datafeed_packet packet; | |
861 | struct sr_datafeed_logic logic; | |
102f1239 | 862 | struct sr_dev_inst *sdi; |
c463dcf0 | 863 | struct dev_context *devc; |
863357fb BV |
864 | size_t new_samples, num_samples; |
865 | int trigger_offset; | |
5a971f66 | 866 | int pre_trigger_samples; |
7b5daad4 | 867 | |
102f1239 BV |
868 | sdi = transfer->user_data; |
869 | devc = sdi->priv; | |
7b5daad4 MC |
870 | |
871 | /* | |
872 | * If acquisition has already ended, just free any queued up | |
873 | * transfer that come in. | |
874 | */ | |
863357fb | 875 | if (devc->sent_samples < 0) { |
7b5daad4 MC |
876 | free_transfer(transfer); |
877 | return; | |
878 | } | |
879 | ||
974fb0ff BV |
880 | sr_info("receive_transfer(): status %s received %d bytes.", |
881 | libusb_error_name(transfer->status), transfer->actual_length); | |
7b5daad4 MC |
882 | |
883 | switch (transfer->status) { | |
884 | case LIBUSB_TRANSFER_NO_DEVICE: | |
863357fb | 885 | devc->sent_samples = -2; |
7b5daad4 MC |
886 | free_transfer(transfer); |
887 | return; | |
888 | case LIBUSB_TRANSFER_COMPLETED: | |
889 | case LIBUSB_TRANSFER_TIMED_OUT: /* We may have received some data though. */ | |
890 | break; | |
891 | default: | |
892 | packet_has_error = TRUE; | |
893 | break; | |
894 | } | |
c463dcf0 | 895 | |
7b5daad4 | 896 | if (transfer->actual_length & 1) { |
96484e22 UH |
897 | sr_err("Got an odd number of bytes from the device. " |
898 | "This should not happen."); | |
899 | /* Bail out right away. */ | |
7b5daad4 MC |
900 | packet_has_error = TRUE; |
901 | devc->empty_transfer_count = MAX_EMPTY_TRANSFERS; | |
902 | } | |
c463dcf0 | 903 | |
7b5daad4 MC |
904 | if (transfer->actual_length == 0 || packet_has_error) { |
905 | devc->empty_transfer_count++; | |
906 | if (devc->empty_transfer_count > MAX_EMPTY_TRANSFERS) { | |
907 | /* | |
908 | * The FX2 gave up. End the acquisition, the frontend | |
909 | * will work out that the samplecount is short. | |
910 | */ | |
863357fb | 911 | devc->sent_samples = -2; |
7b5daad4 MC |
912 | free_transfer(transfer); |
913 | } else { | |
914 | resubmit_transfer(transfer); | |
915 | } | |
916 | return; | |
917 | } else { | |
918 | devc->empty_transfer_count = 0; | |
919 | } | |
c463dcf0 | 920 | |
863357fb | 921 | new_samples = convert_sample_data(devc, devc->convbuffer, |
a989cdbe | 922 | devc->convbuffer_size, transfer->buffer, transfer->actual_length); |
863357fb BV |
923 | |
924 | if (new_samples > 0) { | |
925 | if (devc->trigger_fired) { | |
926 | /* Send the incoming transfer to the session bus. */ | |
927 | packet.type = SR_DF_LOGIC; | |
928 | packet.payload = &logic; | |
929 | if (devc->limit_samples && | |
930 | new_samples > devc->limit_samples - devc->sent_samples) | |
931 | new_samples = devc->limit_samples - devc->sent_samples; | |
a989cdbe BV |
932 | logic.length = new_samples * 2; |
933 | logic.unitsize = 2; | |
863357fb BV |
934 | logic.data = devc->convbuffer; |
935 | sr_session_send(devc->cb_data, &packet); | |
936 | devc->sent_samples += new_samples; | |
937 | } else { | |
938 | trigger_offset = soft_trigger_logic_check(devc->stl, | |
5a971f66 | 939 | devc->convbuffer, new_samples * 2, &pre_trigger_samples); |
863357fb | 940 | if (trigger_offset > -1) { |
5a971f66 | 941 | devc->sent_samples += pre_trigger_samples; |
863357fb BV |
942 | packet.type = SR_DF_LOGIC; |
943 | packet.payload = &logic; | |
944 | num_samples = new_samples - trigger_offset; | |
945 | if (devc->limit_samples && | |
946 | num_samples > devc->limit_samples - devc->sent_samples) | |
947 | num_samples = devc->limit_samples - devc->sent_samples; | |
a989cdbe BV |
948 | logic.length = num_samples * 2; |
949 | logic.unitsize = 2; | |
950 | logic.data = devc->convbuffer + trigger_offset * 2; | |
863357fb BV |
951 | sr_session_send(devc->cb_data, &packet); |
952 | devc->sent_samples += num_samples; | |
953 | ||
954 | devc->trigger_fired = TRUE; | |
955 | } | |
2db95906 MC |
956 | } |
957 | ||
7b5daad4 | 958 | if (devc->limit_samples && |
863357fb BV |
959 | (uint64_t)devc->sent_samples >= devc->limit_samples) { |
960 | devc->sent_samples = -2; | |
7b5daad4 MC |
961 | free_transfer(transfer); |
962 | return; | |
963 | } | |
c463dcf0 MC |
964 | } |
965 | ||
7b5daad4 | 966 | resubmit_transfer(transfer); |
c463dcf0 | 967 | } |