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c463dcf0 MC |
1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se> | |
fec7aa6a MC |
5 | * Copyright (C) 2013 Bert Vermeulen <bert@biot.com> |
6 | * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk> | |
c463dcf0 MC |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
15abcf0f MC |
22 | #include <stdint.h> |
23 | #include <string.h> | |
24 | #include <glib.h> | |
25 | #include <glib/gstdio.h> | |
26 | #include <stdio.h> | |
27 | #include <errno.h> | |
28 | #include <math.h> | |
29 | #include "libsigrok.h" | |
30 | #include "libsigrok-internal.h" | |
515ab088 | 31 | #include "protocol.h" |
15abcf0f MC |
32 | |
33 | #define FPGA_FIRMWARE_18 FIRMWARE_DIR"/saleae-logic16-fpga-18.bitstream" | |
34 | #define FPGA_FIRMWARE_33 FIRMWARE_DIR"/saleae-logic16-fpga-33.bitstream" | |
35 | ||
7b5daad4 MC |
36 | #define MAX_SAMPLE_RATE SR_MHZ(100) |
37 | #define MAX_4CH_SAMPLE_RATE SR_MHZ(50) | |
38 | #define MAX_7CH_SAMPLE_RATE SR_MHZ(40) | |
39 | #define MAX_8CH_SAMPLE_RATE SR_MHZ(32) | |
40 | #define MAX_10CH_SAMPLE_RATE SR_MHZ(25) | |
41 | #define MAX_13CH_SAMPLE_RATE SR_MHZ(16) | |
42 | ||
43 | #define BASE_CLOCK_0_FREQ SR_MHZ(100) | |
44 | #define BASE_CLOCK_1_FREQ SR_MHZ(160) | |
45 | ||
15abcf0f MC |
46 | #define COMMAND_START_ACQUISITION 1 |
47 | #define COMMAND_ABORT_ACQUISITION_ASYNC 2 | |
48 | #define COMMAND_WRITE_EEPROM 6 | |
49 | #define COMMAND_READ_EEPROM 7 | |
50 | #define COMMAND_WRITE_LED_TABLE 0x7a | |
51 | #define COMMAND_SET_LED_MODE 0x7b | |
52 | #define COMMAND_RETURN_TO_BOOTLOADER 0x7c | |
53 | #define COMMAND_ABORT_ACQUISITION_SYNC 0x7d | |
54 | #define COMMAND_FPGA_UPLOAD_INIT 0x7e | |
55 | #define COMMAND_FPGA_UPLOAD_SEND_DATA 0x7f | |
56 | #define COMMAND_FPGA_WRITE_REGISTER 0x80 | |
57 | #define COMMAND_FPGA_READ_REGISTER 0x81 | |
58 | #define COMMAND_GET_REVID 0x82 | |
59 | ||
60 | #define WRITE_EEPROM_COOKIE1 0x42 | |
61 | #define WRITE_EEPROM_COOKIE2 0x55 | |
62 | #define READ_EEPROM_COOKIE1 0x33 | |
63 | #define READ_EEPROM_COOKIE2 0x81 | |
64 | #define ABORT_ACQUISITION_SYNC_PATTERN 0x55 | |
65 | ||
7b5daad4 MC |
66 | #define MAX_EMPTY_TRANSFERS 64 |
67 | ||
c8681396 MC |
68 | /* Register mappings for old and new bitstream versions */ |
69 | ||
70 | enum fpga_register_id { | |
71 | FPGA_REGISTER_VERSION, | |
72 | FPGA_REGISTER_STATUS_CONTROL, | |
73 | FPGA_REGISTER_CHANNEL_SELECT_LOW, | |
74 | FPGA_REGISTER_CHANNEL_SELECT_HIGH, | |
75 | FPGA_REGISTER_SAMPLE_RATE_DIVISOR, | |
76 | FPGA_REGISTER_LED_BRIGHTNESS, | |
77 | FPGA_REGISTER_PRIMER_DATA1, | |
78 | FPGA_REGISTER_PRIMER_CONTROL, | |
79 | FPGA_REGISTER_MODE, | |
80 | FPGA_REGISTER_PRIMER_DATA2, | |
81 | FPGA_REGISTER_MAX = FPGA_REGISTER_PRIMER_DATA2 | |
82 | }; | |
83 | ||
84 | enum fpga_status_control_bit { | |
85 | FPGA_STATUS_CONTROL_BIT_RUNNING, | |
86 | FPGA_STATUS_CONTROL_BIT_UPDATE, | |
87 | FPGA_STATUS_CONTROL_BIT_UNKNOWN1, | |
88 | FPGA_STATUS_CONTROL_BIT_OVERFLOW, | |
89 | FPGA_STATUS_CONTROL_BIT_UNKNOWN2, | |
90 | FPGA_STATUS_CONTROL_BIT_MAX = FPGA_STATUS_CONTROL_BIT_UNKNOWN2 | |
91 | }; | |
92 | ||
93 | enum fpga_mode_bit { | |
94 | FPGA_MODE_BIT_CLOCK, | |
95 | FPGA_MODE_BIT_UNKNOWN1, | |
96 | FPGA_MODE_BIT_UNKNOWN2, | |
97 | FPGA_MODE_BIT_MAX = FPGA_MODE_BIT_UNKNOWN2 | |
98 | }; | |
99 | ||
100 | static const uint8_t fpga_register_map_old[FPGA_REGISTER_MAX + 1] = { | |
101 | [FPGA_REGISTER_VERSION] = 0, | |
102 | [FPGA_REGISTER_STATUS_CONTROL] = 1, | |
103 | [FPGA_REGISTER_CHANNEL_SELECT_LOW] = 2, | |
104 | [FPGA_REGISTER_CHANNEL_SELECT_HIGH] = 3, | |
105 | [FPGA_REGISTER_SAMPLE_RATE_DIVISOR] = 4, | |
106 | [FPGA_REGISTER_LED_BRIGHTNESS] = 5, | |
107 | [FPGA_REGISTER_PRIMER_DATA1] = 6, | |
108 | [FPGA_REGISTER_PRIMER_CONTROL] = 7, | |
109 | [FPGA_REGISTER_MODE] = 10, | |
110 | [FPGA_REGISTER_PRIMER_DATA2] = 12, | |
111 | }; | |
112 | ||
113 | static const uint8_t fpga_register_map_new[FPGA_REGISTER_MAX + 1] = { | |
114 | [FPGA_REGISTER_VERSION] = 7, | |
115 | [FPGA_REGISTER_STATUS_CONTROL] = 15, | |
116 | [FPGA_REGISTER_CHANNEL_SELECT_LOW] = 1, | |
117 | [FPGA_REGISTER_CHANNEL_SELECT_HIGH] = 6, | |
118 | [FPGA_REGISTER_SAMPLE_RATE_DIVISOR] = 11, | |
119 | [FPGA_REGISTER_LED_BRIGHTNESS] = 5, | |
120 | [FPGA_REGISTER_PRIMER_DATA1] = 14, | |
121 | [FPGA_REGISTER_PRIMER_CONTROL] = 2, | |
122 | [FPGA_REGISTER_MODE] = 4, | |
123 | [FPGA_REGISTER_PRIMER_DATA2] = 3, | |
124 | }; | |
125 | ||
126 | static const uint8_t fpga_status_control_bit_map_old[FPGA_STATUS_CONTROL_BIT_MAX + 1] = { | |
127 | [FPGA_STATUS_CONTROL_BIT_RUNNING] = 0x01, | |
128 | [FPGA_STATUS_CONTROL_BIT_UPDATE] = 0x02, | |
129 | [FPGA_STATUS_CONTROL_BIT_UNKNOWN1] = 0x08, | |
130 | [FPGA_STATUS_CONTROL_BIT_OVERFLOW] = 0x20, | |
131 | [FPGA_STATUS_CONTROL_BIT_UNKNOWN2] = 0x40, | |
132 | }; | |
133 | ||
134 | static const uint8_t fpga_status_control_bit_map_new[FPGA_STATUS_CONTROL_BIT_MAX + 1] = { | |
135 | [FPGA_STATUS_CONTROL_BIT_RUNNING] = 0x20, | |
136 | [FPGA_STATUS_CONTROL_BIT_UPDATE] = 0x08, | |
137 | [FPGA_STATUS_CONTROL_BIT_UNKNOWN1] = 0x10, | |
138 | [FPGA_STATUS_CONTROL_BIT_OVERFLOW] = 0x01, | |
139 | [FPGA_STATUS_CONTROL_BIT_UNKNOWN2] = 0x04, | |
140 | }; | |
141 | ||
142 | static const uint8_t fpga_mode_bit_map_old[FPGA_MODE_BIT_MAX + 1] = { | |
143 | [FPGA_MODE_BIT_CLOCK] = 0x01, | |
144 | [FPGA_MODE_BIT_UNKNOWN1] = 0x40, | |
145 | [FPGA_MODE_BIT_UNKNOWN2] = 0x80, | |
146 | }; | |
147 | ||
148 | static const uint8_t fpga_mode_bit_map_new[FPGA_MODE_BIT_MAX + 1] = { | |
149 | [FPGA_MODE_BIT_CLOCK] = 0x04, | |
150 | [FPGA_MODE_BIT_UNKNOWN1] = 0x80, | |
151 | [FPGA_MODE_BIT_UNKNOWN2] = 0x01, | |
152 | }; | |
153 | ||
154 | #define FPGA_REG(x) \ | |
155 | (devc->fpga_register_map[FPGA_REGISTER_ ## x]) | |
156 | ||
157 | #define FPGA_STATUS_CONTROL(x) \ | |
158 | (devc->fpga_status_control_bit_map[FPGA_STATUS_CONTROL_BIT_ ## x]) | |
159 | ||
160 | #define FPGA_MODE(x) \ | |
161 | (devc->fpga_mode_bit_map[FPGA_MODE_BIT_ ## x]) | |
162 | ||
15abcf0f MC |
163 | static void encrypt(uint8_t *dest, const uint8_t *src, uint8_t cnt) |
164 | { | |
165 | uint8_t state1 = 0x9b, state2 = 0x54; | |
96484e22 | 166 | uint8_t t, v; |
15abcf0f MC |
167 | int i; |
168 | ||
96484e22 UH |
169 | for (i = 0; i < cnt; i++) { |
170 | v = src[i]; | |
15abcf0f MC |
171 | t = (((v ^ state2 ^ 0x2b) - 0x05) ^ 0x35) - 0x39; |
172 | t = (((t ^ state1 ^ 0x5a) - 0xb0) ^ 0x38) - 0x45; | |
173 | dest[i] = state2 = t; | |
174 | state1 = v; | |
175 | } | |
176 | } | |
177 | ||
178 | static void decrypt(uint8_t *dest, const uint8_t *src, uint8_t cnt) | |
179 | { | |
180 | uint8_t state1 = 0x9b, state2 = 0x54; | |
96484e22 | 181 | uint8_t t, v; |
15abcf0f | 182 | int i; |
96484e22 UH |
183 | |
184 | for (i = 0; i < cnt; i++) { | |
185 | v = src[i]; | |
15abcf0f MC |
186 | t = (((v + 0x45) ^ 0x38) + 0xb0) ^ 0x5a ^ state1; |
187 | t = (((t + 0x39) ^ 0x35) + 0x05) ^ 0x2b ^ state2; | |
188 | dest[i] = state1 = t; | |
189 | state2 = v; | |
190 | } | |
191 | } | |
192 | ||
193 | static int do_ep1_command(const struct sr_dev_inst *sdi, | |
194 | const uint8_t *command, uint8_t cmd_len, | |
195 | uint8_t *reply, uint8_t reply_len) | |
196 | { | |
197 | uint8_t buf[64]; | |
198 | struct sr_usb_dev_inst *usb; | |
199 | int ret, xfer; | |
200 | ||
201 | usb = sdi->conn; | |
202 | ||
203 | if (cmd_len < 1 || cmd_len > 64 || reply_len > 64 || | |
98fec29e | 204 | !command || (reply_len > 0 && !reply)) |
15abcf0f MC |
205 | return SR_ERR_ARG; |
206 | ||
207 | encrypt(buf, command, cmd_len); | |
208 | ||
209 | ret = libusb_bulk_transfer(usb->devhdl, 1, buf, cmd_len, &xfer, 1000); | |
210 | if (ret != 0) { | |
96484e22 | 211 | sr_dbg("Failed to send EP1 command 0x%02x: %s.", |
15abcf0f MC |
212 | command[0], libusb_error_name(ret)); |
213 | return SR_ERR; | |
214 | } | |
215 | if (xfer != cmd_len) { | |
96484e22 UH |
216 | sr_dbg("Failed to send EP1 command 0x%02x: incorrect length " |
217 | "%d != %d.", xfer, cmd_len); | |
15abcf0f MC |
218 | return SR_ERR; |
219 | } | |
220 | ||
221 | if (reply_len == 0) | |
222 | return SR_OK; | |
223 | ||
96484e22 UH |
224 | ret = libusb_bulk_transfer(usb->devhdl, 0x80 | 1, buf, reply_len, |
225 | &xfer, 1000); | |
15abcf0f | 226 | if (ret != 0) { |
96484e22 | 227 | sr_dbg("Failed to receive reply to EP1 command 0x%02x: %s.", |
15abcf0f MC |
228 | command[0], libusb_error_name(ret)); |
229 | return SR_ERR; | |
230 | } | |
231 | if (xfer != reply_len) { | |
96484e22 UH |
232 | sr_dbg("Failed to receive reply to EP1 command 0x%02x: " |
233 | "incorrect length %d != %d.", xfer, reply_len); | |
15abcf0f MC |
234 | return SR_ERR; |
235 | } | |
236 | ||
237 | decrypt(reply, buf, reply_len); | |
238 | ||
239 | return SR_OK; | |
240 | } | |
241 | ||
242 | static int read_eeprom(const struct sr_dev_inst *sdi, | |
243 | uint8_t address, uint8_t length, uint8_t *buf) | |
244 | { | |
245 | uint8_t command[5] = { | |
246 | COMMAND_READ_EEPROM, | |
247 | READ_EEPROM_COOKIE1, | |
248 | READ_EEPROM_COOKIE2, | |
249 | address, | |
250 | length, | |
251 | }; | |
252 | ||
253 | return do_ep1_command(sdi, command, 5, buf, length); | |
254 | } | |
255 | ||
256 | static int upload_led_table(const struct sr_dev_inst *sdi, | |
257 | const uint8_t *table, uint8_t offset, uint8_t cnt) | |
258 | { | |
96484e22 | 259 | uint8_t chunk, command[64]; |
15abcf0f MC |
260 | int ret; |
261 | ||
98fec29e | 262 | if (cnt < 1 || cnt + offset > 64 || !table) |
15abcf0f MC |
263 | return SR_ERR_ARG; |
264 | ||
265 | while (cnt > 0) { | |
96484e22 | 266 | chunk = (cnt > 32 ? 32 : cnt); |
15abcf0f MC |
267 | |
268 | command[0] = COMMAND_WRITE_LED_TABLE; | |
269 | command[1] = offset; | |
270 | command[2] = chunk; | |
96484e22 | 271 | memcpy(command + 3, table, chunk); |
15abcf0f | 272 | |
96484e22 UH |
273 | ret = do_ep1_command(sdi, command, 3 + chunk, NULL, 0); |
274 | if (ret != SR_OK) | |
15abcf0f MC |
275 | return ret; |
276 | ||
277 | table += chunk; | |
278 | offset += chunk; | |
279 | cnt -= chunk; | |
280 | } | |
281 | ||
282 | return SR_OK; | |
283 | } | |
284 | ||
285 | static int set_led_mode(const struct sr_dev_inst *sdi, | |
286 | uint8_t animate, uint16_t t2reload, uint8_t div, | |
287 | uint8_t repeat) | |
288 | { | |
289 | uint8_t command[6] = { | |
290 | COMMAND_SET_LED_MODE, | |
291 | animate, | |
96484e22 UH |
292 | t2reload & 0xff, |
293 | t2reload >> 8, | |
15abcf0f MC |
294 | div, |
295 | repeat, | |
296 | }; | |
297 | ||
298 | return do_ep1_command(sdi, command, 6, NULL, 0); | |
299 | } | |
300 | ||
301 | static int read_fpga_register(const struct sr_dev_inst *sdi, | |
302 | uint8_t address, uint8_t *value) | |
303 | { | |
304 | uint8_t command[3] = { | |
305 | COMMAND_FPGA_READ_REGISTER, | |
306 | 1, | |
307 | address, | |
308 | }; | |
309 | ||
310 | return do_ep1_command(sdi, command, 3, value, 1); | |
311 | } | |
312 | ||
313 | static int write_fpga_registers(const struct sr_dev_inst *sdi, | |
314 | uint8_t (*regs)[2], uint8_t cnt) | |
315 | { | |
316 | uint8_t command[64]; | |
317 | int i; | |
318 | ||
319 | if (cnt < 1 || cnt > 31) | |
320 | return SR_ERR_ARG; | |
321 | ||
322 | command[0] = COMMAND_FPGA_WRITE_REGISTER; | |
323 | command[1] = cnt; | |
96484e22 UH |
324 | for (i = 0; i < cnt; i++) { |
325 | command[2 + 2 * i] = regs[i][0]; | |
326 | command[3 + 2 * i] = regs[i][1]; | |
15abcf0f MC |
327 | } |
328 | ||
96484e22 | 329 | return do_ep1_command(sdi, command, 2 * (cnt + 1), NULL, 0); |
15abcf0f MC |
330 | } |
331 | ||
332 | static int write_fpga_register(const struct sr_dev_inst *sdi, | |
333 | uint8_t address, uint8_t value) | |
334 | { | |
335 | uint8_t regs[2] = { address, value }; | |
96484e22 | 336 | |
15abcf0f MC |
337 | return write_fpga_registers(sdi, ®s, 1); |
338 | } | |
339 | ||
15abcf0f MC |
340 | static uint8_t map_eeprom_data(uint8_t v) |
341 | { | |
186dde8d | 342 | return (((v ^ 0x80) + 0x44) ^ 0xd5) + 0x69; |
15abcf0f MC |
343 | } |
344 | ||
c8681396 MC |
345 | static int setup_register_mapping(const struct sr_dev_inst *sdi) |
346 | { | |
347 | struct dev_context *devc; | |
348 | int ret; | |
349 | ||
350 | devc = sdi->priv; | |
351 | ||
352 | if (devc->fpga_variant != FPGA_VARIANT_MCUPRO) { | |
353 | uint8_t reg0, reg7; | |
354 | ||
355 | /* | |
356 | * Check for newer bitstream version by polling the | |
357 | * version register at the old and new location. | |
358 | */ | |
359 | ||
360 | if ((ret = read_fpga_register(sdi, 0 /* No mapping */, ®0)) != SR_OK) | |
361 | return ret; | |
362 | ||
363 | if ((ret = read_fpga_register(sdi, 7 /* No mapping */, ®7)) != SR_OK) | |
364 | return ret; | |
365 | ||
366 | if (reg0 == 0 && reg7 > 0x10) | |
367 | devc->fpga_variant = FPGA_VARIANT_ORIGINAL_NEW_BITSTREAM; | |
368 | else | |
369 | devc->fpga_variant = FPGA_VARIANT_ORIGINAL; | |
370 | } | |
371 | ||
372 | if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL_NEW_BITSTREAM) { | |
373 | devc->fpga_register_map = fpga_register_map_new; | |
374 | devc->fpga_status_control_bit_map = fpga_status_control_bit_map_new; | |
375 | devc->fpga_mode_bit_map = fpga_mode_bit_map_new; | |
376 | } else { | |
377 | devc->fpga_register_map = fpga_register_map_old; | |
378 | devc->fpga_status_control_bit_map = fpga_status_control_bit_map_old; | |
379 | devc->fpga_mode_bit_map = fpga_mode_bit_map_old; | |
380 | } | |
381 | ||
382 | return SR_OK; | |
383 | } | |
384 | ||
15abcf0f MC |
385 | static int prime_fpga(const struct sr_dev_inst *sdi) |
386 | { | |
c8681396 | 387 | struct dev_context *devc = sdi->priv; |
15abcf0f | 388 | uint8_t eeprom_data[16]; |
c8681396 | 389 | uint8_t old_mode_reg, version; |
15abcf0f | 390 | uint8_t regs[8][2] = { |
c8681396 MC |
391 | {FPGA_REG(MODE), 0x00}, |
392 | {FPGA_REG(MODE), FPGA_MODE(UNKNOWN1)}, | |
393 | {FPGA_REG(PRIMER_DATA2), 0}, | |
394 | {FPGA_REG(MODE), FPGA_MODE(UNKNOWN1) | FPGA_MODE(UNKNOWN2)}, | |
395 | {FPGA_REG(MODE), FPGA_MODE(UNKNOWN1)}, | |
396 | {FPGA_REG(PRIMER_DATA1), 0}, | |
397 | {FPGA_REG(PRIMER_CONTROL), 1}, | |
398 | {FPGA_REG(PRIMER_CONTROL), 0} | |
15abcf0f MC |
399 | }; |
400 | int i, ret; | |
401 | ||
402 | if ((ret = read_eeprom(sdi, 16, 16, eeprom_data)) != SR_OK) | |
403 | return ret; | |
404 | ||
c8681396 | 405 | if ((ret = read_fpga_register(sdi, FPGA_REG(MODE), &old_mode_reg)) != SR_OK) |
15abcf0f MC |
406 | return ret; |
407 | ||
c8681396 MC |
408 | regs[0][1] = (old_mode_reg &= ~FPGA_MODE(UNKNOWN2)); |
409 | regs[1][1] |= old_mode_reg; | |
410 | regs[3][1] |= old_mode_reg; | |
411 | regs[4][1] |= old_mode_reg; | |
186dde8d | 412 | |
96484e22 | 413 | for (i = 0; i < 16; i++) { |
15abcf0f MC |
414 | regs[2][1] = eeprom_data[i]; |
415 | regs[5][1] = map_eeprom_data(eeprom_data[i]); | |
416 | if (i) | |
417 | ret = write_fpga_registers(sdi, ®s[2], 6); | |
418 | else | |
419 | ret = write_fpga_registers(sdi, ®s[0], 8); | |
420 | if (ret != SR_OK) | |
421 | return ret; | |
422 | } | |
423 | ||
c8681396 | 424 | if ((ret = write_fpga_register(sdi, FPGA_REG(MODE), old_mode_reg)) != SR_OK) |
15abcf0f MC |
425 | return ret; |
426 | ||
c8681396 | 427 | if ((ret = read_fpga_register(sdi, FPGA_REG(VERSION), &version)) != SR_OK) |
15abcf0f MC |
428 | return ret; |
429 | ||
c8681396 | 430 | if (version != 0x10 && version != 0x13 && version != 0x40 && version != 0x41) { |
6f479a0a | 431 | sr_err("Unsupported FPGA version: 0x%02x.", version); |
15abcf0f MC |
432 | return SR_ERR; |
433 | } | |
434 | ||
435 | return SR_OK; | |
436 | } | |
437 | ||
438 | static void make_heartbeat(uint8_t *table, int len) | |
439 | { | |
440 | int i, j; | |
441 | ||
442 | memset(table, 0, len); | |
443 | len >>= 3; | |
96484e22 UH |
444 | for (i = 0; i < 2; i++) |
445 | for (j = 0; j < len; j++) | |
bbc42811 | 446 | *table++ = sin(j * G_PI / len) * 255; |
15abcf0f MC |
447 | } |
448 | ||
449 | static int configure_led(const struct sr_dev_inst *sdi) | |
450 | { | |
451 | uint8_t table[64]; | |
452 | int ret; | |
453 | ||
454 | make_heartbeat(table, 64); | |
455 | if ((ret = upload_led_table(sdi, table, 0, 64)) != SR_OK) | |
456 | return ret; | |
457 | ||
458 | return set_led_mode(sdi, 1, 6250, 0, 1); | |
459 | } | |
460 | ||
461 | static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, | |
462 | enum voltage_range vrange) | |
463 | { | |
464 | struct dev_context *devc; | |
465 | int offset, chunksize, ret; | |
466 | const char *filename; | |
96484e22 | 467 | uint8_t len, buf[256 * 62], command[64]; |
15abcf0f | 468 | FILE *fw; |
15abcf0f MC |
469 | |
470 | devc = sdi->priv; | |
471 | ||
472 | if (devc->cur_voltage_range == vrange) | |
473 | return SR_OK; | |
474 | ||
c8681396 | 475 | if (devc->fpga_variant != FPGA_VARIANT_MCUPRO) { |
6f479a0a PZ |
476 | switch (vrange) { |
477 | case VOLTAGE_RANGE_18_33_V: | |
478 | filename = FPGA_FIRMWARE_18; | |
479 | break; | |
480 | case VOLTAGE_RANGE_5_V: | |
481 | filename = FPGA_FIRMWARE_33; | |
482 | break; | |
483 | default: | |
484 | sr_err("Unsupported voltage range."); | |
485 | return SR_ERR; | |
486 | } | |
15abcf0f | 487 | |
6f479a0a | 488 | sr_info("Uploading FPGA bitstream at %s.", filename); |
98fec29e | 489 | if (!(fw = g_fopen(filename, "rb"))) { |
6f479a0a PZ |
490 | sr_err("Unable to open bitstream file %s for reading: %s.", |
491 | filename, strerror(errno)); | |
492 | return SR_ERR; | |
493 | } | |
15abcf0f | 494 | |
6f479a0a PZ |
495 | buf[0] = COMMAND_FPGA_UPLOAD_INIT; |
496 | if ((ret = do_ep1_command(sdi, buf, 1, NULL, 0)) != SR_OK) { | |
497 | fclose(fw); | |
498 | return ret; | |
499 | } | |
15abcf0f | 500 | |
6f479a0a PZ |
501 | while (1) { |
502 | chunksize = fread(buf, 1, sizeof(buf), fw); | |
503 | if (chunksize == 0) | |
504 | break; | |
505 | ||
506 | for (offset = 0; offset < chunksize; offset += 62) { | |
507 | len = (offset + 62 > chunksize ? | |
508 | chunksize - offset : 62); | |
509 | command[0] = COMMAND_FPGA_UPLOAD_SEND_DATA; | |
510 | command[1] = len; | |
511 | memcpy(command + 2, buf + offset, len); | |
512 | ret = do_ep1_command(sdi, command, len + 2, NULL, 0); | |
513 | if (ret != SR_OK) { | |
514 | fclose(fw); | |
515 | return ret; | |
516 | } | |
15abcf0f | 517 | } |
15abcf0f | 518 | |
6f479a0a PZ |
519 | sr_info("Uploaded %d bytes.", chunksize); |
520 | } | |
521 | fclose(fw); | |
522 | sr_info("FPGA bitstream upload done."); | |
15abcf0f | 523 | } |
15abcf0f | 524 | |
c8681396 MC |
525 | /* This needs to be called before accessing any FPGA registers. */ |
526 | if ((ret = setup_register_mapping(sdi)) != SR_OK) | |
527 | return ret; | |
528 | ||
15abcf0f MC |
529 | if ((ret = prime_fpga(sdi)) != SR_OK) |
530 | return ret; | |
531 | ||
532 | if ((ret = configure_led(sdi)) != SR_OK) | |
533 | return ret; | |
534 | ||
15abcf0f MC |
535 | devc->cur_voltage_range = vrange; |
536 | return SR_OK; | |
537 | } | |
538 | ||
7b5daad4 | 539 | static int abort_acquisition_sync(const struct sr_dev_inst *sdi) |
15abcf0f MC |
540 | { |
541 | static const uint8_t command[2] = { | |
542 | COMMAND_ABORT_ACQUISITION_SYNC, | |
543 | ABORT_ACQUISITION_SYNC_PATTERN, | |
544 | }; | |
545 | uint8_t reply, expected_reply; | |
546 | int ret; | |
547 | ||
548 | if ((ret = do_ep1_command(sdi, command, 2, &reply, 1)) != SR_OK) | |
549 | return ret; | |
550 | ||
551 | expected_reply = ~command[1]; | |
552 | if (reply != expected_reply) { | |
553 | sr_err("Invalid response for abort acquisition command: " | |
96484e22 | 554 | "0x%02x != 0x%02x.", reply, expected_reply); |
15abcf0f MC |
555 | return SR_ERR; |
556 | } | |
557 | ||
558 | return SR_OK; | |
559 | } | |
560 | ||
96484e22 UH |
561 | SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi, |
562 | uint64_t samplerate, uint16_t channels) | |
7b5daad4 | 563 | { |
c8681396 | 564 | uint8_t clock_select, sta_con_reg, mode_reg; |
7b5daad4 MC |
565 | uint64_t div; |
566 | int i, ret, nchan = 0; | |
db11d7d2 MC |
567 | struct dev_context *devc; |
568 | ||
569 | devc = sdi->priv; | |
7b5daad4 MC |
570 | |
571 | if (samplerate == 0 || samplerate > MAX_SAMPLE_RATE) { | |
572 | sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate); | |
573 | return SR_ERR; | |
574 | } | |
575 | ||
576 | if (BASE_CLOCK_0_FREQ % samplerate == 0 && | |
577 | (div = BASE_CLOCK_0_FREQ / samplerate) <= 256) { | |
578 | clock_select = 0; | |
579 | } else if (BASE_CLOCK_1_FREQ % samplerate == 0 && | |
580 | (div = BASE_CLOCK_1_FREQ / samplerate) <= 256) { | |
581 | clock_select = 1; | |
582 | } else { | |
583 | sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate); | |
584 | return SR_ERR; | |
585 | } | |
586 | ||
96484e22 UH |
587 | for (i = 0; i < 16; i++) |
588 | if (channels & (1U << i)) | |
7b5daad4 MC |
589 | nchan++; |
590 | ||
591 | if ((nchan >= 13 && samplerate > MAX_13CH_SAMPLE_RATE) || | |
592 | (nchan >= 10 && samplerate > MAX_10CH_SAMPLE_RATE) || | |
593 | (nchan >= 8 && samplerate > MAX_8CH_SAMPLE_RATE) || | |
594 | (nchan >= 7 && samplerate > MAX_7CH_SAMPLE_RATE) || | |
595 | (nchan >= 4 && samplerate > MAX_4CH_SAMPLE_RATE)) { | |
596 | sr_err("Unable to sample at %" PRIu64 "Hz " | |
597 | "with this many channels.", samplerate); | |
598 | return SR_ERR; | |
599 | } | |
600 | ||
96484e22 UH |
601 | ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range); |
602 | if (ret != SR_OK) | |
db11d7d2 MC |
603 | return ret; |
604 | ||
c8681396 | 605 | if ((ret = read_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), &sta_con_reg)) != SR_OK) |
7b5daad4 MC |
606 | return ret; |
607 | ||
7754fb4d | 608 | /* Ignore FIFO overflow on previous capture */ |
c8681396 | 609 | sta_con_reg &= ~FPGA_STATUS_CONTROL(OVERFLOW); |
7754fb4d | 610 | |
c8681396 MC |
611 | if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && sta_con_reg != FPGA_STATUS_CONTROL(UNKNOWN1)) { |
612 | sr_dbg("Invalid state at acquisition setup register 1: 0x%02x != 0x%02x. " | |
613 | "Proceeding anyway.", sta_con_reg, FPGA_STATUS_CONTROL(UNKNOWN1)); | |
7b5daad4 MC |
614 | } |
615 | ||
c8681396 | 616 | if ((ret = write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), FPGA_STATUS_CONTROL(UNKNOWN2))) != SR_OK) |
7b5daad4 MC |
617 | return ret; |
618 | ||
c8681396 | 619 | if ((ret = write_fpga_register(sdi, FPGA_REG(MODE), (clock_select? FPGA_MODE(CLOCK) : 0))) != SR_OK) |
7b5daad4 MC |
620 | return ret; |
621 | ||
c8681396 | 622 | if ((ret = write_fpga_register(sdi, FPGA_REG(SAMPLE_RATE_DIVISOR), (uint8_t)(div - 1))) != SR_OK) |
7b5daad4 MC |
623 | return ret; |
624 | ||
c8681396 | 625 | if ((ret = write_fpga_register(sdi, FPGA_REG(CHANNEL_SELECT_LOW), (uint8_t)(channels & 0xff))) != SR_OK) |
7b5daad4 MC |
626 | return ret; |
627 | ||
c8681396 | 628 | if ((ret = write_fpga_register(sdi, FPGA_REG(CHANNEL_SELECT_HIGH), (uint8_t)(channels >> 8))) != SR_OK) |
7b5daad4 MC |
629 | return ret; |
630 | ||
c8681396 | 631 | if ((ret = write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), FPGA_STATUS_CONTROL(UNKNOWN2) | FPGA_STATUS_CONTROL(UPDATE))) != SR_OK) |
7b5daad4 MC |
632 | return ret; |
633 | ||
c8681396 | 634 | if ((ret = write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), FPGA_STATUS_CONTROL(UNKNOWN2))) != SR_OK) |
7b5daad4 MC |
635 | return ret; |
636 | ||
c8681396 | 637 | if ((ret = read_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), &sta_con_reg)) != SR_OK) |
7b5daad4 MC |
638 | return ret; |
639 | ||
c8681396 MC |
640 | if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && sta_con_reg != (FPGA_STATUS_CONTROL(UNKNOWN2) | FPGA_STATUS_CONTROL(UNKNOWN1))) { |
641 | sr_dbg("Invalid state at acquisition setup register 1: 0x%02x != 0x%02x. " | |
642 | "Proceeding anyway.", sta_con_reg, FPGA_STATUS_CONTROL(UNKNOWN2) | FPGA_STATUS_CONTROL(UNKNOWN1)); | |
7b5daad4 MC |
643 | } |
644 | ||
c8681396 | 645 | if ((ret = read_fpga_register(sdi, FPGA_REG(MODE), &mode_reg)) != SR_OK) |
7b5daad4 MC |
646 | return ret; |
647 | ||
c8681396 | 648 | if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && mode_reg != (clock_select? FPGA_MODE(CLOCK) : 0)) { |
a11e10ec | 649 | sr_dbg("Invalid state at acquisition setup register 10: 0x%02x != 0x%02x. " |
c8681396 | 650 | "Proceeding anyway.", mode_reg, (clock_select? FPGA_MODE(CLOCK) : 0)); |
7b5daad4 MC |
651 | } |
652 | ||
653 | return SR_OK; | |
654 | } | |
655 | ||
96484e22 | 656 | SR_PRIV int logic16_start_acquisition(const struct sr_dev_inst *sdi) |
7b5daad4 MC |
657 | { |
658 | static const uint8_t command[1] = { | |
659 | COMMAND_START_ACQUISITION, | |
660 | }; | |
661 | int ret; | |
c8681396 MC |
662 | struct dev_context *devc; |
663 | ||
664 | devc = sdi->priv; | |
7b5daad4 MC |
665 | |
666 | if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK) | |
667 | return ret; | |
668 | ||
c8681396 | 669 | return write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), FPGA_STATUS_CONTROL(UNKNOWN2) | FPGA_STATUS_CONTROL(RUNNING)); |
7b5daad4 MC |
670 | } |
671 | ||
96484e22 | 672 | SR_PRIV int logic16_abort_acquisition(const struct sr_dev_inst *sdi) |
7b5daad4 MC |
673 | { |
674 | static const uint8_t command[1] = { | |
675 | COMMAND_ABORT_ACQUISITION_ASYNC, | |
676 | }; | |
677 | int ret; | |
c8681396 | 678 | uint8_t sta_con_reg; |
6f479a0a PZ |
679 | struct dev_context *devc; |
680 | ||
681 | devc = sdi->priv; | |
7b5daad4 MC |
682 | |
683 | if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK) | |
684 | return ret; | |
685 | ||
c8681396 | 686 | if ((ret = write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), 0x00)) != SR_OK) |
7b5daad4 MC |
687 | return ret; |
688 | ||
c8681396 | 689 | if ((ret = read_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), &sta_con_reg)) != SR_OK) |
7b5daad4 MC |
690 | return ret; |
691 | ||
c8681396 MC |
692 | if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && (sta_con_reg & ~FPGA_STATUS_CONTROL(OVERFLOW)) != FPGA_STATUS_CONTROL(UNKNOWN1)) { |
693 | sr_dbg("Invalid state at acquisition stop: 0x%02x != 0x%02x.", sta_con_reg & ~0x20, FPGA_STATUS_CONTROL(UNKNOWN1)); | |
7b5daad4 MC |
694 | return SR_ERR; |
695 | } | |
696 | ||
7b5daad4 | 697 | |
c8681396 MC |
698 | if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL) { |
699 | uint8_t reg8, reg9; | |
700 | ||
701 | if ((ret = read_fpga_register(sdi, 8, ®8)) != SR_OK) | |
702 | return ret; | |
703 | ||
704 | if ((ret = read_fpga_register(sdi, 9, ®9)) != SR_OK) | |
705 | return ret; | |
706 | } | |
7b5daad4 | 707 | |
c8681396 | 708 | if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && sta_con_reg & FPGA_STATUS_CONTROL(OVERFLOW)) { |
7754fb4d MC |
709 | sr_warn("FIFO overflow, capture data may be truncated."); |
710 | return SR_ERR; | |
711 | } | |
712 | ||
7b5daad4 MC |
713 | return SR_OK; |
714 | } | |
715 | ||
96484e22 | 716 | SR_PRIV int logic16_init_device(const struct sr_dev_inst *sdi) |
15abcf0f | 717 | { |
6f479a0a | 718 | uint8_t version; |
15abcf0f MC |
719 | struct dev_context *devc; |
720 | int ret; | |
721 | ||
722 | devc = sdi->priv; | |
723 | ||
724 | devc->cur_voltage_range = VOLTAGE_RANGE_UNKNOWN; | |
725 | ||
7b5daad4 | 726 | if ((ret = abort_acquisition_sync(sdi)) != SR_OK) |
15abcf0f MC |
727 | return ret; |
728 | ||
729 | if ((ret = read_eeprom(sdi, 8, 8, devc->eeprom_data)) != SR_OK) | |
730 | return ret; | |
731 | ||
6f479a0a PZ |
732 | /* mcupro Saleae16 has firmware pre-stored in FPGA. |
733 | So, we can query it right away. */ | |
c8681396 | 734 | if (read_fpga_register(sdi, 0 /* No mapping */, &version) == SR_OK && |
6f479a0a PZ |
735 | (version == 0x40 || version == 0x41)) { |
736 | sr_info("mcupro Saleae16 detected."); | |
737 | devc->fpga_variant = FPGA_VARIANT_MCUPRO; | |
738 | } else { | |
739 | sr_info("Original Saleae Logic16 detected."); | |
740 | devc->fpga_variant = FPGA_VARIANT_ORIGINAL; | |
741 | } | |
742 | ||
96484e22 UH |
743 | ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range); |
744 | if (ret != SR_OK) | |
15abcf0f MC |
745 | return ret; |
746 | ||
747 | return SR_OK; | |
748 | } | |
749 | ||
102f1239 | 750 | static void finish_acquisition(struct sr_dev_inst *sdi) |
7b5daad4 MC |
751 | { |
752 | struct sr_datafeed_packet packet; | |
102f1239 BV |
753 | struct dev_context *devc; |
754 | ||
755 | devc = sdi->priv; | |
7b5daad4 MC |
756 | |
757 | /* Terminate session. */ | |
758 | packet.type = SR_DF_END; | |
759 | sr_session_send(devc->cb_data, &packet); | |
760 | ||
761 | /* Remove fds from polling. */ | |
102f1239 | 762 | usb_source_remove(sdi->session, devc->ctx); |
7b5daad4 MC |
763 | |
764 | devc->num_transfers = 0; | |
765 | g_free(devc->transfers); | |
766 | g_free(devc->convbuffer); | |
863357fb BV |
767 | if (devc->stl) { |
768 | soft_trigger_logic_free(devc->stl); | |
769 | devc->stl = NULL; | |
770 | } | |
7b5daad4 MC |
771 | } |
772 | ||
773 | static void free_transfer(struct libusb_transfer *transfer) | |
774 | { | |
102f1239 | 775 | struct sr_dev_inst *sdi; |
7b5daad4 MC |
776 | struct dev_context *devc; |
777 | unsigned int i; | |
778 | ||
102f1239 BV |
779 | sdi = transfer->user_data; |
780 | devc = sdi->priv; | |
7b5daad4 MC |
781 | |
782 | g_free(transfer->buffer); | |
783 | transfer->buffer = NULL; | |
784 | libusb_free_transfer(transfer); | |
785 | ||
786 | for (i = 0; i < devc->num_transfers; i++) { | |
787 | if (devc->transfers[i] == transfer) { | |
788 | devc->transfers[i] = NULL; | |
789 | break; | |
790 | } | |
791 | } | |
792 | ||
793 | devc->submitted_transfers--; | |
794 | if (devc->submitted_transfers == 0) | |
102f1239 | 795 | finish_acquisition(sdi); |
7b5daad4 MC |
796 | } |
797 | ||
798 | static void resubmit_transfer(struct libusb_transfer *transfer) | |
799 | { | |
800 | int ret; | |
801 | ||
802 | if ((ret = libusb_submit_transfer(transfer)) == LIBUSB_SUCCESS) | |
803 | return; | |
804 | ||
805 | free_transfer(transfer); | |
806 | /* TODO: Stop session? */ | |
807 | ||
808 | sr_err("%s: %s", __func__, libusb_error_name(ret)); | |
809 | } | |
810 | ||
a989cdbe BV |
811 | static size_t convert_sample_data(struct dev_context *devc, |
812 | uint8_t *dest, size_t destcnt, const uint8_t *src, size_t srccnt) | |
c463dcf0 | 813 | { |
7b5daad4 MC |
814 | uint16_t *channel_data; |
815 | int i, cur_channel; | |
816 | size_t ret = 0; | |
96484e22 | 817 | uint16_t sample, channel_mask; |
7b5daad4 MC |
818 | |
819 | srccnt /= 2; | |
820 | ||
821 | channel_data = devc->channel_data; | |
822 | cur_channel = devc->cur_channel; | |
823 | ||
96484e22 | 824 | while (srccnt--) { |
7b5daad4 MC |
825 | sample = src[0] | (src[1] << 8); |
826 | src += 2; | |
827 | ||
828 | channel_mask = devc->channel_masks[cur_channel]; | |
829 | ||
96484e22 | 830 | for (i = 15; i >= 0; --i, sample >>= 1) |
7b5daad4 MC |
831 | if (sample & 1) |
832 | channel_data[i] |= channel_mask; | |
833 | ||
834 | if (++cur_channel == devc->num_channels) { | |
835 | cur_channel = 0; | |
96484e22 | 836 | if (destcnt < 16 * 2) { |
7b5daad4 MC |
837 | sr_err("Conversion buffer too small!"); |
838 | break; | |
839 | } | |
96484e22 UH |
840 | memcpy(dest, channel_data, 16 * 2); |
841 | memset(channel_data, 0, 16 * 2); | |
842 | dest += 16 * 2; | |
1b822521 | 843 | ret += 16; |
96484e22 | 844 | destcnt -= 16 * 2; |
7b5daad4 MC |
845 | } |
846 | } | |
847 | ||
848 | devc->cur_channel = cur_channel; | |
c463dcf0 | 849 | |
7b5daad4 MC |
850 | return ret; |
851 | } | |
852 | ||
55462b8b | 853 | SR_PRIV void LIBUSB_CALL logic16_receive_transfer(struct libusb_transfer *transfer) |
7b5daad4 MC |
854 | { |
855 | gboolean packet_has_error = FALSE; | |
856 | struct sr_datafeed_packet packet; | |
857 | struct sr_datafeed_logic logic; | |
102f1239 | 858 | struct sr_dev_inst *sdi; |
c463dcf0 | 859 | struct dev_context *devc; |
863357fb BV |
860 | size_t new_samples, num_samples; |
861 | int trigger_offset; | |
5a971f66 | 862 | int pre_trigger_samples; |
7b5daad4 | 863 | |
102f1239 BV |
864 | sdi = transfer->user_data; |
865 | devc = sdi->priv; | |
7b5daad4 MC |
866 | |
867 | /* | |
868 | * If acquisition has already ended, just free any queued up | |
869 | * transfer that come in. | |
870 | */ | |
863357fb | 871 | if (devc->sent_samples < 0) { |
7b5daad4 MC |
872 | free_transfer(transfer); |
873 | return; | |
874 | } | |
875 | ||
974fb0ff BV |
876 | sr_info("receive_transfer(): status %s received %d bytes.", |
877 | libusb_error_name(transfer->status), transfer->actual_length); | |
7b5daad4 MC |
878 | |
879 | switch (transfer->status) { | |
880 | case LIBUSB_TRANSFER_NO_DEVICE: | |
863357fb | 881 | devc->sent_samples = -2; |
7b5daad4 MC |
882 | free_transfer(transfer); |
883 | return; | |
884 | case LIBUSB_TRANSFER_COMPLETED: | |
885 | case LIBUSB_TRANSFER_TIMED_OUT: /* We may have received some data though. */ | |
886 | break; | |
887 | default: | |
888 | packet_has_error = TRUE; | |
889 | break; | |
890 | } | |
c463dcf0 | 891 | |
7b5daad4 | 892 | if (transfer->actual_length & 1) { |
96484e22 UH |
893 | sr_err("Got an odd number of bytes from the device. " |
894 | "This should not happen."); | |
895 | /* Bail out right away. */ | |
7b5daad4 MC |
896 | packet_has_error = TRUE; |
897 | devc->empty_transfer_count = MAX_EMPTY_TRANSFERS; | |
898 | } | |
c463dcf0 | 899 | |
7b5daad4 MC |
900 | if (transfer->actual_length == 0 || packet_has_error) { |
901 | devc->empty_transfer_count++; | |
902 | if (devc->empty_transfer_count > MAX_EMPTY_TRANSFERS) { | |
903 | /* | |
904 | * The FX2 gave up. End the acquisition, the frontend | |
905 | * will work out that the samplecount is short. | |
906 | */ | |
863357fb | 907 | devc->sent_samples = -2; |
7b5daad4 MC |
908 | free_transfer(transfer); |
909 | } else { | |
910 | resubmit_transfer(transfer); | |
911 | } | |
912 | return; | |
913 | } else { | |
914 | devc->empty_transfer_count = 0; | |
915 | } | |
c463dcf0 | 916 | |
863357fb | 917 | new_samples = convert_sample_data(devc, devc->convbuffer, |
a989cdbe | 918 | devc->convbuffer_size, transfer->buffer, transfer->actual_length); |
863357fb BV |
919 | |
920 | if (new_samples > 0) { | |
921 | if (devc->trigger_fired) { | |
922 | /* Send the incoming transfer to the session bus. */ | |
923 | packet.type = SR_DF_LOGIC; | |
924 | packet.payload = &logic; | |
925 | if (devc->limit_samples && | |
926 | new_samples > devc->limit_samples - devc->sent_samples) | |
927 | new_samples = devc->limit_samples - devc->sent_samples; | |
a989cdbe BV |
928 | logic.length = new_samples * 2; |
929 | logic.unitsize = 2; | |
863357fb BV |
930 | logic.data = devc->convbuffer; |
931 | sr_session_send(devc->cb_data, &packet); | |
932 | devc->sent_samples += new_samples; | |
933 | } else { | |
934 | trigger_offset = soft_trigger_logic_check(devc->stl, | |
5a971f66 | 935 | devc->convbuffer, new_samples * 2, &pre_trigger_samples); |
863357fb | 936 | if (trigger_offset > -1) { |
5a971f66 | 937 | devc->sent_samples += pre_trigger_samples; |
863357fb BV |
938 | packet.type = SR_DF_LOGIC; |
939 | packet.payload = &logic; | |
940 | num_samples = new_samples - trigger_offset; | |
941 | if (devc->limit_samples && | |
942 | num_samples > devc->limit_samples - devc->sent_samples) | |
943 | num_samples = devc->limit_samples - devc->sent_samples; | |
a989cdbe BV |
944 | logic.length = num_samples * 2; |
945 | logic.unitsize = 2; | |
946 | logic.data = devc->convbuffer + trigger_offset * 2; | |
863357fb BV |
947 | sr_session_send(devc->cb_data, &packet); |
948 | devc->sent_samples += num_samples; | |
949 | ||
950 | devc->trigger_fired = TRUE; | |
951 | } | |
2db95906 MC |
952 | } |
953 | ||
7b5daad4 | 954 | if (devc->limit_samples && |
863357fb BV |
955 | (uint64_t)devc->sent_samples >= devc->limit_samples) { |
956 | devc->sent_samples = -2; | |
7b5daad4 MC |
957 | free_transfer(transfer); |
958 | return; | |
959 | } | |
c463dcf0 MC |
960 | } |
961 | ||
7b5daad4 | 962 | resubmit_transfer(transfer); |
c463dcf0 | 963 | } |